CN101042923A - sense amplifier - Google Patents

Abstract

The present invention is a sense amplifier including: a first current mirror unit coupled to a high voltage source for outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source for outputting a third current according to a second reference current; a first impedance element coupled to the second current and a low voltage source; a second impedance element coupled to the third current and the low voltage source; a third current mirror unit coupled to the first current, the second current and the third current, wherein the third current mirror unit makes the current flowing through the first impedance element be the first current and the current flowing through the second impedance element be a fourth current according to the first current being a reference current of the third current mirror unit.

Description

sense amplifier

technical field

The invention relates to a sense amplifier, in particular to a sense amplifier capable of increasing the read range of the read voltage.

Background technique

Since the non-volatile memory can store data for a long time without power supply, it has become the mainstream of the current memory. For Magnetoresistive RAM (MRAM) and resistive RAM (Resistive RAM, RAM), the way of storing data is to distinguish between 0 and 1 data by using the different resistance values of memory cells in the memory. To read the data in the magnetoresistive memory and the resistive memory is to use the comparison with the current flowing through a reference memory unit to obtain the data stored in the memory unit. Generally speaking, the way of reading is to use a sense amplifier (Sense Amplifier, SA) to read the current in the memory cell, so as to know the status of the memory cell. Because the logic state 0 and 1 in the memory cell have different resistance values, after a bias voltage is applied to the memory cell, there will be different currents, and the logic state 0 or 1 in the memory cell can be obtained by judging the magnitude of the current.

In addition, the reading speed of the memory cell also has a considerable relationship with the sense amplifier. The shorter the time required for the sense amplifier to judge the state of the memory cell, the better, and the read time is not only dependent on the sense amplifier itself, but also related to the current flowing through the memory cell.

FIG. 1 is a schematic circuit diagram of a conventional sense amplifier. The control current source 11 is coupled to a high voltage source VDD and the drain and gate of the transistor N11. A resistor element R is coupled to the source of the transistor N11 and a ground potential. The source of the transistor P11 is coupled to the high voltage source VDD, and its gate and drain are coupled to the drain of the transistor N12 and the gate of the transistor P12. The source of the transistor P12 is coupled to the high voltage source VDD, and the drain thereof is coupled to the drain of the transistor N13. The gate of the transistor N13 is coupled to the gate of the transistor N12. The memory unit 12 is coupled to the source of the transistor N12 and the ground potential. The reference memory unit 13 is coupled to the source of the transistor N13 and the ground potential. The memory cell 12 has an equivalent resistance R _cell and the current flowing through the equivalent resistance R _cell is I _cell . The reference storage unit 13 has two resistors R _max and R _min connected in parallel, and the currents flowing through the resistors are I _H and _IL respectively. The control current source 11 is used to generate a control current I _bias , and utilizes the difference between the channel aspect ratios of the transistors P11 and P12 (1 in FIG. 1 : the current of the transistor P12 is I _ref , and the current flowing through the transistor P11 is 1 /2I _ref . Resistors R _max and R _min respectively represent the resistance values of the storage unit 12 when storing logic 1 and logic 0, and currents I _H and _IL can be obtained respectively after applying a fixed bias voltage. And this technology is By using the resistance value of the memory cell 12 when storing logic 1 or logic 0, the fixed bias voltage is applied so that the memory cell current I _cell is I _H or I _L , and a voltage difference is generated between the terminals 14 and 15, The data stored in the memory cell 12 is judged by a comparator. However, in the present technology, the reference current I _ref is the sum of I _H and _IL , so the sense amplifier must have the ability to divide the current I _H and _IL by two. function, and this will increase the area of the sense amplifier, and because the current gap flowing through the memory unit 12 and the reference memory unit 13 is not large, the speed and accuracy of judgment will be affected. And the current of the sense amplifier of Fig. 1 With a read range of 1/2(I _L -I _H ) or 1/2(I _H -I _L ), if the difference between the currents I _H and I _L is not large enough, the sense amplifier of Figure 1 may not be sensitive enough and easily disturbed by noise.

FIG. 2 is a schematic circuit diagram of another conventional sense amplifier. The circuit diagram shown in FIG. 2 is the circuit diagram mentioned in US Patent No. 6,762,953. The sense amplifier in Fig. 2 also utilizes the current mirror to process Iref and Icell, so that the currents read by the two input terminals 22 and 23 of the comparator 21 are respectively Iref-Icell and Icell-Iref. In this way, a larger current range can be obtained than in the sense amplifier of FIG. 1 (the sense amplifier of FIG. 1 only has a current range of Iref-Icell). But in Figure 2, the value of Iref is still 1/2 (IH+IL), the sense amplifier must use an external circuit to divide the current Iref by two, or set the ratio of the current mirror in the sense amplifier to 1 : 2, to make the readout magnifier work normally. In the sense amplifier in Figure 2, the current readout range is (I _L -I _H ) or (I _H -I _L ), which is obviously increased compared with the readout range of the sense amplifier in Figure 1, but requires more transistors with more circuit area to complete.

In the prior art, the current sensing range of the sense amplifier is either too small (as shown in FIG. 1 ), or requires more transistors and circuit area (as shown in FIG. 2 ) to obtain a larger current sensing range. Therefore, there is a need for a sense amplifier that can obtain a larger current sense range with fewer transistors and a simpler circuit design.

Contents of the invention

The invention provides a sense amplifier coupled to a storage unit, including a first current mirror unit, a second current mirror unit, a first impedance component, a second impedance component and a third current mirror unit. The first current mirror unit has a first output terminal and a second output terminal, is coupled to a high voltage source, outputs the first current at the first output terminal according to a first current, and outputs the first current at the second output terminal Outputting a second current, wherein the second current is twice the first current. The second current mirror unit has a third output terminal coupled to a high voltage source, and outputs a reference current at the third output terminal according to a reference current. The first impedance component has a first impedance value and is coupled to the second output end and a low voltage source. The second impedance component, having the first impedance value, is coupled to the third output terminal and the low voltage source. The third current mirror unit is coupled to the first output terminal, the second output terminal and the third output terminal, and uses the first current as the reference current of the third current mirror unit, so that the current flowing through the first The current of the impedance component is the first current, and the current flowing through the second impedance component is a fourth current.

The present invention also provides a sense amplifier, which includes a first impedance component, a second impedance component, a storage unit current source, a reference storage unit current source, and first to eighth transistors. The first impedance component and the second impedance component are coupled to a low voltage source. The memory cell current source is coupled to a low voltage source for providing a first current. The reference memory cell current source is coupled to the low voltage source for providing a reference current. The first transistor has a first source, a first drain and a first gate, wherein the first source is coupled to a high voltage source, the first drain and the first gate are coupled to the memory cell current source. A second transistor has a second source, a second drain and a second gate, wherein the second source is coupled to the high voltage source, the second gate is coupled to the first gate, The second drain is coupled to the first impedance component. The third transistor has a third source, a third drain and a third gate, wherein the third source is coupled to the high voltage source, and the third gate is coupled to the first gate. A fourth transistor has a fourth source, a fourth drain and a fourth gate, wherein the fourth source is coupled to the high voltage source, and the fourth drain is coupled to the second impedance element. The fifth transistor has a fifth source, a fifth drain and a fifth gate, wherein the fifth source is coupled to the high voltage source, and the fifth gate is coupled to the fourth gate and the The fifth drain is coupled to the reference memory cell current source. The sixth transistor has a sixth source, a sixth drain and a sixth gate, wherein the sixth drain is coupled to the first impedance element and the second drain, and the sixth source is coupled to the low voltage source. The seventh transistor has a seventh source, a seventh drain and a seventh gate, wherein the seventh drain is coupled to the third drain, the sixth gate and the seventh gate, the The seventh source is coupled to the low voltage source. The eighth transistor has an eighth source, an eighth drain, and an eighth gate, wherein the eighth drain is coupled to the second impedance element and the fourth drain, and the eighth gate is coupled to The seventh gate and the eighth source are coupled to the low voltage source.

Description of drawings

FIG. 1 is a schematic circuit diagram of a conventional sense amplifier.

FIG. 2 is a schematic circuit diagram of another conventional sense amplifier.

FIG. 3 is a schematic diagram according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of an embodiment of the first current mirror unit 31 in FIG. 3 .

FIG. 5 is a circuit diagram of an embodiment of the second current mirror unit 32 in FIG. 3 .

FIG. 6 is a circuit diagram of an embodiment of the third current mirror unit 33 in FIG. 3 .

FIG. 7 is a schematic circuit diagram according to another embodiment of the present invention.

FIG. 8 is a schematic circuit diagram according to another embodiment of the present invention.

FIG. 9 is a schematic circuit diagram according to another embodiment of the present invention.

Description of reference symbols

11～control current source

12～storage unit

13 ~ reference storage unit

14, 15, 22, 23, 31a, 31b, 32a to endpoint

16, 21, 36, 75, 85～comparator

P11, P12, N11, N12, N13, T1, T2, T3, T4, T5, T6, T7, T8, T71, T72, T73, T74, T75, T76, T77, T78, T81, T82, T83, T84, T85, T86, T87, T88～Transistor

31 ~ the first current mirror unit

32～Second current mirror unit

33 ~ the third current mirror unit

34, 72, 82～the first impedance component

35, 73, 83 ~ the second impedance component

41, 71, 81 ~ memory cell current source

51, 74, 84～reference current source

Detailed ways

FIG. 3 is a schematic diagram according to an embodiment of the present invention. The first current mirror unit 31 is coupled to a high voltage source VDD, has a first output terminal 31a and a second output terminal 31b, and outputs a current through the second output terminal 31b according to a current source (not shown in the figure). I ₁ and a current I ₂ are output through the first output terminal 31a, where I ₂ =2I ₁ . The second current mirror unit 32 is coupled to the high voltage source VDD, has an output terminal 32 a, and outputs a current I _ref through the output terminal 32 a according to a reference current source (not shown in the figure). The third current mirror unit 33 is coupled to the first output terminal 31a, the second output terminal 31b, the output terminal 32a and a ground terminal, and uses the current _I1 output by the second output terminal 31b as the reference of the third current mirror unit 33 current. The first impedance component 34 is coupled to the first output terminal 31a and a ground terminal, and has an impedance value Z ₁ . The second impedance component 35 is coupled to the output terminal 32a and a ground terminal, and has an impedance value Z ₂ . Because the first output terminal 31a is coupled to the third current mirror 33 and the first impedance component 34, and the third current mirror unit 33 uses the current _I1 output by the second output terminal 31b as the reference current, so the first output terminal 31a The current flowing into the third current mirror unit is I ₁ . The current flowing out of the first output terminal 31a is I ₂ (2I ₁ ), so the magnitude of the current flowing through the first impedance component 34 is I ₁ . Similarly, the magnitude of the current I ₄ flowing through the second set of resistive components 35 is (I _ref −I ₁ ).

In this embodiment, the current _I1 is the current obtained by reading a memory cell with a fixed bias voltage, and when the data stored in the memory cell is logic high level, the current obtained by reading the memory cell with a fixed bias voltage The current is I _H , and when the data stored in the memory cell is at a logic low level, the current obtained by reading the memory cell with a fixed bias voltage is I _L . In this embodiment, the magnitude of the reference current I _ref is (I _H +I _L ). When the data stored in the memory cell is logic high level, the current I ₁ at this time is I _H , so a voltage (I _H ×Z1 ) can be obtained at the terminal 37 . The magnitude of the current I ₄ flowing through the second impedance component 35 is I _L , so a voltage (I _L ×Z2 ) can be obtained at the terminal 38 . The comparator 36 can output a voltage difference (I _H ×Z1−I _L ×Z2). If the impedance Z1 of the first impedance component 34 is equal to the impedance Z2 of the second impedance component 35, the voltage difference is (I _{H −IL} )×Z1.

FIG. 4 is a circuit diagram of an embodiment of the first current mirror unit 31 in FIG. 3 . The PMOS transistor T1 has a first source, a first drain and a first gate, wherein the first source is coupled to the high voltage source VDD, and the first gate and the first drain are coupled to a memory cell current source 41 , the memory cell current source is used to generate the induction current I ₁ of the memory cell. The PMOS transistor T2 has a second source, a second drain and a second gate, wherein the second source is coupled to the high voltage source VDD, the second gate is coupled to the first gate, and the second drain is coupled to Connect to the first output terminal 31a. The PMOS transistor T3 has a third source, a third drain and a third gate, wherein the third source is coupled to the high voltage source VDD, the third gate is coupled to the first gate, and the third drain is coupled to Connect to the second output terminal 31b. In this embodiment, in order to make the current output by the first output terminal 31a twice the current output by the second output terminal 31b, the channel aspect ratio (W/L) of the PMOS transistor T2 is designed to be that of the PMOS transistor T3 Twice the aspect ratio of the channel.

FIG. 5 is a circuit diagram of an embodiment of the second current mirror unit 32 in FIG. 3 . The PMOS transistor T4 has a fourth source, a fourth drain and a fourth gate, wherein the fourth source is coupled to the high voltage source VDD, and the fourth drain is coupled to the output terminal 32a. The PMOS transistor T5 has a fifth source, a fifth drain and a fifth gate, wherein the fifth source is coupled to the high voltage source VDD, the fifth gate and the fifth drain are coupled to the fourth gate, and the fifth gate is coupled to the fifth gate. The fifth drain is also coupled to a reference current source 51 for generating a reference current I _ref . The current mirror circuit formed by the PMOS transistors T4 and T5 enables the output terminal 32 a to output the reference current I _ref .

FIG. 6 is a circuit diagram of an embodiment of the third current mirror unit 33 in FIG. 3 . The NMOS transistor T7 has a seventh source, a seventh gate and a seventh drain, wherein the seventh source and the seventh gate are coupled to the second output terminal 31b for receiving the output from the second output terminal 31b For the current I ₁ , the seventh drain is coupled to a ground potential. In the third current mirror unit 33 , the NMOS transistor T7 is the reference current source of the third current mirror unit 33 according to the current I ₁ output by the second output terminal 31 b. The sixth transistor T6 has a sixth source, a sixth gate and a sixth drain, wherein the sixth drain is coupled to the first output terminal 31a, the sixth gate is coupled to the seventh gate, and the sixth source pole is coupled to ground potential. The eighth transistor T6 has an eighth source, an eighth gate and an eighth drain, wherein the eighth drain is coupled to the output terminal 32a, the eighth gate is coupled to the seventh gate, and the eighth source is coupled to connected to ground potential. Using the current mirror circuit formed by NMOS transistors T6, T7 and T8, the current flowing through the NMOS transistors T6, T7 and T8 is all _I1 , so the current flowing through the first impedance component 34 is _I1 , and the current flowing through the second impedance The current I ₄ of the component 35 is (I _ref −I ₁ ).

FIG. 7 is a schematic circuit diagram according to another embodiment of the present invention. The first sources/drains of the transistors T71, T72, T73, T74 and T75 are coupled to the high voltage source VDD. The gates of the transistors T71 and T72 are coupled to the gate of the transistor T73. The gate and the second source/drain of the transistor T71 are coupled to a memory cell current source 71. The memory cell current source 71 uses a fixed bias voltage to read a current I _cell obtained from a memory cell. When the data stored in the memory cell is logic high level, the current obtained by reading the memory cell with the fixed bias voltage is I _H . When the data stored in the memory cell is logic low level, the current obtained by reading the memory cell with the fixed bias voltage is I _L . The second source/drain of the transistor T72 is coupled to the first source/drain of the transistor T76 and an end of the first impedance element 72 , wherein the first impedance element 72 has an impedance value Z _load . In this embodiment, the current flowing through the transistor T72 is twice the current flowing through the transistor T73, and one way to achieve this is to design the channel aspect ratio (W/L) of the transistor T72 to be twice that of the transistor T73. times. The second source/drain of the transistor T73 is coupled to the first source/drain and the gate of the transistor T77. The gate of the transistor T74 is coupled to the gate of the transistor T75 and the second source/drain, and the second source/drain of the transistor T74 is coupled to the first source/drain of the transistor T78 and one terminal of the second impedance component 73, Wherein the second impedance component 73 has an impedance value Z _load . The second source/drain of the transistor T75 is coupled to a reference current source 74. The reference current source 74 uses the fixed bias to read a reference current I _ref obtained by a reference memory cell. In the present invention, the reference current I ref _ref is (I _H +I _L ). The second sources/drains of the transistors T76, T77 and T78 are coupled to a ground potential.

When the data stored in the memory cell is logic high level, the current obtained by reading the memory cell with the fixed bias voltage is I _H (ie, I _cell =I _H ). The transistors T76 , T77 and T78 form a current mirror structure, and the current I _H flowing into the transistor T77 is used as a reference current, so the current flowing through the transistor T76 is I _H , and the current flowing through the first impedance element 72 is I _H . The transistors T74 and T75 form a current mirror structure, so the current flowing out of the transistor T74 is I _ref , but the current flowing through the transistor T78 is I _H , so the current flowing through the second impedance element 73 is _IL (because I _ref = I _H + I _L ). The comparator 75 is coupled to the first impedance component 72 and the second impedance component 73 , and outputs a voltage V _out according to the voltages V _o and V _ob , and the voltage V _out is the sense range of the sense amplifier. In this embodiment, the voltage V _o is (I _H ×Z _load ), the voltage V _ob is (I _L ×Z _load ), so the voltage V _out is (I _H −I _L )×Z _load .

When the data stored in the memory cell is logic low level, the current obtained by reading the memory cell with the fixed bias voltage is I _L (that is, I _cell = _IL ). The transistors T76, T77 and T78 form a current mirror structure, and the current _IL flowing into the transistor T77 is used as a reference current, so the current flowing through the transistor T76 is _IL , and the current flowing through the first impedance element 72 is also _IL . The transistors T74 and T75 form a current mirror structure, so the current flowing out of the transistor T74 is I _ref , but the current flowing through the transistor T78 is I _L , so the current flowing through the second impedance element 73 is I _H (because I _ref = I _H + I _L ). The comparator 75 is coupled to the first impedance component 72 and the second impedance component 73 , and outputs a voltage V _out according to the voltages V _o and V _ob , and the voltage V _out is the sense range of the sense amplifier. In this embodiment, the voltage Vo is (I _L ×Z _load ), the voltage V _ob is (I _H ×Z _load ), so the voltage V _out is (I _L −I _H )×Z _load . Compared with the existing sense amplifier shown in Figure 1, the sense amplifier of the present invention has a higher voltage range than that shown in Figure 1 regardless of whether the data stored in the memory cell is a logic high level or a logic low level. The sense amplifier is doubled, and compared with the sense amplifier shown in FIG. 2 , it has the advantages of simple circuit and saving circuit area.

FIG. 8 is a schematic circuit diagram according to another embodiment of the present invention. The first sources/drains of the transistors T86, T87 and T88 are coupled to the high voltage source VDD, and the gates of the transistors T87 and T88 are coupled to the gate of the transistor T86. The second source/drain of the transistor T86 is coupled to the first source/drain of the transistor T82 and the first impedance component 82 . The second source/drain of the transistor T87 is coupled to the gate of the transistor T87 and the first source/drain of the transistor T83. The second source/drain of the transistor T88 is coupled to the first source/drain of the transistor T84 and the second impedance component 83 . The memory cell current source 81 is coupled to the high voltage source VDD and the first source/drain and gate of the transistor T81. The memory cell current source 81 uses a fixed bias voltage to read a current I _cell obtained from a memory cell. When the data stored in the memory cell is logic high level, the current obtained by reading the memory cell with the fixed bias voltage is I _H . When the data stored in the memory cell is logic low level, the current obtained by reading the memory cell with the fixed bias voltage is I _L . The reference current source 84 is coupled to the high voltage source VDD and the first source/drain and gate of the transistor T85. The reference current source 84 uses the fixed bias voltage to read a reference current I _ref obtained from a reference memory cell. In the present invention, the reference current I _ref is (I _H +I _L ). Second sources/drains of the transistors T81, T82, T83, T84 and T85 are coupled to a ground potential. The gates of the transistors T82 and T83 are coupled to the gate of the transistor T81. The gate of the transistor T84 is coupled to the gate of the transistor T85. In this embodiment, the current flowing through the transistor T82 is twice the current flowing through the transistor T81, and one way to achieve this is to design the channel aspect ratio (W/L) of the transistor T82 to be twice that of the transistor T81. times. In addition, in this embodiment, the first impedance component 82 and the second impedance component 83 have an impedance value Z _load .

When the data stored in the memory cell is logic high level, the current obtained by reading the memory cell with the fixed bias voltage is I _H (ie, I _cell =I _H ). The transistors T86 , T87 and T88 form a current mirror structure, and the current I _H flowing into the transistor T87 is used as a reference current, so the current flowing through the transistor T86 is I _H , and the current flowing through the first impedance element 82 is I _H . The transistors T84 and T85 form a current mirror structure, the current flowing out of the transistor T84 is I _ref , but the current flowing through the transistor T88 is I _H , so the current flowing through the second impedance component 83 is _IL (because I _ref =I _H + _IL ). The comparator 85 is coupled to the first impedance component 82 and the second impedance component 83 , and outputs a voltage V _out according to the voltages V _o and V _ob , and the voltage V _out is the sense range of the sense amplifier. In this embodiment, the voltage V _o is (VDD-I _H ×Z _load ), the voltage V _ob is (VDD-I _L ×Z _load ), so the voltage V _out is (I _H -I _L )×Z _load .

When the data stored in the memory cell is logic low level, the current obtained by reading the memory cell with the fixed bias voltage is I _L (that is, I _cell = _IL ). The transistors T86, T87 and T88 form a current mirror structure, and the current _IL flowing into the transistor T87 is used as a reference current, so the current flowing through the transistor T86 is _IL , and the current flowing through the first impedance element 72 is also _IL . The transistors T84 and T85 form a current mirror structure, so the current flowing out of the transistor T84 is I _ref , but the current flowing through the transistor T88 is I _L , so the current flowing through the second impedance component 83 is I _H (because I _ref = I _H + I _L ). The comparator 85 is coupled to the first impedance component 82 and the second impedance component 83 , and outputs a voltage V _out according to the voltages Vo and V _ob , and the voltage V _out is the sense range of the sense amplifier. In this embodiment, the voltage Vo is (VDD-I _L ×Z _load ), the voltage V _ob is (VDD-I _H ×Z _load ), so the voltage V _out is (I _L -I _H )×Zload. Compared with the existing sense amplifier shown in Figure 1, the sense amplifier of the present invention has a higher voltage range than that shown in Figure 1 regardless of whether the data stored in the memory cell is a logic high level or a logic low level. The sense amplifier is doubled, and compared with the sense amplifier shown in FIG. 2 , it has the advantages of simple circuit and saving circuit area.

FIG. 9 is a schematic circuit diagram according to another embodiment of the present invention. The first source/drain of the transistors T91, T92, T93, T94 and T95 are coupled to the high voltage source VDD, the gate of the transistor T91 is coupled to the gates of the transistors T92 and T93, and the gate of the transistor T94 is coupled to the gate of T95 . The memory cell current source 91 is coupled to the second source/drain and the gate of the transistor T91. The memory cell current source 91 uses a fixed bias voltage to read the current I _cell obtained from a memory cell. When the data stored in the memory cell is logic high level, the current obtained by reading the memory cell with the fixed bias voltage is I _H . When the data stored in the memory cell is logic low level, the current obtained by reading the memory cell with the fixed bias voltage is I _L . The second source/drain of the transistor T92 is coupled to the first impedance element 92 and the comparator 95 . The second source/drain of the transistor T93 is coupled to the first source/drain of the transistor T96 and the gates of the transistors T96 and T98. The reference current source 94 is coupled to the second source/drain of the transistor T95 and the gate of the transistor T95. The second source/drain of the transistor T94 is coupled to the first source/drain of the transistor T98 , the second impedance component 93 and the comparator 95 .

When the data stored in the memory cell is logic high level, the current obtained by reading the memory cell with the fixed bias voltage is I _H (ie, I _cell =I _H ). The transistors T91 , T92 and T93 form a current mirror structure, so that the current flowing through the current mirror formed by the first impedance element 92 and the transistors T96 and T98 is I _H . The transistors T94 and T95 form a current mirror structure, the current flowing out of the transistor T94 is I _ref , but the current flowing through the transistor T98 is I _H , so the current flowing through the second impedance component 93 is _IL (because I _ref =I _H + _IL ). The comparator 95 is coupled to the first impedance component 92 and the second impedance component 93 , and outputs a voltage V _out according to the voltages Vo and V _ob , and the voltage V _out is the sense range of the sense amplifier. In this embodiment, the voltage Vo is (I _L ×Z _load ), the voltage V _ob is (I _H ×Z _load ), so the voltage V _out is (I _H −I _L )×Z load. Compared with the existing sense amplifier shown in Figure 1, the sense amplifier of the present invention has a higher voltage range than that shown in Figure 1 regardless of whether the data stored in the memory cell is a logic high level or a logic low level. The sense amplifier is doubled, and compared with the sense amplifier shown in FIG. 2 , it has the advantages of simple circuit and saving circuit area.

When the data stored in the memory cell is at logic low level, the current obtained by reading the memory cell with the fixed bias voltage is I _L (that is, I _cell =I _H ). The transistors T91 , T92 and T93 form a current mirror structure, so that the current flowing through the current mirror formed by the first impedance element 92 and the transistors T96 and T98 is I _L . The transistors T94 and T95 form a current mirror structure, the current flowing out of the transistor T94 is I _ref , but the current flowing through the transistor T98 is I _L , so the current flowing through the second impedance component 93 is I _H (because I _ref =I _H + _IL ). The comparator 95 is coupled to the first impedance component 92 and the second impedance component 93 , and outputs a voltage V _out according to the voltages Vo and V _ob , and the voltage V _out is the sense range of the sense amplifier. In this embodiment, the voltage Vo is (I _H ×Z _load ), the voltage V _ob is (I _L ×Z _load ), so the voltage V _out is (I _L −I _H )×Zload. Compared with the existing sense amplifier shown in Figure 1, the sense amplifier of the present invention has a higher voltage range than that shown in Figure 1 regardless of whether the data stored in the memory cell is a logic high level or a logic low level. The sense amplifier is doubled, and compared with the sense amplifier shown in FIG. 2 , it has the advantages of simple circuit and saving circuit area.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is based on the claims of the present invention.

Claims (24)

1. A sense amplifier coupled to a memory cell, comprising: A first current mirror unit, having a first output terminal and a second output terminal, coupled to a high voltage source, outputting the first current at the first output terminal and outputting the first current at the second output terminal according to a first current outputting a second current, wherein the second current is twice the first current; a second current mirror unit, having a third output terminal, coupled to a high voltage source, outputting the reference current at the third output terminal according to a reference current; a first impedance component, having a first impedance value, coupled to the second output terminal and a low voltage source; a second impedance component, having the first impedance value, coupled to the third output terminal and the low voltage source; and A third current mirror unit, coupled to the first output terminal, the second output terminal and the third output terminal, and uses the first current as the reference current of the third current mirror unit, so that the first current mirror unit flows through the first The current of the impedance component is the first current, and the current flowing through the second impedance component is a fourth current. 2. The sense amplifier as claimed in claim 1, further comprising a comparator having two input terminals and one output terminal, wherein one input terminal is coupled to the second output terminal, and the other input terminal is coupled to the first output terminal. Three output terminals, the output terminals are used to output a voltage difference. 3. The sense amplifier as claimed in claim 2, wherein the voltage difference is a difference between the first current and the reference current multiplied by the first impedance value. 4. The sense amplifier as claimed in claim 1 , wherein the memory cell receives the fixed bias voltage to generate a logic high current when storing a logic level 1 data, and the memory cell stores a logic level 0 When the data is received, a logic low current is generated by receiving the fixed bias voltage. 5. The sense amplifier as claimed in claim 4, wherein the reference current is the sum of the logic high current and the logic low current. 6. The sense amplifier as claimed in claim 1, wherein the first current mirror unit further comprises: a memory cell current source, coupled to the low voltage source, for providing the first current; A first transistor has a first source, a first drain and a first gate, wherein the first source is coupled to the high voltage source, the first drain and the first gate are coupled to the memory cell current source; A second transistor has a second source, a second drain and a second gate, wherein the second source is coupled to the high voltage source, the second gate is coupled to the first gate, the second drain is coupled to the first impedance element and the third current mirror unit; and a third transistor having a third source, a third drain and a third gate, wherein the third source is coupled to the high voltage source, the third gate is coupled to the first gate, The third drain is coupled to the third current mirror unit. 7. The sense amplifier of claim 6, wherein an aspect ratio of the second transistor is twice that of the first transistor. 8. The sense amplifier as claimed in claim 1, wherein the second current mirror unit further comprises: a reference memory cell current source coupled to the low voltage source for providing the reference current; A fourth transistor has a fourth source, a fourth drain and a fourth gate, wherein the fourth source is coupled to the high voltage source, and the fourth drain is coupled to the third current mirror unit with the second impedance component; and A fifth transistor has a fifth source, a fifth drain and a fifth gate, wherein the fifth source is coupled to the high voltage source, and the fifth gate is coupled to the fourth gate and the fifth gate The fifth drain is coupled to the reference memory cell current source. 9. The sense amplifier as claimed in claim 1, wherein the third current mirror unit further comprises: A sixth transistor has a sixth source, a sixth drain, and a sixth gate, wherein the sixth drain is coupled to the first impedance component and the first current mirror unit, and the sixth source coupled to the low voltage source; A seventh transistor having a seventh source, a seventh drain and a seventh gate, wherein the seventh drain is coupled to the first current mirror unit, the sixth gate and the seventh gate , the seventh source is coupled to the low voltage source; and An eighth transistor has an eighth source, an eighth drain, and an eighth gate, wherein the eighth drain is coupled to the second impedance component and the second current mirror unit, and the eighth gate coupled to the seventh gate, and the eighth source is coupled to the low voltage source. 10. The sense amplifier as claimed in claim 1, wherein the first impedance component is a resistor, a capacitor, an inductor or a combination of the above components. 11. The sense amplifier as claimed in claim 1, wherein the first impedance element is an active resistor. 12. The sense amplifier as claimed in claim 1, wherein the second impedance component is a resistor, a capacitor, an inductor or a combination of the above components. 13. The sense amplifier as claimed in claim 1, wherein the second impedance element is an active resistor. 14. The sense amplifier as claimed in claim 1, wherein the third current is the sum of the first current and the fourth current. 15. A sense amplifier coupled to a memory cell, comprising: a first impedance component, coupled to a low voltage source; a second impedance component coupled to the low voltage source; a memory cell current source coupled to a low voltage source for providing a first current; a reference memory cell current source coupled to the low voltage source for providing a reference current; A first transistor has a first source, a first drain and a first gate, wherein the first source is coupled to a high voltage source, the first drain and the first gate are coupled to the memory cell current source; A second transistor has a second source, a second drain and a second gate, wherein the second source is coupled to the high voltage source, the second gate is coupled to the first gate, the second drain is coupled to the first impedance element; A third transistor having a third source, a third drain and a third gate, wherein the third source is coupled to the high voltage source, and the third gate is coupled to the first gate; A fourth transistor has a fourth source, a fourth drain and a fourth gate, wherein the fourth source is coupled to the high voltage source, and the fourth drain is coupled to the second impedance element; A fifth transistor has a fifth source, a fifth drain and a fifth gate, wherein the fifth source is coupled to the high voltage source, and the fifth gate is coupled to the fourth gate and the fifth gate the fifth drain, the fifth drain is coupled to the reference memory cell current source; A sixth transistor has a sixth source, a sixth drain, and a sixth gate, wherein the sixth drain is coupled to the first impedance element and the second drain, and the sixth source is coupled to the second drain. connected to the low voltage source; A seventh transistor having a seventh source, a seventh drain and a seventh gate, wherein the seventh drain is coupled to the third drain, the sixth gate and the seventh gate, the seventh source is coupled to the low voltage source; and An eighth transistor has an eighth source, an eighth drain, and an eighth gate, wherein the eighth drain is coupled to the second impedance element and the fourth drain, and the eighth gate is coupled to connected to the seventh gate, and the eighth source is coupled to the low voltage source. 16. The sense amplifier as claimed in claim 15, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are PMOS transistors. 17. The sense amplifier as claimed in claim 15, wherein the sixth transistor, the seventh transistor and the eighth transistor are NMOS transistors. 18. The sense amplifier as claimed in claim 15, further comprising a comparator having two input terminals and an output terminal, wherein one input terminal is coupled to the first impedance component and the second drain, and the other The input terminal is coupled to the second impedance component and the fourth drain, and the output terminal is used for outputting a voltage drop difference between the first impedance and the second impedance. 19. The sense amplifier as claimed in claim 15, wherein the first impedance element and the second impedance element have a first impedance value, and the voltage drop difference is a difference between the first current and the reference current multiplied by on the first impedance value. 20. The sense amplifier of claim 15, wherein an aspect ratio of the second transistor is twice that of the first transistor. 21. The sense amplifier as claimed in claim 15, wherein the first impedance component is a resistor, a capacitor, an inductor or a combination of the above components. 22. The sense amplifier as claimed in claim 15, wherein the first impedance element is an active resistor. 23. The sense amplifier as claimed in claim 15, wherein the second impedance component is a resistor, a capacitor, an inductor or a combination of the above components. 24. The sense amplifier of claim 15, wherein the first impedance element is an active resistor.

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