CN101042923A - Read out amplifier - Google Patents
Read out amplifier Download PDFInfo
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- CN101042923A CN101042923A CN 200610071485 CN200610071485A CN101042923A CN 101042923 A CN101042923 A CN 101042923A CN 200610071485 CN200610071485 CN 200610071485 CN 200610071485 A CN200610071485 A CN 200610071485A CN 101042923 A CN101042923 A CN 101042923A
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- transistor
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- source
- drain electrode
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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Abstract
This invention relates to one read amplifier, which comprises the following parts: one first current lens unit welded to one high voltage source to output one first and second current according to one first reference current with the second volume two times as large as first one; one second current lens unit coupled to one high voltage source to output one third current according to one second reference current; one first resistance part coupled to the second current and one lower voltage source; one second resistance part coupled to the third current and the low voltage source; one third current lens unit welded to the first current, second and third ones and the first current is for reference current for third current lens unit.
Description
Technical field
The present invention relates to a kind of sensor amplifier (sense amplifier), particularly relate to a kind of sensor amplifier that can increase the read range of read-out voltage.
Background technology
Because nonvolatile memory has become the main flow of present storer there not being electric power that but following still long preservation data are provided.(Magnetoresistive RAM, MRAM) (Resistive RAM, RAM), the mode of its storage data is to utilize the resistance difference of store memory storage unit to distinguish 0 or 1 data with resistance-type memory with the reluctance type storer.And read data in reluctance type storer and the resistance-type memory be utilize with the current ratio of the reference memory unit of flowing through, and then learn the data of cell stores.In general, the mode that reads all is to utilize a sensor amplifier (SenseAmplifier SA) reads electric current in the storage unit, to learn the situation of storage unit.Because in the storage unit logic state 0 with had different resistance values at 1 o'clock, after storage unit is applied a bias voltage, just have different electric currents, learn logic state 0 or 1 in the storage unit by the size of judgement electric current.
In addition, the reading speed of storage unit also has suitable relation with sensor amplifier.Sensor amplifier judges that the required time of state of memory cells is short more good more, and the time of reading except depending on sensor amplifier itself, also relevant with the size of current of the storage unit of flowing through.
Fig. 1 is the circuit diagram of an existing sensor amplifier.Control current source 11 couples drain electrode and the grid of a high voltage source VDD and transistor N11.One resistor assembly R couples a source electrode and the earth potential of transistor N11.The source electrode of transistor P11 couples high voltage source VDD, and its grid couples the drain electrode of transistor N12 and the grid of transistor P12 with drain electrode.The source electrode of transistor P12 couples high voltage source VDD, and its drain electrode couples the drain electrode of transistor N13.The grid of transistor N13 couples the grid of transistor N12.Storage unit 12 couples source electrode and the earth potential of transistor N12.Reference memory unit 13 couples source electrode and the earth potential of transistor N13.Has an equivalent resistance R in the storage unit 12
CellAnd this equivalence resistance R of flowing through
CellElectric current be I
CellHave two resistance R in parallel in the reference memory unit 13
MaxWith R
Min, and the electric current of this resistance of flowing through is respectively I
HWith I
LControl current source 11 is in order to produce a Control current I
Bias, and (be 1 in Fig. 1: the electric current of transistor P12 is I to utilize passage length breadth ratio different of transistor P11 and P12
Ref, the electric current of the transistor P11 that flows through is 1/2I
RefResistance R
MaxWith R
MinRepresent the resistance value of storage unit 12 when stored logic 1 and logical zero respectively, and after applying a fixed-bias transistor circuit, just can obtain electric current I respectively
HWith I
LAnd present technique is to utilize the resistance value of storage unit 12 when stored logic 1 or logical zero, applies with this fixed-bias transistor circuit, makes memory cell current I
CellBe I
HOr I
L, and between end points 14 and 15, produce a voltage difference, judge the data of learning that storage unit 12 stores by a comparer.But in the present technique, reference current I
RefBe I
HWith I
LSum, so sensor amplifier must possess and has electric current I
HWith I
LFunction divided by two, and this can increase the area of sensor amplifier, and little because of the storage unit 12 of flowing through with the difference between current distance of reference memory unit 13, can be affected in speed and the accuracy rate judged.And its electric current read range of the sensor amplifier of Fig. 1 is 1/2 (I
L-I
H) or 1/2 (I
H-I
L), if electric current I
HWith I
LDifference big inadequately, the sensor amplifier of Fig. 1 is just may be inadequately sensitive and be subjected to interference of noise easily.
Fig. 2 is the circuit diagram of another existing sensor amplifier.Circuit diagram shown in Figure 2 is a U.S. Patent number 6,762, mentioned circuit diagram in 953.Sensor amplifier among Fig. 2 also is to utilize current mirror, Iref and Icell are dealt with, make two input ends 22 and 23 electric currents that read into of comparer 21 be respectively Iref-Icell and Icell-Iref, bigger range of current (sensor amplifier of Fig. 1 only has the range of current of Iref-Icell) in the sharp sensor amplifier that can obtain in such a way than Fig. 1.But in Fig. 2, the value of Iref still is 1/2 (IH+IL), and sensor amplifier must utilize an external circuit that electric current I ref is done to remove two processing, or the ratio of setting current mirror is 1: 2 in sensor amplifier, could make and read the magnifier normal operation.In the sensor amplifier of Fig. 2, its electric current read range is (I
L-I
H) or (I
H-I
L), obviously the read range than the sensor amplifier of Fig. 1 increases, but needs the more more circuit area of transistor AND gate to finish.
In the prior art, the electric current read range of sensor amplifier is not too little (as Fig. 1), needs more transistor AND gate circuit area (as Fig. 2) exactly, to obtain bigger electric current read range.Therefore, a sensor amplifier that obtains bigger electric current read range with still less transistor and simpler circuit design has its necessity.
Summary of the invention
The invention provides a kind of sensor amplifier, couple a storage unit, comprise one first current lens unit, one second current lens unit, one first impedance component, one second impedance component and one the 3rd current lens unit.This first current lens unit, have one first output terminal and one second output terminal, couple a high voltage source, export this first electric current and export one second electric current in this first output terminal, wherein this second electric current twice that is this first electric current in this second output terminal according to one first electric current.This second current lens unit has one the 3rd output terminal, couples a high voltage source, exports this reference current according to a reference current in the 3rd output terminal.This first impedance component has one first resistance value, couples this second output terminal and a low-voltage source.This second impedance component has this first resistance value, couples the 3rd output terminal and this low-voltage source.The 3rd current lens unit, couple this first output terminal, this second output terminal and the 3rd output terminal, and with this first electric current reference current that is the 3rd current lens unit, the electric current of feasible this first impedance component of flowing through is this first electric current, and the electric current of this second impedance component of flowing through is one the 4th electric current.
The present invention also provides a kind of sensor amplifier, comprises one first impedance component, one second impedance component, a memory cell current source, a reference memory unit current source, first to the 8th transistor.This first impedance component and this second impedance component couple a low-voltage source.This memory cell current source couples a low-voltage source, in order to one first electric current to be provided.This reference memory unit current source couples this low-voltage source, in order to a reference current to be provided.The first transistor has one first source electrode, one first drain electrode and a first grid, and wherein this first source electrode couples a high voltage source, this first drain electrode and this first grid and couples this memory cell current source.One transistor seconds has one second source electrode, one second drain electrode and a second grid, and wherein this second source electrode couples this high voltage source, and this second grid couples this first grid, and this second drain electrode couples this first impedance component.The 3rd transistor has one the 3rd source electrode, one the 3rd drain electrode and one the 3rd grid, and wherein the 3rd source electrode couples this high voltage source, and the 3rd grid couples this first grid.One the 4th transistor has one the 4th source electrode, one the 4th drain electrode and one the 4th grid, and wherein the 4th source electrode couples this high voltage source, and the 4th drain electrode couples this second impedance component.The 5th transistor has one the 5th source electrode, one the 5th drain electrode and one the 5th grid, and wherein the 5th source electrode couples this high voltage source, and the 5th grid couples the 4th grid and the 5th drain electrode, and the 5th drain electrode couples this reference memory unit current source.The 6th transistor has one the 6th source electrode, one the 6th drain electrode and one the 6th grid, and wherein the 6th drain electrode couples this first impedance component and this second drain electrode, and the 6th source electrode couples this low-voltage source.The 7th transistor has one the 7th source electrode, one the 7th drain electrode and one the 7th grid, and wherein the 7th drain electrode couples the 3rd drain electrode, the 6th grid and the 7th grid, and the 7th source electrode couples this low-voltage source.The 8th transistor has one the 8th source electrode, one the 8th drain electrode and one the 8th grid, and wherein the 8th drain electrode couples this second impedance component and the 4th drain electrode, and the 8th grid couples the 7th grid, and the 8th source electrode couples this low-voltage source.
Description of drawings
Fig. 1 is the circuit diagram of an existing sensor amplifier.
Fig. 2 is the circuit diagram of another existing sensor amplifier.
Fig. 3 is the synoptic diagram according to one embodiment of the invention.
Fig. 4 is the circuit diagram of an embodiment of first current lens unit 31 among Fig. 3.
Fig. 5 is the circuit diagram of an embodiment of second current lens unit 32 among Fig. 3.
Fig. 6 is the circuit diagram of an embodiment of the 3rd current lens unit 33 among Fig. 3.
Fig. 7 is a circuit diagram according to another embodiment of the present invention.
Fig. 8 is a circuit diagram according to another embodiment of the present invention.
Fig. 9 is a circuit diagram according to another embodiment of the present invention.
The reference numeral explanation
11～Control current source
12～storage unit
13～reference memory unit
14,15,22,23,31a, 31b, 32a～end points
16,21,36,75,85～comparer
P11, P12, N11, N12, N13, T1, T2, T3, T4, T5, T6, T7, T8, T71, T72, T73, T74, T75, T76, T77, T78, T81, T82, T83, T84, T85, T86, T87, T88～transistor
31～the first current lens unit
32～the second current lens unit
33～the 3rd current lens unit
34,72,82～the first impedance components
35,73,83～the second impedance components
41,71,81～memory cell current source
51,74,84～reference current source
Embodiment
Fig. 3 is the synoptic diagram according to one embodiment of the invention.First current lens unit 31 couples a high voltage source VDD, has one first output terminal 31a and one second output terminal 31b, and exports an electric current I according to a current source (not drawing on the figure) by the second output terminal 31b
1With by the first output terminal 31a output current I
2, I wherein
2=2I
1Second current lens unit 32 couples this high voltage source VDD, has an output terminal 32a, and exports an electric current I according to a reference current source (not drawing on the figure) by output terminal 32a
RefThe 3rd current lens unit 33 couples the first output terminal 31a, the second output terminal 31b, output terminal 32a and an earth terminal, and with the electric current I by second output terminal 31b output
1It is the reference current of the 3rd current lens unit 33.First impedance component 34 couples the first output terminal 31a and an earth terminal, has a resistance value Z
1 Second impedance component 35 couples an output terminal 32a and an earth terminal, has a resistance value Z
2Because the first output terminal 31a couples the 3rd current mirror 33 and first impedance component 34, and the 3rd current lens unit 33 is with the electric current I by second output terminal 31b output
1Therefore be reference current, the electric current that flows into the 3rd current lens unit by the first output terminal 31a is I
1And the electric current that was originally flowed out by the first output terminal 31a is I
2(2I
1), the size of current of first impedance component 34 of therefore flowing through is I
1In like manner, the flow through electric current I of second group of anti-assembly 35
4Size is (I
Ref-I
1).
In the present embodiment, electric current I
1For reading the resulting electric current of a storage unit with a fixed-bias transistor circuit, and when the data of cell stores were logic high, reading the resulting electric current of this storage unit with fixed-bias transistor circuit was I
H, and when the data of cell stores were logic low, reading the resulting electric current of this storage unit with fixed-bias transistor circuit was I
LIn the present embodiment, reference current I
RefSize be (I
H+ I
L).When the data of cell stores are logic high, the electric current I of this moment
1Be I
H, therefore can obtain a voltage (I at end points 37
H* Z1).And the electric current I of second impedance component 35 of flowing through
4Size is I
L, therefore can obtain a voltage (I at end points 38
L* Z2).And the just exportable voltage difference (I of comparer 36
H* Z1-I
L* Z2).If the resistance value Z1 of first impedance component 34 equals the resistance value Z2 of second impedance component 35, then this voltage difference is (I
H-I
L) * Z1.
Fig. 4 is the circuit diagram of an embodiment of first current lens unit 31 among Fig. 3.PMOS transistor T 1 has one first source electrode, first drain electrode and the first grid, wherein first source electrode couples high voltage source VDD, the first grid and first drain electrode couple a memory cell current source 41, and this memory cell current source is in order to produce the induction current I of storage unit
1PMOS transistor T 2 has one second source electrode, second drain electrode and the second grid, and wherein second source electrode couples high voltage source VDD, and second grid couples first grid, and second drain electrode then couples the first output terminal 31a.PMOS transistor T 3 has one the 3rd source electrode, the 3rd drain electrode and one the 3rd grid, and wherein the 3rd source electrode couples high voltage source VDD, and the 3rd grid couples first grid, and the 3rd drain electrode then couples the second output terminal 31b.In the present embodiment, for the electric current that makes the output terminal 31a output of winning is the twice of the electric current of second output terminal 31b output, therefore be designed to the twice of the passage length breadth ratio of PMOS transistor T 3 in the passage length breadth ratio (W/L) of PMOS transistor T 2.
Fig. 5 is the circuit diagram of an embodiment of second current lens unit 32 among Fig. 3.PMOS transistor T 4 has one the 4th source electrode, the 4th drain electrode and one the 4th grid, and wherein the 4th source electrode couples high voltage source VDD, and the 4th drain electrode couples output terminal 32a.PMOS transistor T 5 has one the 5th source electrode, the 5th drain electrode and one the 5th grid, wherein the 5th source electrode couples high voltage source VDD, the 5th grid and the 5th drain electrode couple the 4th grid, and the 5th drain electrode also couples a reference current source 51, and this reference current source is in order to produce reference current I
RefUtilize PMOS transistor T 4 and the current mirroring circuit that T5 forms, make output terminal 32a can export reference current I
Ref
Fig. 6 is the circuit diagram of an embodiment of the 3rd current lens unit 33 among Fig. 3.Nmos pass transistor T7 has one the 7th source electrode, one the 7th grid and one the 7th drain electrode, and wherein the 7th source electrode and the 7th grid couple the second output terminal 31b, in order to receive the electric current I of second output terminal 31b output
1, the 7th drain electrode couples an earthing potential.In the 3rd current lens unit 33, nmos pass transistor T7 is according to the electric current I of second output terminal 31b output
1It is the reference current source of the 3rd current lens unit 33.The 6th transistor T 6 has one the 6th source electrode, one the 6th grid and one the 6th drain electrode, and wherein the 6th drain electrode couples the first output terminal 31a, and the 6th grid couples the 7th grid, and the 6th source electrode couples earthing potential.The 8th transistor T 6 has one the 8th source electrode, one the 8th grid and one the 8th drain electrode, and wherein the 8th drain electrode couples output terminal 32a, and the 8th grid couples the 7th grid, and the 8th source electrode couples earthing potential.The current mirroring circuit that utilizes nmos pass transistor T6, T7 and T8 to form, the electric current of feasible flow through nmos pass transistor T6, T7 and T8 is all I
1, the electric current of first impedance component 34 of therefore flowing through is I
1, the electric current I of second impedance component 35 of flowing through
4Be (I
Ref-I
1).
Fig. 7 is a circuit diagram according to another embodiment of the present invention.First source/drain electrode of transistor T 71, T72, T73, T74 and T75 couples high voltage source VDD.The grid of transistor T 71 and T72 couples the grid of transistor T 73.The grid of transistor T 71 and second source/drain electrode couple a memory cell current source 71, and memory cell current source 71 is the electric current I of removing to read a storage unit gained with a fixed-bias transistor circuit
CellWhen the data of cell stores were logic high, the electric current of reading this storage unit gained with this fixed-bias transistor circuit was I
HWhen the data of cell stores were logic low, the electric current of reading this storage unit gained with this fixed-bias transistor circuit was I
LSecond source/drain electrode of transistor T 72 couples first a source/drain electrode of transistor T 76 and an end points of first impedance component 72, and wherein first impedance component 72 has a resistance value Z
LoadIn the present embodiment, the electric current of the transistor T 72 of flowing through is the twice of electric current of transistor T 73 of flowing through, and method that one of them reaches this purpose is the twice of transistor T 73 for the passage length breadth ratio (W/L) of design transistor T 72.Second source/drain electrode of transistor T 73 couples first source/drain electrode and the grid of transistor T 77.The grid of transistor T 74 couples the grid and the second source/drain electrode of transistor T 75, and second source/drain electrode of transistor T 74 couples first a source/drain electrode of transistor T 78 and an end points of second impedance component 73, and wherein second impedance component 73 has a resistance value Z
LoadSecond source/drain electrode of transistor T 75 couples a reference current source 74, and reference current source 74 is reference current I that remove to read a reference memory unit gained with this fixed-bias transistor circuit
Ref, in the present invention, reference current I
RefBe (I
H+ I
L).Second source/drain electrode of transistor T 76, T77 and T78 couples an earthing potential.
When the data that store in the storage unit were logic high, read this storage unit resulting electric current with this fixed-bias transistor circuit this moment was I
H(that is I
Cell=I
H).Transistor T 76, T77 and T78 form a current mirror framework, and with the electric current I of inflow transistor T77
HBe reference current, the electric current of the transistor T 76 of therefore flowing through is I
H, the electric current of first impedance component 72 of flowing through is I
HTransistor T 74 forms a current mirror framework with T75, so the electric current that is flowed out by transistor T 74 is I
Ref, but the electric current of the transistor T 78 of flowing through is I
HSo the electric current of second impedance component 73 of flowing through is I
L(because I
Ref=I
H+ I
L).Comparer 75 couples first impedance component 72 and second impedance component 73, and according to voltage V
oWith V
ObExport a voltage V
Out, voltage V
OutThe i.e. read range of sensor amplifier for this reason.In the present embodiment, voltage V
oBe (I
H* Z
Load), voltage V
ObBe (I
L* Z
Load), so voltage V
OutBe (I
H-I
L) * Z
Load
When the data that store in the storage unit were logic low, read this storage unit resulting electric current with this fixed-bias transistor circuit this moment was I
L(that is I
Cell=I
L).Transistor T 76, T77 and T78 form a current mirror framework, and with the electric current I of inflow transistor T77
LBe reference current, the electric current of the transistor T 76 of therefore flowing through is I
L, the electric current of first impedance component 72 of flowing through also is I
LTransistor T 74 forms a current mirror framework with T75, so the electric current that is flowed out by transistor T 74 is I
Ref, but the electric current of the transistor T 78 of flowing through is I
LSo the electric current of second impedance component 73 of flowing through is I
H(because I
Ref=I
H+ I
L).Comparer 75 couples first impedance component 72 and second impedance component 73, and according to voltage V
oWith V
ObExport a voltage V
Out, voltage V
OutThe i.e. read range of sensor amplifier for this reason.In the present embodiment, voltage Vo is (I
L* Z
Load), voltage V
ObBe (I
H* Z
Load), so voltage V
OutBe (I
L-I
H) * Z
LoadCompare with existing sensor amplifier shown in Figure 1, the sensor amplifier of the present invention no matter data of cell stores is logic high or logic low, its voltage range of reading sensor amplifier all more shown in Figure 1 doubles, and compare with sensor amplifier shown in Figure 2, have the advantage that circuit is simple and save circuit area.
Fig. 8 is a circuit diagram according to another embodiment of the present invention.First source/drain electrode of transistor T 86, T87 and T88 couples high voltage source VDD, and the grid of transistor T 87 and T88 couples the grid of transistor T 86.Second source/drain electrode of transistor T 86 couples the first source/drain electrode and first impedance component 82 of transistor T 82.Second source/drain electrode of transistor T 87 couples first source/drain electrode of the grid and the transistor T 83 of transistor T 87.Second source/drain electrode of transistor T 88 couples the first source/drain electrode and second impedance component 83 of transistor T 84.Memory cell current source 81 couples first source/drain electrode and the grid of high voltage source VDD and transistor T 81, and memory cell current source 81 is the electric current I of removing to read a storage unit gained with a fixed-bias transistor circuit
CellWhen the data of cell stores were logic high, the electric current of reading this storage unit gained with this fixed-bias transistor circuit was I
HWhen the data of cell stores were logic low, the electric current of reading this storage unit gained with this fixed-bias transistor circuit was I
LReference current source 84 couples first source/drain electrode and the grid of high voltage source VDD and transistor T 85, and reference current source 84 is reference current I that remove to read a reference memory unit gained with this fixed-bias transistor circuit
Ref, in the present invention, reference current I
RefBe (I
H+ I
L).Second source/drain electrode of transistor T 81, T82, T83, T84 and T85 couples an earthing potential.The grid of transistor T 82 and T83 couples the grid of transistor T 81.The grid of transistor T 84 couples the grid of transistor T 85.In the present embodiment, the electric current of the transistor T 82 of flowing through is the twice of electric current of transistor T 81 of flowing through, and method that one of them reaches this purpose is the twice of transistor T 81 for the passage length breadth ratio (W/L) of design transistor T 82.In addition, in the present embodiment, first impedance component 82 and second impedance component 83 have a resistance value Z
Load
When the data that store in the storage unit were logic high, read this storage unit resulting electric current with this fixed-bias transistor circuit this moment was I
H(that is I
Cell=I
H).Transistor T 86, T87 and T88 form a current mirror framework, and with the electric current I of inflow transistor T87
HBe reference current, the electric current of the transistor T 86 of therefore flowing through is I
H, the electric current of first impedance component 82 of flowing through is I
HTransistor T 84 forms a current mirror framework with T85, and the electric current that is flowed out by transistor T 84 is I
Ref, but the electric current of the transistor T 88 of flowing through is I
HSo the electric current of second impedance component 83 of flowing through is I
L(because I
Ref=I
H+ I
L).Comparer 85 couples first impedance component 82 and second impedance component 83, and according to voltage V
oWith V
ObExport a voltage V
Out, voltage V
OutThe i.e. read range of sensor amplifier for this reason.In the present embodiment, voltage V
oBe (VDD-I
H* Z
Load), voltage V
ObBe (VDD-I
L* Z
Load), so voltage V
OutBe (I
H-I
L) * Z
Load
When the data that store in the storage unit were logic low, read this storage unit resulting electric current with this fixed-bias transistor circuit this moment was I
L(that is I
Cell=I
L).Transistor T 86, T87 and T88 form a current mirror framework, and with the electric current I of inflow transistor T87
LBe reference current, the electric current of the transistor T 86 of therefore flowing through is I
L, the electric current of first impedance component 72 of flowing through also is I
LTransistor T 84 forms a current mirror framework with T85, so the electric current that is flowed out by transistor T 84 is I
Ref, but the electric current of the transistor T 88 of flowing through is I
LSo the electric current of second impedance component 83 of flowing through is I
H(because I
Ref=I
H+ I
L).Comparer 85 couples first impedance component 82 and second impedance component 83, and according to voltage Vo and V
ObExport a voltage V
Out, voltage V
OutThe i.e. read range of sensor amplifier for this reason.In the present embodiment, voltage Vo is (VDD-I
L* Z
Load), voltage V
ObBe (VDD-I
H* Z
Load), so voltage V
OutBe (I
L-I
H) * Zload.Compare with existing sensor amplifier shown in Figure 1, the sensor amplifier of the present invention no matter data of cell stores is logic high or logic low, its voltage range of reading sensor amplifier all more shown in Figure 1 doubles, and compare with sensor amplifier shown in Figure 2, have the advantage that circuit is simple and save circuit area.
Fig. 9 is a circuit diagram according to another embodiment of the present invention.First source/drain electrode of transistor T 91, T92, T93, T94 and T95 couples high voltage source VDD, and the grid of transistor T 91 couples the grid of transistor T 92 and T93, and the grid of transistor T 94 couples the grid of T95.Memory cell current source 91 couples second source/drain electrode and the grid of transistor T 91.Memory cell current source 91 is the electric current I of removing to read a storage unit gained with a fixed-bias transistor circuit
CellWhen the data of cell stores were logic high, the electric current of reading this storage unit gained with this fixed-bias transistor circuit was I
HWhen the data of cell stores were logic low, the electric current of reading this storage unit gained with this fixed-bias transistor circuit was I
LSecond source/drain electrode of transistor T 92 couples first impedance component 92 and comparer 95.Second source/drain electrode of transistor T 93 couples the grid of first source/drain electrode, transistor T 96 and the T98 of transistor T 96.Reference current source 94 couples the second source/drain electrode of transistor T 95 and the grid of transistor T 95.Second source/drain electrode of transistor T 94 couples first source/drain electrode, second impedance component 93 and the comparer 95 of transistor T 98.
When the data that store in the storage unit were logic high, read this storage unit resulting electric current with this fixed-bias transistor circuit this moment was I
H(that is I
Cell=I
H).Transistor T 91, T92 and T93 form a current mirror framework, and the electric current of the current mirror that feasible flow through first impedance component 92 and transistor T 96 and T98 form is I
HTransistor T 94 forms a current mirror framework with T95, and the electric current that is flowed out by transistor T 94 is I
Ref, but the electric current of the transistor T 98 of flowing through is I
HSo the electric current of second impedance component 93 of flowing through is I
L(because I
Ref=I
H+ I
L).Comparer 95 couples first impedance component 92 and second impedance component 93, and according to voltage Vo and V
ObExport a voltage V
Out, voltage V
OutThe i.e. read range of sensor amplifier for this reason.In the present embodiment, voltage Vo is (I
L* Z
Load), voltage V
ObBe (I
H* Z
Load), so voltage V
OutBe (I
H-I
L) * Zload.Compare with existing sensor amplifier shown in Figure 1, the sensor amplifier of the present invention no matter data of cell stores is logic high or logic low, its voltage range of reading sensor amplifier all more shown in Figure 1 doubles, and compare with sensor amplifier shown in Figure 2, have the advantage that circuit is simple and save circuit area.
When the data that store in the storage unit were logic low, read this storage unit resulting electric current with this fixed-bias transistor circuit this moment was I
L(that is I
Cell=I
H).Transistor T 91, T92 and T93 form a current mirror framework, and the electric current of the current mirror that feasible flow through first impedance component 92 and transistor T 96 and T98 form is I
LTransistor T 94 forms a current mirror framework with T95, and the electric current that is flowed out by transistor T 94 is I
Ref, but the electric current of the transistor T 98 of flowing through is I
LSo the electric current of second impedance component 93 of flowing through is I
H(because I
Ref=I
H+ I
L).Comparer 95 couples first impedance component 92 and second impedance component 93, and according to voltage Vo and V
ObExport a voltage V
Out, voltage V
OutThe i.e. read range of sensor amplifier for this reason.In the present embodiment, voltage Vo is (I
H* Z
Load), voltage V
ObBe (I
L* Z
Load), so voltage V
OutBe (I
L-I
H) * Zload.Compare with existing sensor amplifier shown in Figure 1, the sensor amplifier of the present invention no matter data of cell stores is logic high or logic low, its voltage range of reading sensor amplifier all more shown in Figure 1 doubles, and compare with sensor amplifier shown in Figure 2, have the advantage that circuit is simple and save circuit area.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (24)
1. a sensor amplifier couples a storage unit, comprising:
One first current lens unit, have one first output terminal and one second output terminal, couple a high voltage source, export this first electric current and export one second electric current in this first output terminal, wherein this second electric current twice that is this first electric current in this second output terminal according to one first electric current;
One second current lens unit has one the 3rd output terminal, couples a high voltage source, exports this reference current according to a reference current in the 3rd output terminal;
One first impedance component has one first resistance value, couples this second output terminal and a low-voltage source;
One second impedance component has this first resistance value, couples the 3rd output terminal and this low-voltage source; And
One the 3rd current lens unit, couple this first output terminal, this second output terminal and the 3rd output terminal, and with this first electric current reference current that is the 3rd current lens unit, the electric current of feasible this first impedance component of flowing through is this first electric current, and the electric current of this second impedance component of flowing through is one the 4th electric current.
2. sensor amplifier as claimed in claim 1 wherein also comprises a comparer, has two input ends and an output terminal, and wherein an input end couples this second output terminal, and another input end couples the 3rd output terminal, and this output terminal is in order to export a voltage difference.
3. sensor amplifier as claimed in claim 2, wherein this voltage difference is multiplied by this first resistance value for a difference of this first electric current and this reference current.
4. sensor amplifier as claimed in claim 1, wherein this storage unit is when storing the data of a logic level 1, accept this fixed-bias transistor circuit and produce a logic high electric current, this storage unit is accepted this fixed-bias transistor circuit and is produced a logic low electric current when storing the data of a logic level 0.
5. sensor amplifier as claimed in claim 4, wherein this reference current is this logic high electric current and this logic low electric current sum.
6. sensor amplifier as claimed in claim 1, wherein this first current lens unit also comprises:
One memory cell current source couples this low-voltage source, in order to this first electric current to be provided;
One the first transistor has one first source electrode, one first drain electrode and a first grid, and wherein this first source electrode couples this high voltage source, this first drain electrode and this first grid and couples this memory cell current source;
One transistor seconds has one second source electrode, one second drain electrode and a second grid, and wherein this second source electrode couples this high voltage source, and this second grid couples this first grid, and this second drain electrode couples this first impedance component and the 3rd current lens unit; And
One the 3rd transistor has one the 3rd source electrode, one the 3rd drain electrode and one the 3rd grid, and wherein the 3rd source electrode couples this high voltage source, and the 3rd grid couples this first grid, and the 3rd drain electrode couples the 3rd current lens unit.
7. sensor amplifier as claimed in claim 6, wherein a breadth length ratio of this transistor seconds is the twice of a breadth length ratio of this first transistor.
8. sensor amplifier as claimed in claim 1, wherein this second current lens unit also comprises:
One reference memory unit current source couples this low-voltage source, in order to this reference current to be provided;
One the 4th transistor has one the 4th source electrode, one the 4th drain electrode and one the 4th grid, and wherein the 4th source electrode couples this high voltage source, and the 4th drain electrode couples the 3rd current lens unit and this second impedance component; And
One the 5th transistor has one the 5th source electrode, one the 5th drain electrode and one the 5th grid, and wherein the 5th source electrode couples this high voltage source, and the 5th grid couples the 4th grid and the 5th drain electrode, and the 5th drain electrode couples this reference memory unit current source.
9. sensor amplifier as claimed in claim 1, wherein the 3rd current lens unit also comprises:
One the 6th transistor has one the 6th source electrode, one the 6th drain electrode and one the 6th grid, and wherein the 6th drain electrode couples this first impedance component and this first current lens unit, and the 6th source electrode couples this low-voltage source;
One the 7th transistor has one the 7th source electrode, one the 7th drain electrode and one the 7th grid, and wherein the 7th drain electrode couples this first current lens unit, the 6th grid and the 7th grid, and the 7th source electrode couples this low-voltage source; And
One the 8th transistor has one the 8th source electrode, one the 8th drain electrode and one the 8th grid, and wherein the 8th drain electrode couples this second impedance component and this second current lens unit, and the 8th grid couples the 7th grid, and the 8th source electrode couples this low-voltage source.
10. sensor amplifier as claimed in claim 1, wherein this first impedance component is the combination of a resistance, an electric capacity, an inductance or said modules.
11. sensor amplifier as claimed in claim 1, wherein this first impedance component is an active resistance.
12. sensor amplifier as claimed in claim 1, wherein this second impedance component is the combination of a resistance, an electric capacity, an inductance or said modules.
13. sensor amplifier as claimed in claim 1, wherein this second impedance component is an active resistance.
14. sensor amplifier as claimed in claim 1, wherein the 3rd electric current is this first electric current and the 4th electric current sum.
15. a sensor amplifier couples a storage unit, comprising:
One first impedance component couples a low-voltage source;
One second impedance component couples this low-voltage source;
One memory cell current source couples a low-voltage source, in order to one first electric current to be provided;
One reference memory unit current source couples this low-voltage source, in order to a reference current to be provided;
One the first transistor has one first source electrode, one first drain electrode and a first grid, and wherein this first source electrode couples a high voltage source, this first drain electrode and this first grid and couples this memory cell current source;
One transistor seconds has one second source electrode, one second drain electrode and a second grid, and wherein this second source electrode couples this high voltage source, and this second grid couples this first grid, and this second drain electrode couples this first impedance component;
One the 3rd transistor has one the 3rd source electrode, one the 3rd drain electrode and one the 3rd grid, and wherein the 3rd source electrode couples this high voltage source, and the 3rd grid couples this first grid;
One the 4th transistor has one the 4th source electrode, one the 4th drain electrode and one the 4th grid, and wherein the 4th source electrode couples this high voltage source, and the 4th drain electrode couples this second impedance component;
One the 5th transistor has one the 5th source electrode, one the 5th drain electrode and one the 5th grid, and wherein the 5th source electrode couples this high voltage source, and the 5th grid couples the 4th grid and the 5th drain electrode, and the 5th drain electrode couples this reference memory unit current source;
One the 6th transistor has one the 6th source electrode, one the 6th drain electrode and one the 6th grid, and wherein the 6th drain electrode couples this first impedance component and this second drain electrode, and the 6th source electrode couples this low-voltage source;
One the 7th transistor has one the 7th source electrode, one the 7th drain electrode and one the 7th grid, and wherein the 7th drain electrode couples the 3rd drain electrode, the 6th grid and the 7th grid, and the 7th source electrode couples this low-voltage source; And
One the 8th transistor has one the 8th source electrode, one the 8th drain electrode and one the 8th grid, and wherein the 8th drain electrode couples this second impedance component and the 4th drain electrode, and the 8th grid couples the 7th grid, and the 8th source electrode couples this low-voltage source.
16. sensor amplifier as claimed in claim 15, wherein this first transistor, this transistor seconds, the 3rd transistor, the 4th transistor and the 5th transistor are the PMOS transistor.
17. sensor amplifier as claimed in claim 15, wherein the 6th transistor, the 7th transistor and the 8th transistor are nmos pass transistor.
18. sensor amplifier as claimed in claim 15, wherein also comprise a comparer, have two input ends and an output terminal, wherein an input end couples this first impedance component and this second drain electrode, another input end couples this second impedance component and the 4th drain electrode, and this output terminal is in order to export a pressure drop difference of this first impedance and this second impedance.
19. sensor amplifier as claimed in claim 15, wherein this first impedance component and this second impedance component have one first resistance value, and this pressure drop difference is multiplied by this first resistance value for a difference of this first electric current and this reference current.
20. sensor amplifier as claimed in claim 15, wherein a breadth length ratio of this transistor seconds is the twice of a breadth length ratio of this first transistor.
21. sensor amplifier as claimed in claim 15, wherein this first impedance component is the combination of a resistance, an electric capacity, an inductance or said modules.
22. sensor amplifier as claimed in claim 15, wherein this first impedance component is an active resistance.
23. sensor amplifier as claimed in claim 15, wherein this second impedance component is the combination of a resistance, an electric capacity, an inductance or said modules.
24. sensor amplifier as claimed in claim 15, wherein this first impedance component is an active resistance.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200610071485 CN101042923B (en) | 2006-03-24 | 2006-03-24 | Read out amplifier |
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| CN 200610071485 CN101042923B (en) | 2006-03-24 | 2006-03-24 | Read out amplifier |
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| CN101042923A true CN101042923A (en) | 2007-09-26 |
| CN101042923B CN101042923B (en) | 2010-05-12 |
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| CN 200610071485 Expired - Fee Related CN101042923B (en) | 2006-03-24 | 2006-03-24 | Read out amplifier |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101777374A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Readout amplifier with process and current compensation |
| CN102044303A (en) * | 2009-10-14 | 2011-05-04 | 无锡华润上华半导体有限公司 | ROM (Read-Only Memory) |
| CN102592649A (en) * | 2011-01-06 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Flash EEPROM sensitive amplifier circuit |
| CN102722213A (en) * | 2012-06-26 | 2012-10-10 | 昆明物理研究所 | Photovoltaic detector read-out unit circuit applying inverted voltage follower |
| CN105027218A (en) * | 2013-03-08 | 2015-11-04 | 密克罗奇普技术公司 | Resistive random access memory (reram) and conductive bridging random access memory (cbram) cross coupled fuse and read method and system |
| CN106448736A (en) * | 2015-08-06 | 2017-02-22 | 复旦大学 | Method for generating reading reference current related to resistance value |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100205530B1 (en) * | 1996-04-24 | 1999-07-01 | 윤종용 | Sense amplifier |
| KR100308195B1 (en) * | 1999-09-30 | 2001-11-02 | 윤종용 | Sense amplifier circuit for use in a semiconductor memory device |
| CN100502244C (en) * | 2004-10-15 | 2009-06-17 | 宇田控股有限公司 | Switch operation amplifier and its acting method |
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- 2006-03-24 CN CN 200610071485 patent/CN101042923B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044303A (en) * | 2009-10-14 | 2011-05-04 | 无锡华润上华半导体有限公司 | ROM (Read-Only Memory) |
| CN101777374A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Readout amplifier with process and current compensation |
| CN101777374B (en) * | 2010-01-12 | 2014-01-29 | 上海宏力半导体制造有限公司 | Readout amplifier with process and current compensation |
| CN102592649A (en) * | 2011-01-06 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Flash EEPROM sensitive amplifier circuit |
| CN102722213A (en) * | 2012-06-26 | 2012-10-10 | 昆明物理研究所 | Photovoltaic detector read-out unit circuit applying inverted voltage follower |
| CN105027218A (en) * | 2013-03-08 | 2015-11-04 | 密克罗奇普技术公司 | Resistive random access memory (reram) and conductive bridging random access memory (cbram) cross coupled fuse and read method and system |
| CN105027218B (en) * | 2013-03-08 | 2019-07-26 | 密克罗奇普技术公司 | Resistive random access memory (RERAM) and conductive bridge-type random access memory (CBRAM) cross-linked fuse and read method and system |
| CN106448736A (en) * | 2015-08-06 | 2017-02-22 | 复旦大学 | Method for generating reading reference current related to resistance value |
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