CN100502244C - Switch operation amplifier and its acting method - Google Patents
Switch operation amplifier and its acting method Download PDFInfo
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- CN100502244C CN100502244C CNB2004100857177A CN200410085717A CN100502244C CN 100502244 C CN100502244 C CN 100502244C CN B2004100857177 A CNB2004100857177 A CN B2004100857177A CN 200410085717 A CN200410085717 A CN 200410085717A CN 100502244 C CN100502244 C CN 100502244C
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Abstract
This invention relates to a switching calculation amplifier. It is composed of: (1). a bias circuit, comprising: a No.1 current mirror, bias signal producer and a low output impedance buffer circuit; (2) an amplifier stage circuit, comprising: No.1 transistor, No.2 differential couple, No.3 current mirror, No.4 current mirror, No.5 current mirror, a sampling hole switch anda complementary sampling hold switch; (3). buffer stage circuit, comprising: a capacitor, a No.2 transistor and a No.3 transistor. Due to the calculation of switching calculation amplifier, the output voltage can be kept at stable condition.
Description
Technical field
The present invention relates to a kind of sample-and-hold circuit, particularly relate in a kind of sample-and-hold circuit design about switch operation amplifier (Switched OP Amplifier).
Background technology
Sample-and-hold circuit (Sample and Hold circuit) mainly is the front end that is used for analog-digital converter (ADC), to increase accuracy to the sampled data acquisition, so sample-and-hold circuit all is to be positioned at system position foremost, so its usefulness will directly determine the performance of whole system.In addition, for example the sampling of CD-ROM drive chip servo (servo) signal when the burning pattern also is by a sample-and-hold circuit with keeping, voltage output when guaranteeing sampling (sample) and keeping (hold) can maintain stable state, yet, sample-and-hold circuit has many kinds of circuit forms to realize, below will do explanation with the form of switched amplifier (Switched OP Amplifier).
As shown in Figure 1, be with the schematic diagram of switched amplifier as sample-and-hold circuit, when S/H=1 (switch conduction), be sampling state and V this moment
OUTWith V
NJoin to form negative feedback, make output voltage V
OUT=V
P, and allow capacitor C
hOn voltage followed voltage V
PWhen S/H=0 (switch opens circuit), be hold mode this moment, and output voltage is then by capacitor C
hOn voltage provide, make that the output voltage under the hold mode still can maintain voltage V
P
Shown in Figure 2, it is the inside built-up circuit figure of known technology about Fig. 1, and input signal is by V
PEnter amplification grade circuit 10 (being formed) by transistor M0～M12, and bias circuit 12 (being made up of transistor M15～M24) produces bp0, bpc, bnc, four groups of bias voltages such as bn0 with provide amplification grade circuit 10 and buffer stage circuit 14 (by transistor M13, M14 and capacitor C
hForm) use.
When sampling mode (switch S conducting H open circuit), at this moment, transistor M7, M8, M9, M10 are connected to separately bias voltage (bpc and bnc) and make transistor operate in service area (activeregion) separately and form path, and by the NZ point to capacitor C
hBe charged to predetermined magnitude of voltage (V
P), make negative feedback set up V
OUT=V
PWherein bias voltage bn0 and bnc produce by the transistor M15 and the M17 of diode connected mode (diode connected) according to two groups of current sources (current source) i1, i2 respectively; Bias voltage bnc and bn0 carry out primary current mirror current replication for transistor M18, M20, M19, M21 in the current mirroring circuit again, give the transistorized M22 of PMOS, M23, M24 again to produce bias voltage signal bpc and bp0.In addition, bias voltage bn0 again the transistor M0 in the feed-in amplification grade circuit 10 to produce a tail current (tail current) i
t, current i
tGive differential transistor M1 and M2 again and produce i (differential pair)
t1 and i
t2, i wherein
t1=(1/2) i
t+ Δ i, and i
t2=(1/2) i
t-Δ i.
On the other hand, i
t1 produces current i via the current mirror (current mirror) of PMOS transistor M3 and M5 again
t3, current i under sampling mode equally
t3 flow through transistor M7, M9, M11 lies in transistor M12 generation image current i through the pass of primary current mirror again
t4, add current i
t5 (current mirror by transistor M4, M6, M8 produces) are with the voltage V that determines that NZ is ordered
NZ, make V via the connected mode of feedback
OUT=V
N=V
P, and simultaneously to capacitor C
hCharging.
When keeping pattern (switch S open circuit H conducting), at this moment, transistor M7, M8, M9, M10 are connected to V separately
DDAnd GND, make above-mentioned transistor operate in cut-off region (cut off) formation and open circuit, at this moment, input signal V
PCan't influence V
OUT, and V
OUTValue will be because of capacitor C
hStored electric charge and remain on the final V of sampling mode
OUTValue makes output voltage be able to keep under the switching state of sampling and maintenance and still keeps certain value.
Yet, have considerable shortcoming with the circuit design of the switch operation amplifier of above-mentioned known technology, comprise drift as earthing potential.Under the sampling state, transistor M7, M8, M9, M10 are conducting (turn on), the operating current that generation is about 400 milliamperes (size of current is complied with transistorized size, as: W/L, and different); And when hold mode, above-mentioned transistor is then for ending (cut off) state, almost there is not operating current to produce, therefore, under switching state, the variation of electric current is because the effect of the inner stray resistance of circuit causes the earthy change of internal interface, and then influence the level of output voltage, even produce the situation of misoperation.
In addition, be to utilize two groups of bias current source i1 in the bias circuit of known technology, i2 is to produce bias voltage (bn0, bnc, bp0, bpc), therefore, desire changes the frequency range of this switch operation amplifier, method faster is directly to change bias current i1, i2, but because the bias voltage framework that repeatedly meets (cascade) at transistor is (under the transistor M15～M21), the change bias current may cause bias voltage (bnc and bpc) can't all be biased in transistorized best operating point under different situations, and make the part transistor exceed the scope of service area, cause the frequency range excursion of switch operation amplifier to be restricted.
On the other hand, for transistor M7, M8, M9, M10, its gate terminal voltage separately switches along with state and changes (change or at voltage bpc to V between voltage bnc to GND
DDBetween the change), therefore, to set (settle) respectively at bnc and bpc two magnitudes of voltage, as if both setting speed differences at the voltage that moment NMOS and the PMOS transistor gate of sampling are extreme, with causing the of short duration wild effect of output voltage, cause setting-up time to postpone more.In view of this, the invention provides a kind of design of switch operation amplifier of sample-and-hold circuit, the problem that is produced with effective solution known technology.
Summary of the invention
Purpose of the present invention is for providing a kind of switch operation amplifier that has than the regulated output voltage level.
Another object of the present invention is for providing a switch operation amplifier with preferable frequency range control characteristic.
A further object of the present invention is for providing a switch operation amplifier with quick setting output voltage characteristic.
The invention provides a kind of switch operation amplifier, comprise: a bias circuit, an amplification grade circuit and a buffer stage circuit.Bias circuit is by one first current mirror, one bias voltage signal generator, one low output impedance buffer circuit is formed, wherein this first current mirror is by a reference current (being produced by a current source) operation, mirror image end at this first current mirror produces one first image current, this first image current produces one first bias voltage signal when flowing through this bias voltage signal generator, the transistorized gate terminal of this first current mirror then provides second bias voltage signal, this low output impedance buffer circuit is first input signal with this second bias voltage signal, with a bias voltage input signal (being produced by resistor voltage divider circuit) is second input signal, exporting one the 3rd bias voltage signal, the bias voltage sizableness of the 3rd bias voltage signal and bias voltage input signal but have relative little output impedance.
The low output impedance buffer circuit comprises one the 4th transistor, one first differential to, one second current mirror, wherein this first differential right wherein transistor is that grid, drain electrode couple transistor npn npn, these first differential two right transistor drain ends connect the reference edge and the mirror image end of this second current mirror again, the first above-mentioned input signal is input into the 4th transistorized gate terminal, this second input signal is input into this first differential right input, and exports the 3rd bias voltage signal in this first differential right transistor for the grid leak utmost point couples the transistor npn npn end.
Amplification grade circuit, this amplification grade circuit is by a first transistor, one second is differential right, one the 3rd current mirror, the 4th current mirror, the 5th current mirror, an one sampling maintained switch and a complementary sampling maintained switch are formed, wherein this first transistor is opened by this first bias voltage signal, with provide these second differential right two transistor drain ends the reference edge of the 3rd current mirror that connects respectively and the reference edge electric current of the 4th current mirror, whether the image current of the 3rd current mirror is introduced the image current of the 3rd current mirror the reference edge of the 5th current mirror with decision by the 3rd bias voltage signal control, and the mirror image end of the 4th current mirror connects this sampling maintained switch and this complementation sampling maintained switch, and wherein these second differential two right transistorized gate terminal respectively as amplification grade circuit just, the negative voltage input.
The buffer stage circuit, the transistor seconds and the 3rd transistor that comprise an electric capacity and two series connection, wherein should take a sample maintained switch when sample time, by the 3rd bias voltage signal control this sampling maintained switch path so that the image current of the 4th current mirror to the charging of this electric capacity, the image current of the 5th current mirror is also to this electric capacity charging simultaneously, second differential just right up to this, when the input voltage of negative voltage input equates, this electric capacity stops charging, the terminal voltage of this electric capacity is then as the input signal of this transistor seconds, the drain electrode of this transistor seconds is as signal output part and feed back to this second differential right negative voltage input, this sampling maintained switch is when the retention time, this sampling maintained switch will be closed, to cut off the image current of the 5th current mirror, with the time should complementation the sampling maintained switch open, to keep the image current of the 4th current mirror.
Description of drawings
By below in conjunction with the detailed description of accompanying drawing, can understand the plurality of advantages of foregoing and the present invention easily, wherein:
Fig. 1 is the schematic diagram of sample-and-hold circuit.
Fig. 2 is the inside built-up circuit figure of known technology about Fig. 1.
Fig. 3 is the inside built-up circuit figure of the switch operation amplifier of one embodiment of the invention.
The reference numeral explanation
10,20 amplification grade circuits, 12,22 bias circuits
14,24 buffer stage circuit, 26 sampling maintained switchs
28 complementary sampling maintained switch 220 low output impedance buffer circuits
Embodiment:
Switch operation amplifier provided by the invention can improve known technology when switching sampling/hold mode, avoids the electric current instability to cause problems such as internal interface earth potential variation.Below enumerate a preferred embodiment with explanation the present invention, but those skilled in the art should know that this only is one for example, and be not in order to limit invention itself.The detailed description of relevant this preferred embodiment is as follows.
Switch operation amplifier as shown in Figure 3 comprises: an amplification grade circuit 20, a bias circuit 22 and a buffer stage circuit 24.Wherein bias circuit 22 comprises one first current mirror (transistor M15, M16) and low output impedance buffer circuit 220 (transistor M18～M22), current source is in order to produce a reference current i1, and produce bias voltage signal bp0 via the gate terminal of two-transistor M15, the M16 of first current mirror, in addition, utilize image current i2 that the mirror image end of first current mirror produces then to produce bias voltage signal bn0 via a bias voltage signal generator (the diode-type transistor M17 that couples as the grid on the figure, drain electrode).Bias voltage signal bn0 can provide the transistor M0 of amplification grade circuit 20 to produce tail current it (tail current); Bias voltage signal bp0 is then in order to drive the PMOS transistor M14 of buffer stage circuit 24.
220 of low output impedance buffer circuits differentially are made up of (transistor M19, M20) and second current mirror (transistor M21, M22) transistor M18, first, and wherein the grid of M18 couples mutually with the grid of M15, M16, and is driven by bias voltage signal bp0.In addition, the drain electrode of M18 couples the source electrode of M19, M20, and the grid of transistor M19 couples bias voltage input signal boc_in, and the grid of M20 couples the drain electrode that is coupled to transistor M22 mutually with its drain electrode.The grid of the transistor M21 of second current mirror, drain electrode more couple the drain electrode of M19 except that the grid that couples M22.
Bias voltage signal bp0 is in order to driving transistors M18, and bias voltage input signal boc_in passes through differential to reaching the current mirror that transistor M21, M22 form that transistor M19, M20 form, to produce another bias voltage signal boc, wherein bias voltage input signal boc_in is obtained by a resistor voltage divider circuit (not shown).Therefore, bias voltage signal boc is driven the transistor M7 and the M9 of amplification grade circuit 20, and offers transistor M8 and the grid bias of M10 under sampling state (switch S conducting).It should be noted that buffer circuit herein has less output impedance (output impedance), and utilize second current mirror (transistor M21, M22), make voltage V as load
Boc_inEqual voltage V
Boc, drive the transistor (M7, M8, M9, M10, M8a) of amplification grade circuit 20 so that stable bias voltage signal boc to be provided.
Utilize the driving of bias voltage signal boc and the structure of the 3rd current mirror (transistor M3, M5, M7), in mirror image end (transistor M5 one side) the generation image current i of the 3rd current mirror
T3, current i wherein
T3Be similar to current i approximately
T1On the other hand, under the sampling state (switch S conducting, H open circuit), the transistor M8 conducting of sampling maintained switch 26 makes current i
T4Be similar to current i approximately
T2According to the structure of the 5th current mirror (transistor M9, M11, M12), transistor M9 couples the current i of the M11 that flows through with the drain electrode of M7, M8 respectively mutually with the drain electrode of the transistor M10 of sampling maintained switch 26
T3Be able to obtain the current i of transistor M12 through the current replication of the 5th current mirror
T5
In addition, also comprise a complementary sampling maintained switch 28 (being made of a PMOS transistor M8a) in the amplification grade circuit 20, the source electrode of M8a and M8 all is coupled to the drain electrode of transistor M6, and the drain electrode of M8a is ground connection then.The effect of transistor M8a is in hold mode (switch H conducting, the S open circuit) under, (sampling maintained switch 26 is closed when transistor M8 ends, complementary sampling maintained switch 28 is opened), provide a current path by transistor M8a, make the image current of transistor M6 be able to be directed at earth terminal (GND) via transistor M8a.Therefore, no matter under sampling/hold mode, the electric current in the amplification grade circuit 20 all can be kept stable.
With preferred embodiment of the present invention, during state, at this moment, transistor M7, M8, M9, M10 gate terminal voltage are all bias voltage boc in sampling, thus above-mentioned transistor all operate in service area (active region) and form channel status, and by the NZ point to capacitor C
hCharge to a predetermined magnitude of voltage, make negative feedback set up (can simultaneously with reference to figure 1), the output voltage V of this moment
OUT=V
N=V
PWhen hold mode (switch S open circuit, H conducting), at this moment, transistor M8, M10 are connected to V separately
DDWith GND, make transistor M8, M10 close and form and open circuit, cause input signal V
PCan't influence V
OUT, and output voltage V
OUTWill be because of in sampling capacitor C during state
hThe electric charge that is charged and V when remaining on the sampling state
OUTValue.In addition, though the transistor M8 in the amplification grade circuit 20 by a transistor M8a conducting is arranged in addition, and transistor M7, M9 also continue to keep conducting state, makes hold mode and total work electric current of sampling state keep definite value.
The design of switch operation amplifier of the present invention has following advantage:
(1) in amplification grade circuit 20 of the present invention, because the grid bias of transistor M7, M9 all is fixed on boc, make the eternal conducting of M7, M9, though adding transistor M8 ends in hold mode, but with then conducting of time transistor M8a, make the electric current of transistor M6, this side of M8a be imported GND smoothly, and then make the total current in the amplification grade circuit 20 under sampling state and hold mode, almost remain unchanged, allow the GND current potential of circuit inside and the outside not violent change of reason electric current of GND current potential, and influence the level of output voltage.
(2) in bias circuit 22 of the present invention, only utilize one group of bias current source, to produce amplification grade circuit 20 and buffer stage circuit 24 required bias voltage boc, bn0 and bp0, make that each transistorized bias point compared to the prior art in the switch operation amplifier, more easy to control in the service area, and then make the control elasticity more of frequency range.
(3) enter moment of sampling mode in the present invention in the maintenance pattern, the grid voltage of transistor M8 is (by V
DDBecome boc) and the grid voltage (becoming boc) of transistor M10 by GND receive bias voltage boc simultaneously because bias voltage boc is near V
DDWith the average place of GND, make electric charge moment neutralization to quicken the setting-up time of transistor M8, M10 grid voltage, therefore, voltage that NZ is ordered and output voltage V
OUTCan be set to predetermined voltage fast, promote service speed.
Though the present invention with the preferred embodiments explanation as above, so it is not in order to limit the present invention's spirit and invention entity in the foregoing description.Therefore, the modification of being done under the prerequisite that does not break away from spirit of the present invention and scope all should be included in the application's the scope of claim.
Claims (10)
1. switch operation amplifier comprises at least:
One bias circuit provides one first bias voltage signal, one second bias voltage signal and one the 3rd bias voltage signal to amplification grade circuit and buffer stage circuit;
One amplification grade circuit, comprise a first transistor, one second is differential right, one the 3rd current mirror, the 4th current mirror, the 5th current mirror, an one sampling maintained switch and a complementary sampling maintained switch, wherein this first transistor is by this first bias voltage signal control, with provide these second differential right two transistors the reference edge of the 3rd current mirror that connects respectively and the reference edge electric current of the 4th current mirror, whether the image current of the 3rd current mirror is introduced the image current of the 3rd current mirror the reference edge of the 5th current mirror with decision by the 3rd bias voltage signal control, and the mirror image end of the 4th current mirror connects this sampling maintained switch and this complementation sampling maintained switch, the maintained switch of wherein should sampling maintained switch and this complementation taking a sample is conducting state simultaneously not, keeping the image current of the 4th current mirror, these second differential two right transistorized gate terminal are respectively as just, the negative voltage input; And
One buffer stage circuit, be used for the output of class buffer amplifier circuit, it comprises an electric capacity, a transistor seconds and one the 3rd transistor, this electric capacity one end is connected to the grid of sampling maintained switch and transistor seconds, the drain electrode of this transistor seconds is connected to the 3rd transistor and as signal output part and feed back to this second differential right negative voltage input, and the 3rd transistor is by this second bias voltage signal control.
2. switch operation amplifier as claimed in claim 1, this bias circuit wherein, comprise one first current mirror, a bias voltage signal generator, a low output impedance buffer circuit, and operate on this first current mirror with a reference current, produce this second bias voltage signal, this bias voltage signal generator connects this first current mirror, produces this first bias voltage signal, this low output impedance buffer circuit connects this first current mirror and with a bias voltage input signal, to produce the 3rd bias voltage signal.
3. switch operation amplifier as claimed in claim 2, wherein above-mentioned low output impedance buffer circuit comprises one the 4th transistor, one first differential to, one second current mirror, wherein the 4th transistor is with this second bias voltage signal control, and be connected to that this is first differential right, this is first differential to being connected with second current mirror, make this bias voltage input signal be input to that this is first differential right, to produce the 3rd bias voltage signal.
4. switch operation amplifier as claimed in claim 2, wherein this reference current is produced by a current source.
5. switch operation amplifier as claimed in claim 2, wherein this bias voltage input signal produces by a resistor voltage divider circuit.
6. switch operation amplifier as claimed in claim 2, wherein the bias voltage of the 3rd bias voltage signal and this bias voltage input signal size identical when but the 3rd bias voltage signal has relatively little output impedance.
7. switch operation amplifier as claimed in claim 2, wherein this bias voltage signal generator uses a diode-type transistor.
8. switch operation amplifier as claimed in claim 1, wherein this sampling maintained switch by the series connection one the 5th transistor AND gate 1 the 6th transistor formed, by the 3rd bias voltage signal to determine the open and close of this sampling maintained switch.
9. switch operation amplifier as claimed in claim 1, should complementation sampling maintained switch be a transistor wherein, its source electrode couples the mirror image end of the 4th current mirror, its then ground connection that drains, and grid is controlled to determine the open and close of this complementation sampling maintained switch by the 3rd bias voltage signal.
10. a sampling is switched the method for running with maintenance, be applicable to that one switches in the operational amplifier, this switch operation amplifier comprises a bias circuit, an amplification grade circuit and a buffer stage circuit that produces one the 3rd bias voltage signal, this amplification grade circuit comprises that at least one second is differential to, one the 4th current mirror, one the 5th current mirror, a sampling maintained switch and a complementary sampling maintained switch, this buffer stage circuit comprises an electric capacity at least, wherein this electric capacity is used to cushion the output from described amplification grade circuit, and this method comprises the following steps:
When taking a sample state, with the 3rd bias voltage signal control this sampling maintained switch the path conducting so that the image current of the image current of the 4th current mirror and the 5th current mirror to the charging of this electric capacity, and control an output voltage by this electric capacity and feed back to the second differential right negative voltage input, equate up to the input voltage of this second differential right positive and negative voltage input end; And
When carrying out hold mode, this sampling maintained switch will be closed, with the image current of the image current that cuts off the 5th current mirror and the 4th current mirror to this electric capacity charging, this electric capacity discharges to keep the level of this output voltage, should open by complementation sampling maintained switch simultaneously, to keep the image current of the 4th current mirror.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100857177A CN100502244C (en) | 2004-10-15 | 2004-10-15 | Switch operation amplifier and its acting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100857177A CN100502244C (en) | 2004-10-15 | 2004-10-15 | Switch operation amplifier and its acting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1588805A CN1588805A (en) | 2005-03-02 |
| CN100502244C true CN100502244C (en) | 2009-06-17 |
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ID=34605167
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100857177A Expired - Fee Related CN100502244C (en) | 2004-10-15 | 2004-10-15 | Switch operation amplifier and its acting method |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101042923B (en) * | 2006-03-24 | 2010-05-12 | 财团法人工业技术研究院 | Read out amplifier |
| US7777573B2 (en) * | 2008-05-29 | 2010-08-17 | Himax Technologies Limited | Operational amplifier having adjustable bias current and related source driver of display thereof |
| US8471549B2 (en) * | 2010-05-09 | 2013-06-25 | Richwave Technology Corp. | Power detector |
| CN102570988B (en) * | 2010-12-23 | 2014-12-10 | 联咏科技股份有限公司 | Amplifier device |
| JP5917858B2 (en) * | 2011-08-29 | 2016-05-18 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
| IT201700021364A1 (en) * | 2017-02-24 | 2018-08-24 | St Microelectronics Srl | OPERATIONAL AMPLIFIER, CIRCUIT, EQUIPMENT AND CORRESPONDENT PROCEDURE |
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2004
- 2004-10-15 CN CNB2004100857177A patent/CN100502244C/en not_active Expired - Fee Related
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