CN102592649A - Flash EEPROM sensitive amplifier circuit - Google Patents
Flash EEPROM sensitive amplifier circuit Download PDFInfo
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- CN102592649A CN102592649A CN2011100016190A CN201110001619A CN102592649A CN 102592649 A CN102592649 A CN 102592649A CN 2011100016190 A CN2011100016190 A CN 2011100016190A CN 201110001619 A CN201110001619 A CN 201110001619A CN 102592649 A CN102592649 A CN 102592649A
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- voltage
- reference current
- gain resistor
- current source
- storage unit
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Abstract
The invention discloses a Flash EEPROM sensitive amplifier circuit which comprises a reference current source, a P-type cascade negative feedback loop and a load gain resistor; the reference current source is used for providing reference current for the sensitive amplifier circuit; the P-type cascade negative feedback loop adopts a PMOS (P-channel Metal Oxide Semiconductor) transistor for realizing the cascade structure, and is used for positioning a voltage clamp at the bit line of a reference unit or a storage unit at the preset bias potential; and the reference current source, the P-type cascade negative feedback loop and the load gain resistor are sequentially connected in series, and the load gain resistor is grounded. The current generated by the reference current source is shunted through the reference unit or the storage unit and then flows through the load gain resistor to generate detection voltage or reference detection voltage, both the detection voltage and the reference detection voltage are transmitted to a subsequent differential comparator, and the data value in the storage unit is further obtained by comparing the detection voltage and the reference detection voltage. The Flash EEPROM sensitive amplifier circuit can work under the low power supply voltage and provide high drain terminal voltage, thereby improving the reading speed.
Description
Technical field
The present invention relates to a kind of amplifying circuit, particularly relate to the sensitive amplifying circuit of a kind of Flash EEPROM.
Background technology
Continuous progress along with semiconductor fabrication process and IC design ability; People can be comprising that processor, storer, mimic channel, interface logic even radio circuit are integrated on the chip; Here it is system level chip (System-on-Chip, SoC).Along with data throughout constantly rises and the system low-power consumption requirement, system level chip is increasing to the demand of storer.It is occupied to it is predicted that about 90% silicon area in the future will be had a storer of difference in functionality, and in-line memory will become the deciding factor of domination total system.Non-volatility memorizer (is representative with flash, EEPROM) with its power down not the characteristic of obliterated data become important component part indispensable in the in-line memory, it is improving system performance, is improving chip reliability, is reducing cost and aspect such as power consumption has all played positive effect.
Improve constantly along with what technological level and system low-power consumption required; Chip power supply voltage constantly reduces; The performance of reading to Flash EEPROM has proposed increasingly high requirement, therefore designs one and stablizes, and the sensitive amplifying circuit of sensing circuit is of great practical significance reliably.
Summary of the invention
The technical matters that the present invention will solve provides the sensitive amplifying circuit of a kind of Flash EEPROM, and it can be operated under the low supply voltage, and high drain terminal voltage is provided, and improves reading speed.
For solving the problems of the technologies described above, the sensitive amplifying circuit of Flash EEPROM of the present invention comprises:
One reference current source is used for reference current to this sensitivity amplifying circuit being provided;
One P class cascade feedback loop, it adopts PMOS pipe to realize cascade structure, is used for voltage clamp with reference unit bit line or storage unit bit line in preset bias potential;
One load gain resistor, one of which end are the voltage detecting end, and the other end is an earth terminal ground connection, are used for producing detection voltage and reference detection voltage;
Said reference current source, P class cascade feedback loop are connected with the load gain resistor successively; The electric current that said reference current source the produces said load gain resistor of after reference unit or storage unit shunting, flowing through, generation said with reference to detecting voltage or detecting voltage and send into follow-up differential comparator.
Said P class cascade negative feedback loop route PMOS pipe constitutes with amplifier, and an input end of this amplifier is said preset bias potential, the source end that its another said PMOS of input termination manages, the grid of the said PMOS pipe of its output termination.
Said reference current source, said reference unit bit line or storage unit bit line all with the source end of PMOS pipe, promptly another input end of said amplifier joins.
The drain terminal of the said PMOS pipe of said load gain resistor voltage detecting termination, this end while is as the input end of said follow-up differential comparator.
Two ends are leaked in the voltage detecting terminal voltage of said reference unit bit-line voltage or storage unit bit-line voltage and the said load gain resistor said PMOS pipe source of living apart, and can optimize respectively and be provided with and do not influence each other.
Because what said sense amplifier adopted is the PMOS cascade structure; Therefore voltage is the highest can to rise to the overdrive voltage that only hangs down two PMOS than supply voltage at the detection voltage of output terminal or with reference to detecting; Very near the current potential of supply voltage, so it can be operated under the low supply voltage, and high drain terminal voltage is provided; For example can high drain voltage to the 1v can be provided still under the 1.2v supply voltage; When supply voltage raises, can continue to raise, thereby improve the voltage margin and the reading speed of sense amplifier.Simultaneously both sides are leaked in said voltage detecting terminal voltage and the said bit-line voltage said PMOS pipe source of living apart, can guarantee that working power voltage descends after, the decline of voltage detecting terminal voltage can not cause the synchronous decline of bit-line voltage, guarantees that read operation is normally carried out under the low-voltage.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is sensitive amplification circuit structure figure of the present invention;
Embodiment
Be illustrated in figure 1 as circuit structure of the present invention, it mainly comprises: a reference current source Is; One P class cascade feedback loop NFL, it adopts the PMOS pipe to realize cascade structure; One load gain resistor R, one of which end are voltage detecting end SAI, and the other end is an earth terminal ground connection.Said reference current source Is, P class cascade feedback loop NFL connect with load gain resistor R successively.Said P class cascade negative-feedback circuit NFL is made up of PMOS pipe Mp and amplifier A, and the input end of this amplifier A is preset bias potential Vref, and its another said PMOS of input termination manages the source end of Mp, the grid of the said PMOS pipe of its output termination Mp; Said reference current source Is, said reference unit bit line or storage unit bit line BL all manage the source end of Mp with PMOS, another input end of promptly above-mentioned amplifier A joins; The voltage detecting end SAI of said load gain resistor R connects the drain terminal of said PMOS pipe Mp, and this end while is as the input end of follow-up differential comparator; Two ends are leaked in the voltage detecting end SAI voltage of the bit line BL voltage of said reference unit bit line or storage unit and the said load gain resistor R said PMOS pipe source of living apart, and can optimize respectively and be provided with and do not influence each other.
During work; Said P class cascade feedback loop NFL with the voltage clamp of reference unit bit line or storage unit bit line BL in preset bias potential Vref; Said bit line BL voltage is not changed with the conducting electric current of storage unit or reference unit, thereby in the read operation process, make storage unit and reference cell current keep stable amplitude.Said reference current source Is is used for reference current to this sensitivity amplifying circuit being provided; This reference current said load gain resistor R that after the shunting of reference unit or storage unit, flows through; The reference that produces detects voltage or detects voltage and send into follow-up differential comparator by voltage detecting end SAI; Detect voltage and detect voltage through this reference relatively, thereby obtain the data value in the storage unit.
Above-mentionedly be merely preferred embodiment of the present invention, can not limit practical range of the present invention with this, promptly all according to any modification and extension that the present invention did, all belong to protection scope of the present invention.
Claims (5)
1. the sensitive amplifying circuit of Flash EEPROM is characterized in that, comprising:
One reference current source is used for reference current to this sensitivity amplifying circuit being provided;
One P class cascade feedback loop, it adopts PMOS pipe to realize cascade structure, is used for voltage clamp with reference unit bit line or storage unit bit line in preset bias potential;
One load gain resistor, one of which end are the voltage detecting end, and the other end is an earth terminal ground connection, are used for producing detection voltage and reference detection voltage;
Said reference current source, P class cascade feedback loop are connected with the load gain resistor successively; The electric current that said reference current source the produces said load gain resistor of after reference unit or storage unit shunting, flowing through, generation said with reference to detecting voltage or detecting voltage and send into follow-up differential comparator.
2. circuit as claimed in claim 1; It is characterized in that: said P class cascade negative feedback loop route PMOS pipe constitutes with amplifier; One input end of this amplifier is said preset bias potential, the source end that its another said PMOS of input termination manages, the grid of the said PMOS pipe of its output termination.
3. according to claim 1 or claim 2 circuit is characterized in that: said reference current source, said reference unit bit line or storage unit bit line all with the source end of PMOS pipe, promptly another input end of said amplifier joins.
4. according to claim 1 or claim 2 circuit is characterized in that: the drain terminal of the said PMOS pipe of said load gain resistor voltage detecting termination, this end are simultaneously as the input end of said follow-up differential comparator.
5. according to claim 1 or claim 2 circuit; It is characterized in that: two ends are leaked in the bit-line voltage of said reference unit bit line or storage unit and the voltage detecting terminal voltage of the said load gain resistor said PMOS pipe source of living apart, and can optimize respectively and be provided with and do not influence each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100016190A CN102592649A (en) | 2011-01-06 | 2011-01-06 | Flash EEPROM sensitive amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100016190A CN102592649A (en) | 2011-01-06 | 2011-01-06 | Flash EEPROM sensitive amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102592649A true CN102592649A (en) | 2012-07-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100016190A Pending CN102592649A (en) | 2011-01-06 | 2011-01-06 | Flash EEPROM sensitive amplifier circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN102592649A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6205073B1 (en) * | 2000-03-31 | 2001-03-20 | Motorola, Inc. | Current conveyor and method for readout of MTJ memories |
| CN101042923A (en) * | 2006-03-24 | 2007-09-26 | 财团法人工业技术研究院 | Read out amplifier |
| US20080165592A1 (en) * | 2007-01-09 | 2008-07-10 | Sony Corporation | Semiconductor memory device, sense amplifier circuit and memory cell reading method |
-
2011
- 2011-01-06 CN CN2011100016190A patent/CN102592649A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6205073B1 (en) * | 2000-03-31 | 2001-03-20 | Motorola, Inc. | Current conveyor and method for readout of MTJ memories |
| CN101042923A (en) * | 2006-03-24 | 2007-09-26 | 财团法人工业技术研究院 | Read out amplifier |
| US20080165592A1 (en) * | 2007-01-09 | 2008-07-10 | Sony Corporation | Semiconductor memory device, sense amplifier circuit and memory cell reading method |
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| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120718 |