CN101033968B - Monitoring apparatus suitable for interferometric fiber optic gyroscope - Google Patents
Monitoring apparatus suitable for interferometric fiber optic gyroscope Download PDFInfo
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- CN101033968B CN101033968B CN2007100629174A CN200710062917A CN101033968B CN 101033968 B CN101033968 B CN 101033968B CN 2007100629174 A CN2007100629174 A CN 2007100629174A CN 200710062917 A CN200710062917 A CN 200710062917A CN 101033968 B CN101033968 B CN 101033968B
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Abstract
This invention relates to a kind of monitoring device apply to interference type fiber-optic gyro. The first processor D4 receive gyro output serial port data, pin_1 signal, pin_2 signal, light-source temperature-control fault0_1 signal, light-source temperature-control fault1_1 signal, light-source temperature-control fault0_2 signal, light-source temperature-control fault1_2 signal, power 3V3_DP1 signal. The first processor's level conversion circuit receives data information output by first processor D4; the second processor D8 respectively output power supply control signal to power supply control switch D10 of gyro sensing circuit and secondary light source. The invention adopts two CPU redundant back-up designed monitoring device, the first CPU design to receive interference type fiber-optic gyro output parameter, through parcel then output; the second one CPU design to monitor interference type fiber-optic gyro's working state, at same time monitor the working state of first CPU, also can be used as communication backup of first CPU. Such monitoring device could real-time handle different kinds of working order of triaxiality fiber-optic gyro, and according to triaxiality fiber-optic gyro defined malfunction to process relative disposing, advance the reliability of monitoring device.
Description
Technical field
The present invention relates to a kind of supervising device, more particularly say, be meant a kind of supervising device that adopts two CPU redundancy backup designs, first CPU is used to receive the parameter of interference optical fiber top output, output after packing; Second CPU is used to monitor the duty of interference optical fiber top, also the duty of first CPU monitored simultaneously, also can be used as the backup communication of first CPU.
Background technology
Because optical fibre gyro has mechanical gyro and the incomparable advantage of laser gyro, and along with reaching its maturity of production technology, optical fibre gyro constantly expands its range of application; In some specific application, the environment for use of optical fibre gyro is comparatively abominable as electromagnetic interference (EMI), x radiation x, vacuum insulation etc.; When optical fibre gyro was worked in these environment, temporary inefficacy or operation irregularity may appear in its light path and circuit devcie, and then can from inefficacy or abnormality recover gyro if optical fibre gyro is applied certain external control this moment.And the most gyros that use are at present only protected at the susceptible parts in gyro inside, and do not adopt any outer monitoring measure; Though this way can be simplified technical indicators such as the volume, weight of whole gyro, under some bad working environment, but can't realize optical fibre gyro from lost efficacy or the abnormal work state under recovery certainly.
Summary of the invention
The purpose of this invention is to provide a kind of supervising device that is applicable to interference optical fiber top, this supervising device is finished monitoring to the optical fibre gyro duty by designing two CPU, and failure condition is handled.
The present invention is a kind of supervising device that is applicable to interference optical fiber top, is made up of the level shifting circuit of the level shifting circuit of first processor D4, the second processor D8, first processor, second processor and first processor power control switch D9, gyro testing circuit power switch D10 and secondary light source power control switch D11;
Described first processor D4 receives serial data, PIN_1 signal, PIN_2 signal, light source temperature control Fault0_1 signal, light source temperature control Fault1_1 signal, light source temperature control Fault0_2 signal, light source temperature control Fault1_2 signal, the power supply 3V3_DP1 signal of gyro output;
The level shifting circuit of described first processor receives the data message of described first processor D4 output;
The level shifting circuit of described second processor receives the data message of described second processor D8 output;
Described second processor D8 out-put supply control signal respectively gives gyro testing circuit power control switch D10 and secondary light source power control switch D11.
The advantage of supervising device of the present invention is: (1) adopts two processor chips that the duty of three axis optical fibre gyro is monitored in real time, has improved the stability of gyro output information; (2) in second processor by fault judgement threshold value (PIN threshold value lower limit FH is set, upper limit 199H, temperature threshold lower limit 000H, upper limit 5A0H) judge the fault of gyro, and handle in real time, improve the serviceability of gyro, prolonged the mission life of gyro; (3) photodetector (PIN) output signal and gyro internal temperature signal are monitored, can be avoided gyro owing to the mortality that the influence of environment and other factors causes is damaged; (4) by the hardware design of dual processor and interface chip thereof and the software flow of packing data output, realize the hardware redundancy backup of optical fibre gyro and external communication, also made the status information of gyro and angular velocity information together export; Increased the reliability of the external communication of gyro, also provide condition for further research to gyro.
Description of drawings
Fig. 1 is the structured flowchart of supervising device of the present invention.
Fig. 2 A is the circuit theory diagrams of first processor.
Fig. 2 B is the circuit theory diagrams of second processor.
Fig. 3 A is first cpu power gauge tap schematic diagram.
Fig. 3 B is gyro testing circuit power supply control principle figure.
Fig. 3 C is secondary light source power supply control principle figure.
Fig. 4 A is the photoelectric switching circuit schematic diagram.
Fig. 4 B is the first photoelectric commutator signal pre-processing circuit schematic diagram.
Fig. 4 C is the second photoelectric commutator signal pre-processing circuit schematic diagram.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
See also shown in Figure 1, the present invention is a kind of supervising device that is applicable to interference optical fiber top, this supervising device is by first processor D4, the second processor D8, the level shifting circuit of first processor, the level shifting circuit of second processor, and first processor power control switch D9, gyro testing circuit power switch D10 and secondary light source power control switch D11 form, first processor D4 receives the serial data of gyro output, the PIN_1 signal, the PIN_2 signal, light source temperature control Fault0_1 signal, light source temperature control Fault1_1 signal, light source temperature control Fault0_2 signal, light source temperature control Fault1_2 signal, power supply 3V3_DP1 signal, the level shifting circuit of first processor receives the data message of first processor D4 output, the level shifting circuit of second processor receives the data message of second processor D8 output, and second processor D8 out-put supply control signal respectively gives gyro testing circuit power control switch D10 and secondary light source power control switch D11.
In the present invention, the level shifting circuit of first processor is made up of incoming level conversion chip D3 and transmission level conversion chip D2; The level shifting circuit of second processor is made up of incoming level conversion chip D6 and transmission level conversion chip D7.
In the present invention, first processor D4 chooses the TMS320LF240XA family chip, the second processor D8 chooses the TMS320LF240XA family chip, incoming level conversion chip in the level shifting circuit of the level shifting circuit of first processor and second processor is chosen the MAX3371 chip, the transmission level conversion chip is chosen the MAX3371 chip, first processor power control switch D9 chooses the TPS2024 chip, gyro testing circuit power switch D10 chooses the TPS2024 chip, and secondary light source power supply control transmission level conversion chip system switch D11 chooses the TPS2024 chip.
The present invention adopts the supervising device of two CPU redundancy backup designs, and first CPU is used to receive the parameter of interference optical fiber top output, output after packing; Second CPU is used to monitor the duty of interference optical fiber top, also the duty of first CPU monitored simultaneously, also can be used as the backup communication of first CPU.Such supervising device can be handled the various duties of three axis optical fibre gyro in real time, and carries out the processing of correlativity according to the fault of three axis optical fibre gyro definition, and has improved the reliability of supervising device.
The connection of each terminal is as follows in the hardware circuit of the present invention:
(1) each terminal connection of first processor D4 (TMS320LF2403A chip) is: shown in Fig. 2 A
The power input 6,10,27,35,52,56 of first processor D4, AD conversion power supply input end 21, phaselocked loop power supply input end 39 link to each other with the output terminal 6 of switch D9, AD changes high reference voltage end 20 and links to each other with the voltage output end 4 of Voltage Reference source chip C3, and FLASH programming power supply input end 60 connects+the 5V power supply;
The ground input end 5,9,26,51,55 of D4 connects digitally, and power drives interrupting input end 36 connects digitally, and AD converter power supply ground input end 22 connects simulation ground, and the low reference voltage input terminal 19 of AD converter connects simulation ground.
The end 7,8,29,30,31,32,33 of D4 connects the end 8,7,6,4,2,3,5 that JTAG downloads socket X3 respectively, the end 8 of JTAG download socket X3 connects the back and connects with the end 6 of switch D9 with resistance R 4, end 7 connects the back with resistance R 3 and connects with the end 6 of switch D9, end 1 connects with the end 6 of switch D9, holds 9 to connect digitally.
The AD conversion input end 17 of D4 connects with the end 1 of the pre-process circuit A2 of photodetector by resistance R 25, the end 8 of pre-process circuit A2 connects+connect simulation ground by capacitor C 47 behind the 5V power supply, end 4 connects-connect simulation ground by capacitor C 46 behind the 5V power supply, end 3 connects simulation ground by capacitor C 45, and connect gyro by resistance R 21, be connected in end 1 after resistance R 24 and capacitor C 48 are in parallel and hold between 2, end 2 connects simulation ground by resistance R 23, capacitor C 44, and connect with the end 7 of photoelectric commutator by resistance R 22, photoelectric commutator is a custom circuit; AD conversion input end 18 connects with the end 1 of the pre-process circuit A4 of photodetector by resistance R 30, the end 8 of pre-process circuit A4 connects+connect simulation ground by capacitor C 52 behind the 5V power supply, end 4 connects-connect simulation ground by capacitor C 51 behind the 5V power supply, end 3 connects simulation ground by capacitor C 50, and connect gyro by resistance R 26, be connected in end 1 after resistance R 29 and capacitor C 53 are in parallel and hold between 2, end 2 connects simulation ground by resistance R 28, capacitor C 49, and connects with the end 7 of photoelectric commutator by resistance R 27;
The startup ROM of D4 enables input end 23 and links to each other with the end 6 of switch D9 after resistance R 17;
The input end of clock 24 of D4 is connected with crystal oscillating circuit G1;
The reset signal input end 28 of D4 links to each other with the end 6 of switch D9 after resistance R 5, connects digitally after capacitor C 25;
Resistance R 19 is connected with capacitor C 35, and is connected between phase-locked loop clock filtering input end 38, the phase-locked loop clock filtering input end 37 with oscillatory circuit of capacitor C 35 formations in parallel;
The SPI sheet of D4 select output terminal 40, SPI master go out from go into end 45, SPI output terminal of clock 47 connects with circuit of light sources, Digital I input end 53,54 connects with circuit of light sources;
The Digital I output terminal 41 of D4 is imported 42 ends with the external interrupt of second CPU D8 and is connected after resistance R 6;
The serial data input end 44 of D4 links to each other with the end 6 of first cpu power gauge tap D9 after resistance R 7, and links to each other with the Z axle of optical fibre gyro;
The end 4 of level transferring chip D2 receives the CAN bus signals, through level conversion after hold 3 ends 63 of exporting to first processor D4; End 64 output signals of first processor D4 output signal to the CAN bus by holding 4 after end 3 level conversion of level transferring chip D3, end 63, end 64 have been realized the communication of first processor D4 and CAN bus;
Each terminal of (2) second processor D8 (TMS320LF2403A chip) connects: shown in Fig. 2 B
Power supply input end 6,10,27,35,52,56, the phaselocked loop power supply input end 39 of the second processor D8 connect digital 3.3V power supply; AD converter power supply input end 21 connects simulation 3.3V power supply; AD changes high reference voltage end 20 and links to each other with the voltage output end 4 of Voltage Reference source chip C4 (ADR391); FLASH programming power supply input end 60 connects+the 5V power supply.The ground input end 5,9,26,34,51,55 of D8 connects digitally, and power drives interrupting input end 36 connects digitally, and AD conversion power supply ground input end 22 connects simulation ground, and the low reference voltage end 19 of AD conversion connects simulation ground.
The end 7,8,29,30,31,32,33 of D8 is received 8,7,6,4,2,3,5 ends that JTAG downloads socket X4 respectively, the end 8 that JTAG downloads socket X4 meets digital 3.3V by resistance R 12, end 7 meets digital 3.3V by resistance R 11, and end 1 meets digital 3.3V, and end 9 connects digitally.
The end 2 of D8 connects with the end 4 of switch D 10, and passes through resistance R 15 and digitally connect; End 3 connects with the end 4 of switch D11, and passes through resistance R 16 and digitally connect; End 4 connects with the end 4 of switch D9, and passes through resistance R 14 and digitally connect;
The AD conversion input end 17 of D8 connects with the end 1 of the pre-process circuit A2 of photodetector, and AD conversion input end 18 connects with the end 1 of the pre-process circuit A4 of photodetector;
The startup ROM of D8 enables input end 23 and connects digital 3.3V power supply by resistance R 18;
The input end of clock 24 of D8 is connected with crystal oscillating circuit G2;
The reset signal input end 28 of D8 connects digital 3.3V power supply by resistance R 13, and connects digitally by capacitor C 27;
Resistance R 20 is connected with capacitor C 36, and is connected between phase-locked loop clock filtering input end 38, the phase-locked loop clock filtering input end 37 with oscillatory circuit of capacitor C 37 formations in parallel;
The SPI sheet of D8 select output terminal 40, SPI master go out from go into end 45, SPI output terminal of clock 47 connects with circuit of light sources,
The serial data input end 44 of D8 meets digital 3.3V by resistance R 10, and links to each other with the X-axis of optical fibre gyro;
The digital input end 53,54 of D8 connects with circuit of light sources respectively;
The end 4 of level transferring chip D7 receives the CAN bus signals, through level conversion after hold 3 ends 63 of exporting to the second processor D8; End 64 output signals of the second processor D8 output signal to the CAN bus by holding 4 after end 3 level conversion of level transferring chip D6, end 63, end 64 have been realized the communication of the second processor D8 and CAN bus.
(3) power supply:
In the present invention, power supply circuit is a custom circuit, its provide 3.3V ,+the 5V power supply is to first CPU, second CPU and each external circuit, provide-the 5V power supply is to the PIN signal pre-processing circuit.
(4) connection of each external circuit is:
The end 1 of reference voltage chip C3 (ADR391 chip) is in parallel with end 2, and links to each other with the end 6 of first cpu power gauge tap D9, and end 3 is in parallel after capacitor C 1 connects simulation ground with end 4, and end 5 connects simulation ground; The end 1 of first cpu power gauge tap chip D9 connects digitally, and end 2 meets digital 3.3V with end 3 after in parallel, end 6, end 7, holds 8 parallel connections, shown in Fig. 3 A;
The end 1 of reference voltage chip C4 (ADR391 chip) is in parallel with end 2, and links to each other with digital 3.3V by inductance L 5, and links to each other with simulation ground through capacitor C 29, capacitor C 30, capacitor C 31, and end 3 is in parallel after capacitor C 33 connects simulation ground with end 4;
The end 1 of gyro testing circuit power supply 3.3V gauge tap chip D10 connects digitally, and end 2 meets digital 3.3V with end 3 after in parallel, is connected with optical fibre gyro after end 6, end 7, end 8 are in parallel, shown in Fig. 3 B;
The end 1 of secondary light source power control switch chip D11 connects digitally, and end 2 meets digital 3.3V with end 3 after in parallel, connects with circuit of light sources after end 6, end 7, end 8 are in parallel, shown in Fig. 3 C.
The end 1 of photoelectric switching circuit A1 connects-5V, connects simulation ground by capacitor C 40, capacitor C 41, and end 3, end 5, end 8 connect simulation ground, end 4 connects-5V, end 7 output photoelectric conversion signals, end 10 connects+5V, connects simulation ground (shown in Fig. 4 A) by capacitor C 42, capacitor C 43.
The end 8 of the first photo detector signal pre-process circuit A2 connects+5V, connect simulation ground by capacitor C 47, end 4 connects-5V, connect simulation ground by capacitor C 46, end 3 connects the voltage-regulation end through resistance R 21, and by capacitor C 45 with connecing simulation, end 2 connects after resistance R 24 and capacitor C 48 are in parallel and holds 1, end 2 connects photoelectric conversion signal through resistance R 23, resistance R 22, connect simulation ground through capacitor C 44 between resistance R 23 and the resistance R 22, end 1 connects (shown in Fig. 4 B) through resistance R 25 with the end 17 of first processor D4, the end 17 of the second processor D8.
The end 8 of the second photo detector signal pre-process circuit A4 connects+5V, connect simulation ground by capacitor C 52, end 4 connects-5V, connect simulation ground by capacitor C 51, end 3 connects the voltage-regulation end through resistance R 26, and by capacitor C 50 with connecing simulation, end 2 connects after resistance R 29 and capacitor C 53 are in parallel and holds 1, end 2 connects photoelectric conversion signal through resistance R 28, resistance R 27, connect simulation ground through capacitor C 49 between resistance R 28 and the resistance R 27, end 1 connects (shown in Fig. 4 C) through resistance R 30 with the end 18 of first processor D4, the end 18 of the second processor D8.
In the present invention, the control flow of first processor D4 is:
1. the initialization of first processor (dsp chip): various registers, data storage area, program parameter in the first processor chip are carried out initial configuration;
2. three gyro main light source constant-current drive circuit parts (through end 40,45,47) are configured;
3. initialization finishes, receive the serial data (content includes gyro angular velocity X-axis information 32bits, Y-axis information 32bits, Z axis information 32bits, gyro internal temperature information 12bits) that optical fibre gyro sends over interrupt mode, after receiving, data are kept at gyro angular velocity storage unit, temperature storage unit in the DSP data storage area respectively;
4. start the A/D collector that carries on the first processor chip, A/D converted contents 10bits is kept at PIN value storage unit in the first processor data storage area;
5. gyro temperature control circuit duty 2bits is gathered and is kept in the temperature control state storage unit in the first processor chip data memory block;
6. the amplitude packing data that gyro angular velocity data, temperature data, PIN (photodetector) are located is sent;
Dsp chip that adopts among the present invention and fpga chip difference are: dsp chip is that serial is carried out to program implementation, and fpga chip is an executed in parallel to program implementation.Therefore, dsp chip can not be to fpga chip parallel like that reception and process information and data.
In the present invention, the control flow of the second processor D8 is:
1. the internal initialization of the second processor D8 (dsp chip): various registers, data storage area, program parameter in the dsp chip are carried out initial configuration;
2.DSP chip initiation finishes, receive the serial data (content includes gyro angular velocity X-axis information 32bits, Y-axis information 32bits, Z axis information 32bits, gyro internal temperature information 12bits) that optical fibre gyro sends over interrupt mode, after receiving, data are kept at gyro angular velocity storage unit, temperature storage unit in the DSP data storage area respectively;
3. the A/D collector that carries on the startup dsp chip is kept at PIN value storage unit in the dsp chip data storage area to A/D converted contents 10bits; (the PIN signal can not directly be connected on the A/D, needs through pre-process circuit)
4. gyro temperature control circuit duty 2bits is gathered and is kept in the temperature control state storage unit in the dsp chip data storage area; Begin information is analyzed and handled, its serial Interrupt Process content is following:
5. the amplitude packing data at gyro angular velocity data, temperature data, PIN place is sent (its condition that need satisfy of this step is the power supply that first processor D4 could move and disconnect first processor D4 when not working);
6. the gyro data of the current three gyro information that receives and front 5 times (determine times of collection by system, generally be made as 5～15 times) is compared, if the data no change is then restarted gyro testing circuit 3.3V power supply;
7. the PIN data and the PIN threshold value in the DSP program that A/D are collected compare (PIN threshold value lower limit FH, upper limit 199H), if data not in normal range, are then revised light source continuous current size, by changing source device output optical power, adjust the amplitude of PIN output signal;
8. the temperature threshold in gyro internal temperature information and the DSP program is compared (temperature threshold lower limit 000H, upper limit 5A0H), if the gyro temperature over-range, then turn-off gyro 3.3V and supply power to Millisecond and restart power supply after the time;
9. if gyro light source temperature control circuit working state abnormal (when two signals of Fault0_1 and Fault1_1 are not high level) is then restarted circuit of light sources power supply 3.3V; If turn-offed the power supply of first processor, then the dsp chip executive routine goes to step 2;
Second processor is being carried out the external interrupt processing: (step below just can entering into when having only when first processor D4 operation irregularity)
10. if first processor D4 operation irregularity then enters in the external interrupt program of the second processor D8, turn-off the 3.3V power supply of first processor D4, restart then, in the return message acquisition step 2; If first processor D4 operation irregularity repeats, then turn-off the 3.3V power supply of first processor D4 fully, enter into step 2;
In the present invention, the first processor D4 external interrupt that happens suddenly adopts the light source constant-current drive circuit is reinitialized configuration, and the system program of the second processor D8 goes to information acquisition step 2.
In the present invention, defined the fault of three axis optical fibre gyro system, as following table:
| Fault | Treating method |
| Gyro temperature anomaly (the gyro temperature surpasses threshold value) | Turn-off gyro and open the gyro power supply after power supply a period of time again |
| PIN place abnormal signal (not in range of normal value) | Light source power is revised |
| Gyro temperature control circuit operation irregularity | Restart the light source temperature control circuit |
| The gyro output data is constant | Restart the gyro resolving circuit and refer to conventional testing circuit |
| Communication failure: refer to supervising device faults itself first processor operation irregularity | Cut off first processor (host CPU) power supply, start second processor (aiding CPU) communication function |
Claims (1)
1. supervising device that is applicable to interference optical fiber top, adopt two processor chips that the duty of three axis optical fibre gyro is monitored in real time, it is characterized in that: this supervising device is made up of the level shifting circuit of first processor (D4), second processor (D8), first processor, level shifting circuit, first processor power control switch (D9), gyro testing circuit power switch (D10) and the secondary light source power control switch (D11) of second processor;
First processor (D4) is chosen the TMS320LF240XA family chip;
Second processor (D8) is chosen the TMS320LF240XA family chip;
Incoming level conversion chip in the level shifting circuit of the level shifting circuit of first processor (D4) and second processor (D8) is chosen the MAX3371 chip, the transmission level conversion chip is chosen the MAX3371 chip;
First processor power control switch (D9) is chosen the TPS2024 chip;
Gyro testing circuit power switch (D10) is chosen the TPS2024 chip;
Secondary light source power control switch (D11) is chosen the TPS2024 chip;
PIN_2 signal, light source temperature control Fault0_1 signal, light source temperature control Fault1_1 signal, light source temperature control Fault0_2 signal, light source temperature control Fault1_2 signal and the power supply 3V3_DP1 signal of the PIN_1 signal of the serial data of described first processor (D4) first aspect reception interference optical fiber top output, pre-process circuit (A2) output of first photodetector, pre-process circuit (A4) output of second photodetector; Second aspect is exported the level shifting circuit that first data message is given described first processor;
Described second processor (D8) out-put supply control signal is respectively given gyro testing circuit power control switch (D10) and secondary light source power control switch (D11);
The serial data of described interference optical fiber top output is meant X-axis information 32bits, Y-axis information 32bits, Z axis information 32bits and the gyro internal temperature information 12bits of gyro angular velocity;
Judge the fault of interference optical fiber top in second processor (D8) by the fault judgement threshold value, this fault judgement threshold value is meant PIN threshold value lower limit FH, upper limit 199H and temperature threshold lower limit OOOH, upper limit 5A0H;
The connection of each terminal is in the hardware circuit of this supervising device:
The power input 6,10,27,35,52,56 of first processor (D4), AD conversion power supply input end 21 link to each other with the output terminal 6 of phaselocked loop power supply input end 39 with first processor power control switch (D9), AD changes high reference voltage end 20 and links to each other with the voltage output end 4 of Voltage Reference source chip C3, and FLASH programming power supply input end 60 connects+the 5V power supply;
The ground input end 5,9,26,51 and 55 of first processor (D4) connects digitally, and power drives interrupting input end 36 connects digitally, and AD converter power supply ground input end 22 connects simulation ground, and the low reference voltage input terminal 19 of AD converter connects simulation ground;
The end 7,8,29,30,31,32 and 33 of first processor (D4) connects the end 8,7,6,4,2,3 and 5 that a JTAG downloads socket (X3) respectively, the end 8 of the one JTAG download socket (X3) connects the back and connects with the end 6 of first processor power control switch (D9) with resistance R 4, end 7 connects the back with resistance R 3 and connects with the end 6 of first processor power control switch (D9), end 1 connects with the end 6 of first processor power control switch (D9), holds 9 to connect digitally;
The AD conversion input end 17 of first processor (D4) connects with the end 1 of the pre-process circuit (A2) of first photodetector by resistance R 25, the end 8 of the pre-process circuit of first photodetector (A2) connects+connect simulation ground by capacitor C 47 behind the 5V power supply, end 4 connects-connect simulation ground by capacitor C 46 behind the 5V power supply, end 3 connects simulation ground by capacitor C 45, and connect gyro by resistance R 21, be connected in after resistance R 24 and capacitor C 48 are in parallel first photodetector pre-process circuit (A2) end 1 and hold between 2, end 2 is simulated ground by connecing after resistance R 23 and the capacitor C 44, and connects with the end 7 of photoelectric commutator by resistance R 22; AD conversion input end 18 connects with the end 1 of the pre-process circuit (A4) of second photodetector by resistance R 30, the end 8 of the pre-process circuit of second photodetector (A4) connects+connect simulation ground by capacitor C 52 behind the 5V power supply, end 4 connects-connect simulation ground by capacitor C 51 behind the 5V power supply, end 3 connects simulation ground by capacitor C 50, and connect gyro by resistance R 26, be connected in after resistance R 29 and capacitor C 53 are in parallel second photodetector pre-process circuit (A4) end 1 and hold between 2, end 2 is by resistance R 28, capacitor C 49 connects simulation ground, and connects with the end 7 of photoelectric commutator by resistance R 27;
The startup ROM of first processor (D4) enables input end 23 and links to each other with the end 6 of first processor power control switch (D9) after resistance R 17;
The input end of clock 24 of first processor (D4) is connected with crystal oscillating circuit G1;
The reset signal input end 28 of first processor (D4) links to each other with the end 6 of first processor power control switch (D9) after resistance R 5, connects digitally after capacitor C 25;
Resistance R 19 is connected with capacitor C 35, and is connected between the phase-locked loop clock filtering input end 38 and phase-locked loop clock filtering input end 37 of first processor (D4) with oscillatory circuit of capacitor C 35 formations in parallel;
The SPI sheet of first processor (D4) selects output terminal 40, SPI master to go out from going into end 45 and SPI output terminal of clock 47 to connect with circuit of light sources, and Digital I input end 53 and 54 connects with circuit of light sources;
The Digital I output terminal 41 of first processor (D4) is imported 42 ends with the external interrupt of second processor (D8) and is connected after resistance R 6;
The serial data input end 44 of first processor (D4) links to each other with the end 6 of first processor power control switch (D9) after resistance R 7, and links to each other with the Z axle of optical fibre gyro;
The end 4 of level transferring chip D2 receives the CAN bus signals, through level conversion after hold 3 ends 63 of exporting to first processor (D4); End 64 output signals of first processor (D4) are after end 3 level conversion of level transferring chip D3, end 4 by level transferring chip D3 outputs signal to the CAN bus, and the end 63 of first processor (D4) and end 64 have been realized the communication of first processor (D4) with the CAN bus;
The power supply input end 6,10,27,35,52,56 and the phaselocked loop power supply input end 39 of second processor (D8) connect digital 3.3V power supply; AD converter power supply input end 21 connects simulation 3.3V power supply; AD changes high reference voltage end 20 and links to each other with the voltage output end 4 of Voltage Reference source chip C4; FLASH programming power supply input end 60 connects+the 5V power supply.The ground input end 5,9,26,34,51,55 of second processor (D8) connects digitally, and power drives interrupting input end 36 connects digitally, and AD conversion power supply ground input end 22 connects simulation ground, and the low reference voltage end 19 of AD conversion connects simulation ground;
The end 7,8,29,30,31,32 and 33 of second processor (D8) is received 8,7,6,4,2,3 and 5 ends that the 2nd JTAG downloads socket (X4) respectively, the end 8 that the 2nd JTAG downloads socket (X4) meets digital 3.3V by resistance R 12, end 7 meets digital 3.3V by resistance R 11, end 1 meets digital 3.3V, and end 9 connects digitally;
The end 2 of second processor (D8) connects with the end 4 of gyro testing circuit power switch (D10), and passes through resistance R 15 and digitally connect; End 3 connects with the end 4 of secondary light source power control switch (D11), and passes through resistance R 16 and digitally connect; End 4 connects with the end 4 of first processor power control switch (D9), and passes through resistance R 14 and digitally connect;
The AD conversion input end 17 of second processor (D8) connects with the end 1 of the pre-process circuit (A2) of first photodetector, and AD conversion input end 18 connects with the end 1 of the pre-process circuit (A4) of second photodetector;
The startup ROM of second processor (D8) enables input end 23 and connects digital 3.3V power supply by resistance R 18;
The input end of clock 24 of second processor (D8) is connected with crystal oscillating circuit G2;
The reset signal input end 28 of second processor (D8) connects digital 3.3V power supply by resistance R 13, and connects digitally by capacitor C 27;
Resistance R 20 is connected with capacitor C 36, and is connected between phase-locked loop clock filtering input end 38, the phase-locked loop clock filtering input end 37 with oscillatory circuit of capacitor C 37 formations in parallel;
The SPI sheet of second processor (D8) selects output terminal 40, SPI master to go out from going into end 45 and SPI output terminal of clock 47 to connect with circuit of light sources,
The serial data input end 44 of second processor (D8) meets digital 3.3V by resistance R 10, and links to each other with the X-axis of optical fibre gyro;
The digital input end 53,54 of second processor (D8) connects with circuit of light sources respectively;
The end 4 of level transferring chip D7 receives the CAN bus signals, through level conversion after hold 3 ends 63 of exporting to second processor (D8); End 64 output signals of second processor (D8) output signal to the CAN bus by holding 4 after end 3 level conversion of level transferring chip D6, end 63 and end 64 have been realized the communication of second processor (D8) with the CAN bus.
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| CN2007100629174A CN101033968B (en) | 2007-01-22 | 2007-01-22 | Monitoring apparatus suitable for interferometric fiber optic gyroscope |
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| CN102435208B (en) * | 2011-09-01 | 2013-07-10 | 中国航空工业第六一八研究所 | Flexible gyroscope unlocking detection method for platform type inertial navigation system |
| CN102323008B (en) * | 2011-09-01 | 2013-10-23 | 中国航空工业第六一八研究所 | Balance testing method for inertial platform of platform type inertial navigation system |
| CN102519483A (en) * | 2011-11-25 | 2012-06-27 | 西安航天精密机电研究所 | Self-detecting method for working state of gyro |
| CN102645230B (en) * | 2012-04-11 | 2015-06-24 | 中航捷锐（北京）光电技术有限公司 | Fault detection method and device of optical fiber gyroscope |
| CN103148846B (en) * | 2013-02-25 | 2015-03-18 | 哈尔滨工业大学 | Micromechanical gyroscope driving device based on arbitrary waveform of DDS (Direct Digital Frequency Synthesizer) |
| CN103808321B (en) * | 2013-12-27 | 2016-08-17 | 北京航天时代光电科技有限公司 | A kind of three-axis integrative inertial measurement unit of optical fiber gyroscope based on light source cold standby and compensation and installation method |
| CN105973267A (en) * | 2015-12-31 | 2016-09-28 | 西安航天精密机电研究所 | Gyro working state self-detection system and method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5650849A (en) * | 1993-10-16 | 1997-07-22 | British Aerospace Public Limited Company | Optical rate sensor having modulated clockwise and counterclockwise beams |
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| US5650849A (en) * | 1993-10-16 | 1997-07-22 | British Aerospace Public Limited Company | Optical rate sensor having modulated clockwise and counterclockwise beams |
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