CN101031999A - Reduction of source and drain parasitic capacitance in cmos devices - Google Patents

Reduction of source and drain parasitic capacitance in cmos devices Download PDF

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Publication number
CN101031999A
CN101031999A CNA200580032866XA CN200580032866A CN101031999A CN 101031999 A CN101031999 A CN 101031999A CN A200580032866X A CNA200580032866X A CN A200580032866XA CN 200580032866 A CN200580032866 A CN 200580032866A CN 101031999 A CN101031999 A CN 101031999A
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dopant
knot
substrate
plasma
introduce
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尤里·叶罗欣
郑宇桥
杰伊·T·舒尤尔
史蒂文·R·沃尔特
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Varian Semiconductor Equipment Associates Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

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  • Power Engineering (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

A method for fabricating a semiconductor-based device includes providing a doped semiconductor substrate, introducing a second dopant into the substrate to define a pn junction, and introducing a neutralizing species into the substrate in the neighborhood of the pn junction to reduce a capacitance associated with the pn junction. A semiconductor-based device includes a semiconductor substrate having first and second dopants, and a neutralizing species. The first and second dopants define a pn junction, and the neutralizing species neutralizes a portion of the first dopant in the neighborhood of the pn junction to decrease a capacitance associated with the pn junction.

Description

Reduce source electrode and drain parasitic capacitance in the cmos device
Technical field
The present invention relates to the device of based semiconductor, specifically relate to provide the device and the manufacture method of the based semiconductor that reduces parasitic capacitance.
Background technology
Integrated circuit generally comprises the intrinsic parasitic antenna harmful to circuit performance.For example, the transistorized pn knot of bipolar transistor and metal-oxide semiconductor (MOS) (MOS) has electric capacity under reverse bias voltage condition, and therefore can be used as capacitor parasitics.As another example, interconnection line can be used for electrode for capacitors, produces capacitor parasitics equally.It is because they can cause undesirable effect that these capacity cells are called as " parasitism ".Parasitic capacitive elements can for example be introduced circuit delay.For example, in logical circuit, the parasitic input capacitance of drived unit can be used as the load capacitance of driver element, and therefore can influence the time of delay of driver element.
In complementary MOS (CMOS) circuit, the source electrode of MOS transistor and drain electrode show and the electric capacity that is limited between source electrode and the substrate and the knot of the reverse biased pn between drain electrode and the substrate is relevant.Usually, these pn knot is added reverse biased and is separated with the underclad portion with source electrode and drain electrode and substrate.The capacitive part of reverse biased junction is determined by the depletion widths of knot.
In order to form N type MOS transistor, for example, be doped with p type substrate such as the p type dopant of boron (B) and can in institute's favored area, inject n type dopant, to form dense relatively impure source and drain electrode n type district such as arsenic (As) or phosphorus (P).Usually, in source electrode and drain region, the n type concentration of dopant of injection is mixed greatly than the p type of substrate, thus source electrode and drain region is transformed into the n type state that needs.Can be therefore as parasitic capacitive elements with n type source electrode and drain region with the pn knot that underlying substrate p type partly separates.Source electrode and the drain electrode can produce integrated circuit total parasitic capacitance 30% or more.Reduce this electric capacity the speed of service of increase and the power consumption of reduction can be provided.
In order to reduce source electrode and drain parasitic capacitance, can (SOI) make integrated circuit on the wafer at for example silicon-on-insulator (silicon-on-insulator).Unfortunately, the SOI wafer is than conventional silicon wafer costliness.And, use the SOI wafer may need to revise circuit design, can cause the distinctive design problem of SOI, such as buoyancy aid (floating-body) and hysteresis effect, and can exist defect concentration in the relevant SOI wafer than the big problem in the standard silicon wafer, this can reduce device fabrication yield and increase device cost thus.
Summary of the invention
Can be thereby the present invention partly is derived from by tying the understanding that relevant depletion widths reduces the parasitic capacitance relevant with the pn knot with the part of dopant to increase in the part with pn.Can be for example by residing in some dopants in the displacement lattice point with deactivation matter and/or the passivation of displacement material and/or displace some electroactive adulterants from the displacement lattice point, thereby in and the dopant part.For example, but a part of boron near the substrate the hydrogen passivation pn knot, with the depletion widths of the knot of the pn between expansion n type source electrode or drain region and the p of the lower floor type substrate zone.And, can for example inject and inject hydrogen and dopant easily jointly by plasma.
Can by comprise simultaneously injected material and in and the injection material of material form plasma.Scheme as an alternative, can by comprise such as the injection material of the injected material of dopant species and from comprise and the neutralization materials of material form plasma.Therefore, though do not require, dopant species and in and the injection of material can take place simultaneously.
In some embodiments of the present invention, supply with dopant gas and carrier gas to plasma.Can select carrier gas with provide can be in addition in and the material of activated dopants atom.Can by for example with in and material form Electronic Keying and replace the dopant atom that neutralizes on the interstitial lattice node with the passivation dopant atom and/or by being neutralized material.Dopant and in and material can be injected successively, perhaps can be injected simultaneously from identical plasma.Therefore, the present invention can for example be applied to the system based on the plasma injection.Can utilize for example pulse or continuous plasma from the plasma injected system that feature of the present invention benefits.
Therefore, in first aspect, feature of the present invention is a kind of method of making the device of based semiconductor.This method comprises: the substrate that comprises the semiconductor and first dopant is provided; Second dopant is incorporated in the substrate; With will in and material be incorporated in the substrate.First and second dopants limit the pn knot in the substrate.In reduce and the relevant electric capacity of pn knot by the active concentration that reduces near first dopant the pn knot with material.
The dosage that can select corrective matter is to provide the neutralization that is less than all first dopants.For example, can select dosage with provide enough in and material, reduce about 20～90% with active concentration with first dopant.Can be by for example increasing the knot depletion widths to reduce the electric capacity of pn knot.For example can in growth course, first dopant be introduced semiconductor by diffusion and/or by injecting.
In second aspect, feature of the present invention is a kind of device of based semiconductor.This device comprises substrate.This substrate comprises semiconductor, limit the pn knot first and second dopants and in and material.In with the part of the local neutralization of material first dopant species to reduce and the relevant electric capacity of pn knot.The pn knot can be relevant with transistor.
Description of drawings
Do not plan to draw in proportion accompanying drawing.In the accompanying drawings, each the identical or roughly the same element shown in each figure is represented by same or analogous Reference numeral.For clear, not that each element all can be marked in each figure.In the accompanying drawings:
Fig. 1 is the embodiment flow chart according to the method for the device of principle of the invention manufacturing based semiconductor;
Fig. 2 a is the embodiment sectional drawing of the pn knot of based semiconductor in accordance with the principles of the present invention;
Fig. 2 b is the embodiment sectional drawing of the device of based semiconductor in accordance with the principles of the present invention.
Embodiment
The invention is not restricted to set forth in the following description or the structure of element illustrated in the accompanying drawings and the detailed applications of configuration.The present invention can have other embodiment and can be put into practice in every way or implement.And word used herein and term are used for explanation and should be considered as restriction.Here use " comprising ", " comprising " or " having ", " containing " and their variation mean and comprise project and equivalent and the additional project of listing thereafter.
Word used herein " plasma " is the plasma of broad sense, be meant can similar gas phase, can comprise in electronics, atom or molecular ion, atom or molecule free radical material (species) (that is the neutral substance of activation) and neutral atom and the molecule arbitrarily or all.Plasma generally has and is roughly zero net charge.Plasma can be planted material by one or more by for example ionization and/or decomposition incident and be formed, and this ionization and/or decomposition incident can encourage with for example inductance and/or capacitive coupling by power supply again.
Phrase used herein " plasma injection " be meant the quality that is used to not have conventional beam implanter (beam implanter) from the injection of plasma select (mass selection) feature injection technique.The plasma implanter generally comprises substrate and plasma in same chamber.Plasma can or immerse substrate near substrate thus.Usually, the various material types from plasma will inject substrate.When being used for herein, word " material " can refer to atom, molecule or their set, and they can be neutrality, ionization or excitation state.
Fig. 1 is the embodiment flow chart of method 100 of making the device of based semiconductor in accordance with the principles of the present invention.Substrate is provided, and this substrate comprises such as the semiconductor of silicon and first dopant, so that p type or n type substrate to be provided.Method 100 comprises introduces in the substrate (step 110) limiting the pn knot jointly with first dopant with second dopant, and will in and material introduce in the substrate (step 120) and tie relevant electric capacity to reduce with pn.This device can be the element of for example circuit, for example diode or transistor.Transistor for example can be MOS transistor or bipolar transistor.Scheme as an alternative, device can be the part of circuit or complete circuit.
The introducing (step 110) of second dopant causes the part of substrate to be transformed into the n type or to be transformed into the p type from the n type from the p type, and this type with first and second dopants is relevant.The pn knot appears between the substrate of zone that changes and vicinity thus.The pn knot can be relevant with for example transistorized source electrode and/or drain electrode, for example MOS transistor.
Substrate can be for example p type or n type silicon wafer.As the technical staff in the technical field of manufacturing semiconductors is known, can adds respectively such as the dopant of B, P or As simultaneously by for example growing silicon crystal and make this wafer.Therefore, first dopant can be B that for example is used for p type wafer or P or the As that is used for n type wafer.Then can be by for example respectively n type dopant or p type dopant being introduced (step 110) thus in wafer, form source electrode and drain region in the zone of wishing.For example, can introduce (step 110) second dopant by such as the injection of plasma injection or by diffusion.
In the following description, mention specific dopant and specific in and the exemplary intention of the present invention of material be not to be limited to these materials.Should be appreciated that principle of the present invention can be applied on the injection material and injected material of wide region.Therefore, for simplicity, some described embodiment of the present invention are mentioned and are introduced As to produce the boron doped substrate of transistorized source electrode and drain region.But principle of the present invention can be applied to other material and device architecture to reduce junction capacitance.
Thereby can will introduce substrate (step 110) as the arsenic of second dopant by for example diffusion into the surface or injection As through substrate.As the technical staff in the technical field of manufacturing semiconductors is known, can begin to make MOS transistor by the silicon substrate that use has an equally distributed basically B dopant.Then can be by forming the source electrode and the drain electrode of MOS transistor in the zone of the As of relative higher concentration being introduced substrate.Because the As in source electrode and the drain region is than the concentration height of the B in these zones, so source electrode and drain region are transformed into n section bar material from the p type.
In addition, can in same (p type) substrate, form p type MOS transistor by the trap that for example at first in p type substrate, forms n type dopant.Can in trap, form source electrode and drain region by introducing p type dopant then, in n type trap, to limit p type source electrode and drain region.Therefore, principle of the present invention can for example be applied to improving transistor that forms and the transistor that needs the less doping step in manufacture process in trap.
In and material can be introduced into to reduce the electric capacity (step 120) of pn knot by the depletion widths that reduces pn knot.Technical staff in the technical field of semiconductor device is appreciated that the electric capacity of pn knot can part be determined by the depletion widths of the knot of reverse biased.Depletion widths can part be determined by the concentration of the dopant that limits the pn knot again.
In and material can be deactivation matter and/or the displacement material.Can select corrective matter to reduce near the concentration of the activated dopants of pn knot, increase depletion widths thus.For example, hydrogen (H) thus can be used as deactivation matter makes their deactivations (word used herein " hydrogen " comprises the isotope of hydrogen, such as deuterium) to combine with the dopant atom electronics.Can select near the pn knot in and the concentration of material so that the required part deactivation in the dopant.
Usually, to the concentration of lower dopant, the depletion widths of particular bias conditions is bigger.Technical staff in the technical field of semiconductor device is appreciated that the net concentration of activated dopants can have active influence to depletion widths.Particularly, under lower concentration level, form bigger depletion widths and fall to hold specific bias voltage at pn knot two ends.
In having the typical MOS transistor of heavily doped source electrode or drain electrode, most of depletion widths occurs in a side of the less doping of pn knot.In this case, the concentration of dopant of the substrate side of pn knot can be determined the scope of depletion widths to a great extent.By the passivation a part of B in the substrate for example, can increase depletion widths and reduce electric capacity thus.
Therefore, in an example according to principle of the present invention, method 100 is applied in the boron doped silicon wafer of p type.The As of the concentration by will be higher relatively inject the zone of wishing, then by annealing so that at least some deactivations of dopant form source electrode and drain region.Hydrogen is injected into a part of boron in the substrate of the contiguous pn knot that neutralizes, and reduces the activated dopants net concentration near the p type substrate part in source electrode and drain region thus.Depletion widths under the given voltage conditions can be thus than in that not introduce the depletion widths that obtains under the situation of passivation H for example big, and reduce electric capacity thus.As following illustrating in greater detail, H can be before injecting the process of As, among and/or be injected into afterwards.
More generally, according to principle of the present invention, substrate can comprise the silicon layer of doping.For example, as the technical staff in the technical field of semiconductor device is known, be made for n type or p type by the dopant that adds such as phosphorus or boron, substrate can n type or p type silicon wafer.As the technical staff in the technical field of semiconductor device was known, substrate can for example be a silicon chip, the insulating barrier that this silicon wafer also can for example be imbedded with the form combination of silicon-on-insulator (SOI) wafer.In and material can maybe can help other material of the passivation and/or the displacement of dopant atom for H.
Usually, in preferred and near part first dopant the pn knot rather than the substrate of first dopant with low concentration is provided simply.Under latter event, the contiguous for example substrate of the channel region of MOS transistor also will have first dopant of low concentration.This transistor can produce for example break-through (punch-through) and lose efficacy.Therefore, according to principle of the present invention, the active concentration of first dopant is can be near pn knot lower and keep higher concentration level near the other parts at device.
Can or inject and introduce second dopant (step 110) by for example diffusion.Can inject or plasma injection realization injection by for example beam (beam).Method 100 also can comprise by neutralization materials and dopant material and forms plasma (step 111).Plasma injects and can be used to for example inject simultaneously dopant species and and material.Can be for example by the use mask or near for example optionally second dopant introducing pn being tied by the autoregistration process.
Second dopant can comprise one or more kind dopant species, and can provide (step 112) by one or more kind dopant materials that comprise dopant species.Some suitable dopant materials comprise for example AsH 3, PH 3, BF 3, AsF 5, PF 3, B 5H 9And B 2H 6In and material can comprise that one or more of being planted neutralization materials and provided by one or more plant materials.The carrier gas that neutralization materials can be used as in the injected system for example is provided (step 122).More generally, can utilize carrier gas, no matter it whether provide in and material.Some carrier gas comprise He, Ne, Ar, Kr and Xe.
Scheme as an alternative, in some embodiments, material provide simultaneously second dopant species and in and material (step 132).For example, can provide by dopant material with material in.For example, if wish H be in and material, some possible dopant materials comprise AsH so 3, PH 3, B 5H 9, B 2H 6With other contain the H material.Therefore, can form plasma from single material, with provide simultaneously dopant and in and material.And, mix and in and material can for example inject and be injected jointly by plasma.
When use injecting, can by the injected system of any type introduce second dopant and in and material (step 110,120).Suitable system comprises the system based on DC, RF and microwave power (power) supply.Can power (power) be transferred to injected system by for example capacitive coupling, inductance coupling high or waveguide.Can use a plurality of implantation steps to introduce second dopant (step 110) and/or deactivation matter (step 120).
Ion implantor for example can comprise gas or solid material are transformed into the ion source that is limited the ion beam of (well-defined) well.Ion implantor can carry out quality analysis to ion beam, with the material of selecting to wish, and quickens and guide the target area of the material beam of hope to substrate.Can for example move the beam that on the target area, distributes by beam scanning and/or target.The beam implanter can inject energy for dopant species, dopant ion thus and dopant location provides accurate control.
As the replacement scheme that beam injects, for example can use plasma to inject, to develop its lower cost potential under lower energy and higher production capacity.Suitable plasma injection technique comprises that for example plasma immersion ion injects (PIII).Plasma injects and can utilize the continuous or intermittent plasmas that for example can be used for continuously or intermittently inject.In the plasma doping system of a kind of suitable type of utilizing intermittent plasmas, semiconductor wafer is placed on the conductive platen (platen) that is arranged in the plasma doping chamber and is used as negative electrode.The ionizable gas that comprises material requested is introduced into indoor, and, between platen and anode, apply potential pulse, near wafer, to form glow discharge plasma with plasma cover layer (sheath).The potential pulse that applies for example can cause the ion in the plasma to pass the plasma cover layer and be injected in the wafer.The degree of depth of injecting can be relevant with the voltage that applies between wafer and anode.
The plasma injection technique can be used for developing the ability of the material beyond their the injection dopant species.For example, the neutral substance of various neutral substances, activation and various ion can be injected in the substrate.
Can select position and the concentration level of injection parameter with the material of control injection.For example, can be by selecting proper dosage and injecting energy and partly realize expectation influence to the active dopant concentration level of pn knot.For example, can select to inject energy injection is positioned near the substrate that underlies of pn knot.Can select dosage so that a certain amount of deactivation matter to be provided, this deactivation matter will neutralize near the described knot the substrate that underlies a big chunk but be not the first whole dopants.
For example, pn junction depth (below the substrate) can for example be about 10～100nm, and part is derived from second dopant that injects the about 5～70nm of the degree of depth.In and material can be injected into for example degree of depth of about 20～200nm, and some embodiments have the preferred depth of about 2X～5X of the desired value of pn junction depth.The injection energy of hydrogen can be for example about 500eV～about 10keV.For about 2 * 10 18Cm -3First concentration of dopant, the dosage of hydrogen can be for example about 10 14～about 5 * 10 15Cm -2In some embodiments, such as in the hydrogen and the concentration of the dosage of material and first dopant proportional.
In introducing and behind the material (step 120), substrate may need annealing, with in for example and material allows when being introduced into by injection and material to dopant atom move and with its reaction.For example, annealing can allow the H atom to combine to the B atom diffusion and with it with its passivation.Therefore, deactivation matter can make the free key of a part of dopant species atom saturated to prevent that saturated atom from contributing free carrier to semi-conducting material.On the contrary, the displacement material can by for example in ion implantation process with dopant atom collision or for example by in back implantation annealing process from displacement position " release " thus dopant atom replace lattice point from activity and displace dopant atom.
Second dopant and/or in and material can inject by plasma and be introduced into (step 110,120).When Production Example such as shallow device knot, it can be useful using the plasma injection technique.Compare with typical ion beam implanter, plasma injects can provide improved dose rates (dose rate) under lower energy.For example, under being lower than the energy of 10keV (in for example inferior 90nm device shallow junction form institute is conventional to be required), the introducing (step 110) that the plasma injection can be second dopant provides higher production capacity.
As mentioned above, plasma inject can provide simultaneously dopant and and the injection of material, and dopant and in and material can provide by single injection material.For example, plasma can be by AsH 3Form.Except unleavened AsH 3Beyond other molecule and atom, plasma can comprise for example AsH 3, AsH 2, As and H free radical, AsH 2, AsH, As and H cation and electronics.As and H can be injected jointly by plasma.And, the As of common injection and at least some of H, for example AsH can be provided in the one matter that provides by plasma 2Therefore, in injected material, for example, the molecule of ionization can comprise simultaneously second dopant and in and material.Scheme as an alternative is by replacing part first dopant species in the substrate simultaneously and second dopant is provided in substrate, during injected material or dopant species also can be used as and material.
If AsH 3The injection material that is used as the common injection of As and H, so in some embodiments of the present invention, select injection parameter with provide scope be from As dosage about 5% to the H dosage that approximates As dosage.As dosage can be selected as about 10 14～about 10 16Cm -2
Under the situation of MOS transistor, at the great majority relevant with the drain region or all after the treatment steps in the introducing and material (step 120) with limiting transistor source.That is, can preferably after being neutralized, the expectation part of first dopant make second dopant and corrective quality guarantee hold undisturbed as far as possible.Scheme as an alternative, such as in H additional and material can before or after second dopant injects, be injected into.Can utilize extraction voltage (extraction voltage) to inject additional and material, select described extraction voltage for example to make it about 0.2～2 times for the level of the extraction voltage that is used to inject second dopant.
The dosage that can select corrective matter is with first dopant in the substrate that pn forges face of residing in of neutralization for example about 20～90%.As mentioned above, effectively dosage will provide enough in and material with enough dopants that neutralizes, thereby junction capacitance is had remarkable influence, be unlikely to big simultaneously to the problem that produces such as break-through and leakage.Select suitable dosage, electric capacity can be reduced for example about 50% or up to about 70% or bigger.
Fig. 2 a is can be by for example embodiment sectional drawing of the device 200 of the part based semiconductor of method 100 manufacturings.Device 200 comprises substrate 210.Substrate 210 comprises semiconductor, limit first and second dopants of pn knot J in the semiconductor and pn final result portion in and material, described in and in the material and near part first dopant of pn knot to reduce tying relevant electric capacity with pn.When the pn knot applies reverse biased, the pn knot is relevant with depletion widths W, shown in dotted line.
Fig. 2 b is can be by for example embodiment sectional drawing of the transistor 200a of method 100 manufacturings.Transistor 200a comprises: the source area 230 and drain region 240, the source contact 231 that contacts with source area 230, the drain contact 241 that contacts with drain region 240, the gate contact 220 of adjacent substrate 210a and the gate dielectric 225 between gate contact 220 and the substrate 210a that have the silicon-based substrate 210a of first dopant, limited by second dopant.Substrate 210a also be included near source electrode and the drain region 230,240 in and material, in this and the depletion widths tied of material increase and source electrode and drain region 230,240 relevant pn.During field of manufacturing semiconductor devices technical staff is appreciated that and material in source electrode and 230,240 parts, drain region, and can with source electrode and drain region 230,240 autoregistrations.
Source electrode and drain contact 231,241 can comprise silicide.Gate contact 220 can comprise the conductive polycrystalline silicon bottom and the suicide upper portion of for example mixing.Scheme as an alternative, gate contact 220 can be formed by another electric conducting material, for example heavily doped semiconductor; The metal of titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta) or indium (Ir) for example; Or provide the metallic compound of suitable work content, for example titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), tantalum nitride (TaN), tantalum silicide (TaSi), nickle silicide (NiSi) or indium oxide (IrO 2).
But the part epitaxial growth of substrate, and can be added in the epitaxial loayer of growth such as first dopant species of B.Can be for example by precipitating metal level and making metal level and substrate 210a reaction formation source electrode and drain contact 231,241.
Can for example thermal oxidation or deposition technique form dielectric layer 225 by various conventional methods of the prior art.Gate-dielectric 225 can be the thick silicon dioxide layer of for example 1.0～10.0nm.Perhaps, dielectric 225 can be for example silicon oxynitride, silicon nitride, a plurality of silicon nitride and silicon oxide layer or high-k dielectric.When the effective gate oxide thicknesses that for example needs to approach for example is equivalent to 2.0nm or thinner SiO 2During layer thickness, can use substituting dielectric material.
According to principle of the present invention, transistor 200a can be used as NMOS or PMOS element.Transistor 200a can comprise source electrode, drain electrode and the channel layer region of for example different doping types and level.
Though several aspects of at least one embodiment of the present invention have been described thus, have should be understood that those skilled in the art are easy to expect various changes, modification and improvement.This change, modification and improvement will constitute a part of this disclosure, and will be contained in the spirit and scope of the present invention.Therefore, above explanation and accompanying drawing only are as an example.

Claims (26)

1. method of making the device of based semiconductor comprises:
The substrate that comprises the semiconductor and first dopant is provided;
Second dopant is incorporated in the substrate, and described first and second dopants limit the pn knot in described substrate; With
Will in and material be incorporated in the described substrate, to reduce and the relevant electric capacity of pn knot by the electroactive mark that reduces near first dopant the described pn knot.
2. according to the process of claim 1 wherein, described in and material comprise near the deactivation matter of part first dopant the described pn knot of passivation.
3. according to the process of claim 1 wherein, described in and material comprise near the displacement material of displacement lattice point replacing section first dopant the described pn knot.
4. according to the process of claim 1 wherein, described pn knot is relevant with the source electrode of MOS transistor, and described first and second dopants also limit the two pn knot relevant with the drain electrode of MOS transistor.
5. according to the process of claim 1 wherein, introduce described in and material comprise by tying and increase relative depletion widths when being in reverse bias condition and reduce electric capacity as pn.
6. according to the process of claim 1 wherein, introduce described second dopant and introduce described in and material take place simultaneously basically.
7. according to the method for claim 6, also comprise by forming plasma with material and by at least a compound that comprises described second dopant in described, wherein introduce described second dopant and comprise that carrying out plasma from described plasma injects described second dopant and introduce described and material and comprise that carrying out plasma from described plasma injects described and material.
8. according to the method for claim 7, wherein, described at least a compound comprises and is selected from AsH 3, PH 3And B 2H 6In at least a compound.
9. according to the process of claim 1 wherein, described deactivation matter comprises hydrogen.
10. according to the process of claim 1 wherein, described first dopant is B, and described second dopant is selected from P, As and Sb.
11. according to the process of claim 1 wherein, described second dopant is B, described first dopant is selected from P, As and Sb.
12., introduce described second dopant and comprise from the plasma of the type that is selected from glow discharge plasma and RF plasma and inject described second dopant according to the process of claim 1 wherein.
13. according to the method for claim 12, also comprise part by comprise described in and the carrier gas of material form described plasma.
14. according to the method for claim 13, wherein, described in and material comprise the inert gas that is selected from He, Ne, Ar, Kr and Xe.
15. according to the method for claim 13, wherein, described formation step comprises that the mixture by described carrier gas and dopant gas forms described plasma, wherein said in and material be 0～90% of described admixture of gas.
16. according to the process of claim 1 wherein, introduce described in and material comprise select described in and the dosage of material, in this dosage described and material neutralization is less than all described first dopants.
17. according to the method for claim 16, described in and the dosage of material be about 0.2～about 2 times of dosage of described second dopant.
18. according to the method for claim 16, wherein, introduce described in and material comprise that the active mark with described first dopant reduces about 20～90%.
19. according to the process of claim 1 wherein, introduce described in and material comprise that the active mark with described first dopant reduces at least even as big as effectively preventing the level of break-through.
20., introduce the peak concentration that described second dopant comprises described second dopant that provides bigger than the peak concentration of described first dopant according to the process of claim 1 wherein.
21. according to the process of claim 1 wherein, introduce described in and material comprise select described in and the injection degree of depth of material, make it relevant with first dopant side that described pn ties.
22., provide described substrate to be included in the process in growth of described substrate and the growth afterwards of described substrate described first dopant be incorporated in the described substrate according to the process of claim 1 wherein.
23. the device of the based semiconductor that the method by claim 1 is made.
24. the device of a based semiconductor comprises:
Substrate, described substrate comprise semiconductor, limit first and second dopants of pn knot and the described pn knot that neutralizes near described first dopant species a certain mark with reduce the electric capacity relevant with described pn knot in and material.
25. according to the device of claim 24, wherein, described pn knot is relevant with transistorized source electrode.
26. according to the device of claim 25, wherein, described first and second dopants limit the two pn knot relevant with transistor drain.
CNA200580032866XA 2004-08-27 2005-08-18 Reduction of source and drain parasitic capacitance in cmos devices Pending CN101031999A (en)

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WO2006026180A3 (en) 2006-08-03
JP2008511990A (en) 2008-04-17

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