CN101026194A - Non-volatile floating-gate memory based on two-layer nano silicon structure and its preparing method - Google Patents
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- CN101026194A CN101026194A CN200710021060.1A CN200710021060A CN101026194A CN 101026194 A CN101026194 A CN 101026194A CN 200710021060 A CN200710021060 A CN 200710021060A CN 101026194 A CN101026194 A CN 101026194A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 59
- 238000000034 method Methods 0.000 title claims description 51
- 239000005543 nano-size silicon particle Substances 0.000 title claims description 36
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229910004205 SiNX Inorganic materials 0.000 claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 42
- 239000010703 silicon Substances 0.000 claims description 42
- 238000000137 annealing Methods 0.000 claims description 29
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 22
- 230000005641 tunneling Effects 0.000 claims description 19
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 17
- 229910021423 nanocrystalline silicon Inorganic materials 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000001052 transient effect Effects 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 3
- 238000005499 laser crystallization Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 238000012423 maintenance Methods 0.000 claims description 2
- 238000004377 microelectronic Methods 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000003860 storage Methods 0.000 abstract description 16
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000002096 quantum dot Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
This invention relates to a semiconductor non-volatile floating grid storage based on double-layer nm Si structure, which takes p-type Si (resistivity: 1-10Ohm.cm) as a substrate and sets source and drain at either side of the substrate, and sets a SiO2 layer formed by a first tunnel dielectric layer of 1-2nm thick or a SiNx layer with the thickness of 3-5nm on the substrate, then a first Si nm layer with the grain size of 2-7nm, then a second tunnel dielectric layer of a SiO2 layer of 1-2nm thick or a SiNx layer of 3-5nm thick, then forms a second Si nm layer with the grain size of 2-7nm to be deposited to form a control SiN dielectric layer in the thickness of 8-20nm and a polysilicon grid is on the SiO or the SiN dielectric layer.
Description
Technical field
The present invention relates to the non-volatile floating gate memory of a kind of semiconductor, especially based on novel semi-conductor non-volatile floating-gate memory of two-layer nano silicon structure and preparation method thereof based on nano-silicon crystal grain.
Background technology
Flash memory (Flash memory) is as the non-volatile floating-gate memory typical device, moving electronic components such as USB flash disk, MP3 and mobile phone have been widely used at present, just promoting the modernization of daily life, more be expected to substitute in the near future the hard disk in the personal computer, computer is opened use and end when closing, be need not to make the information in the memory to read and restore from hard disk.
Studies show that in recent years, flush memory device is in the process of miniaturization, low-power consumption development, reached the restriction of nano-scale, make metal-oxide semiconductor fieldeffect transistor (MOSFET) device based on nano-silicon crystal grain, possibility of its application is subject to people's attention in low-power consumption of new generation in future, high integration nanoscale memory spare owing to its new physical phenomenon reaches.Fig. 1 is the cross-sectional view of this MOSFET device based on nano silicon structure.10:P type Si substrate wherein; 11: source (n+-Si); 12: leak (n+-Si); 13: tunnel oxide; The 14:nc-Si layer; 17: the controlled oxidation layer; 18: the polycrystalline Si grid; The operation principle of device is to change the threshold voltage of device by tunnelling and the electronics that is stored in the nano-silicon floating grid, thereby reaches the function of stored information.Sort memory is compared with common MOS structure memory, and its advantage is: because the coulomb blockade effect, each quantum dot (nano-silicon crystal grain) is being stored an electronics, and power consumption is very low; The tunneling barrier layer is very thin, and writing speed is very fast.But correspondingly, because the tunneling barrier layer is very thin, the charge storage time of nano-silicon memory fails to reach the requirement of application, again because electronic effect charge storage of each quantum dot storage.
The Chinese patent application CN01108248.8 germanium/MOSFET memory with composite nm-grain Ge/Si float grid structure of the applicant's application, be embedded in floating-gate memory structure in the silicon dioxide with germanium/composite nm-grain Ge/Si, adopt germanium/composite nm-grain Ge/Si substituted for silicon nanocrystal as MOSFET memory, i.e. charge storage elements.And relating to the double-layer nanometer silicon crystal grain, the application is embedded in floating-gate memory structure in the dielectric layer.
Summary of the invention
The objective of the invention is: propose to adopt two-layer nano silicon structure to substitute conventional individual layer nano silicon structure as charge storage elements, to solve writing and erasable programming time and the contradiction of memory time of individual layer nano-silicon floating-gate memory, thereby under shorter programming time prerequisite, effectively prolong the charge storage time, meanwhile strengthened the storage capacity of electric charge again.
Technical solution of the present invention is: based on the semiconductor non-volatile floating-gate memory of two-layer nano silicon structure, comprise semiconductor P type Si substrate 20; Be medium tunnel layer 23 directly over the raceway groove between source-drain electrode, it is the tunnelling silicon nitride layer that forms with the tunnel oxide silicon layer of plasma oxidation method formation or the deposit of PECVD method; Above tunneling medium layer, form double-layer nanometer silicon layer 24 and 26; It between the double-layer nanometer silicon layer tunneling medium layer 25; Deposit control medium layer (silica or silicon nitride 27) then; Use low pressure chemical vapor deposition (LPCVD) method deposit polysilicon as grid on it.Utilize self-registered technology in Semiconductor substrate and polysilicon, to mix at last and form source electrode 21, drain electrode 22 and grid 28.Double-layer nanometer silicon layer in the said structure is as charge storage elements (referring to Fig. 2).
Particularly described tunneling medium layer is meant tunnel oxide silicon SiO
2Layer or tunnelling silicon nitride SiNx layer.As substrate, source-drain area is in the left and right sides of substrate with p type silicon (resistivity is 1-10 Ω cm), and the ground floor tunneling medium layer is SiO on the substrate
2Layer, thickness is 1-2nm or SiNx layer, thickness is 3-5nm; Be the first nanometer Si layer then, crystallite dimension is 2-7nm; Second layer tunneling medium layer also is SiO
2Layer, thickness is 1-2nm or SiNx layer, thickness is 3-5nm; Be the second nanometer Si layer then, crystallite dimension is 2-7nm; Deposit forms control SiNx dielectric layer on the second nanometer Si layer, and thickness is 8-20nm; On the control medium layer, be polysilicon gate.
Preparation method of the present invention: the preparation of described two-layer nano silicon structure is the SiO that tunneling medium layer forms on p type silicon substrate in the PECVD system
2Directly form the nanometer silicon layer with growth/etching (layer by layer) method successively on the layer, also can be in the PECVD system earlier growth amorphous silicon (a-Si) layer form the nanometer silicon layer (density of nano-silicon＞5 * 10 with the method for thermal annealing or the method for laser crystallization then
11Cm
-2).The formation method of tunnel oxide silicon layer: the ionic medium body carries out oxidation to silicon in the PECVD system: oxygen flow is: 27sccm; Underlayer temperature: 250 ± 30 ℃; Air pressure: 320 ± 50mTorr; Time: 20 ± 5min; The SiO that forms
2Layer: thickness is about 1-2nm;
The formation method of tunnelling SiNx layer: deposit SiNx layer feeds SiH in the PECVD system
4/ NH
3Flow: 5sccm/45sccm; Underlayer temperature: 250 ± 30 ℃; Power source frequency: 13.56MHz, power: 30W; Air pressure: 320 ± 50mTorr; Time: 50 ± 10s.Form the SiNx layer: thickness is about 3-5nm.
The formation of nanometer silicon layer can be selected for use in the PECVD system and be passed through SiH
4Deposition of amorphous silicon (a-Si), successively growth/etching (the layer by layer) method or the a-Si layer of growing earlier form the nanometer silicon layer with the thermal annealing method then.Growth/etching (layer by layer) method successively: first deposit a-Si layer, after use H
2Plasma etching just can form the nc-Si layer after so repeating several cycles, at last under 900 ℃ of conditions in nitrogen atmosphere annealing 30 minutes to improve nc-Si layer quality.
Elder generation's deposit a-Si layer is after thermal annealing forms the method for nanometer silicon layer: the quasistatic method for annealing: kept 1 hour in nitrogen atmosphere under 1100 ℃ of conditions or the thermal transient annealing method that combines with conventional thermal annealing: in the nitrogen atmosphere, keep 50-150s after with the step-length of 100 ℃/s temperature being risen to 800-1000 ℃, after the cooling, kept 1 hour after with the step-length of 10 ℃/min temperature being risen to 1000 ℃ or 1100 ℃ again.The thermal annealing method is meant the method that conventional high temperature furnace quasistatic method for annealing or thermal transient annealing combine with conventional thermal annealing.
Because the thickness of control medium layer generally need reach more than the 10nm, if use the SiNx layer, then only need to adopt the condition of tunnelling SiNx layer, only prolonging deposition time is that 100 ± 10s gets final product.
Characteristics of the present invention:
1. propose to adopt two-layer nano silicon structure to substitute the individual layer nano silicon structure as floating gate memory cell, under suitable applied voltage, continue to enter second layer nanometer silicon layer after electric charge being finished deposit the ground floor nano-silicon in, also can make electric charge directly enter second layer nanometer silicon layer, thereby be implemented under the short programming time prerequisite, the memory time of effective boost device, both solved the programming time of nano-silicon floating-gate memory and the contradiction of memory time, and can improve charge storage simultaneously and realize the bifurcation storage.
2. the preparation method of the two-layer nano silicon structure that adopts of the inventive method, promptly 1) (layer by layer) growth/lithographic method directly forms the nanometer silicon layer with successively in the PECVD system; 2) in the PECVD system earlier growth amorphous silicon (a-Si) layer form the nanometer silicon layer with the method for thermal annealing or the method for laser crystallization then, be with current microelectronic processing technology compatible mutually.
3. the inventive method adopts PECVD method original position formation two-layer nano silicon/medium tunnel layer structure in growth chamber to have tangible layer structure, effectively control the relative position of two-layer nano-silicon.
4. contain in the MOS structure of two-layer nano silicon, double-deck nc-Si quantum-dot structure injects phenomenon at the two-stage electric charge of accumulation area and inversion regime.The C-V characteristic curve has disclosed this phenomenon, as shown in Figure 3.At flat band voltage skew (Δ V
Fb) in the change curve with the accumulation area scanning voltage, can observe two tangible steps (Fig. 4).
5. the energy band diagram (Fig. 5) when substrate is in transoid in the two-layer nano silicon structure is used for illustrating that two-layer nano silicon has stronger storage capacity.Under suitable external voltage, when the electron energy of second layer nanometer silicon layer is consistent with ground floor nanometer silicon layer, electronics enters second layer nanometer silicon layer from ground floor nanometer silicon layer tunnelling, the tunnelling electronics relaxes towards on the interfacial state of second layer nano-silicon then, and store into there, it will be difficult to tunnelling again and return substrate, and only be tunneling to electronics in the ground floor nanometer silicon layer, be to be easier to tunnelling to return substrate, that is to say that second layer nanometer silicon layer will show the storage capacity stronger than ground floor (longer memory time).
Fig. 6 (a) and (b) provide the I-V characteristic curve of charge storage two-layer nano silicon MOS structure under the second layer and ground floor situation respectively.I-V curve display asymmetry in the electronics charge and discharge process among Fig. 6 (a), and approaching symmetry among Fig. 6 (b) has reconfirmed that second layer nanometer silicon layer has than the stronger storage capacity of ground floor nanometer silicon layer.
Description of drawings:
Fig. 1 is based on the cross-sectional view of the MOSFET device of nano silicon structure.
Fig. 2 is based on the cross-sectional view of the MOSFET device of two-layer nano silicon structure.
Fig. 3 is that the two-stage electric charge of double-deck nc-Si quantum-dot structure injects the phenomenon schematic diagram, and returning stagnates increases Fig. 3 (a) in the injection of the hole of accumulation area along with the increase of bias voltage, and Fig. 3 (b) injects at the electronics of inversion regime.
Fig. 4 is flat band voltage skew (the Δ V of C-V curve of sample that contains the double-deck nc-Si quantum dot of storehouse
Fb) with the variation of accumulation area scanning voltage, can observe two tangible steps, illustration has shown because electronics injects the Δ V that causes
FbPlatform effect; And have only a step in the sample that contains individual layer nc-Si quantum dot of round dot representative.
Fig. 5 is the energy band diagram when substrate is in transoid in the two-layer nano silicon MOS structure.
Fig. 6 is the I-characteristic curve of charge storage two-layer nano silicon MOS structure under second layer Fig. 6 (a) and ground floor Fig. 6 (b) situation.
Among Fig. 1: 10 P type Si substrates, 11 sources (n+-Si), 12 leak (n+-Si), 13 tunnel oxides, 14nc-Si layer, 17 controlled oxidation layers, 18 polycrystalline Si grid
Among Fig. 2: 20 P type Si substrates, 21 sources (n+-Si), 22 leak (n+-Si), 23 tunneling medium layer, 24 ground floor nc-Si layers, 25 tunneling medium layer, 26 second layer nc-Si layers, 27 control medium layers, 28 polycrystalline Si grid
Embodiment
Referring to Fig. 2 structure of the present invention: as substrate, source-drain area is in the both sides of substrate with p type silicon (resistivity is 1-10 Ω cm), and ground floor tunneling medium layer thickness is 1-2nm on the substrate, as the SiO of 2nm
2Layer; Or 3-5nm, as the SiNx layer of 4nm, be the first nanometer Si layer then, crystallite dimension is 2-7nm, as 3 or 5nm; Second layer tunneling medium layer is with first tunneling medium layer on the substrate; Be the second nanometer Si layer then, crystallite dimension is 2-7nm, as 3 or 5nm; Deposit forms silica or the silicon nitride medium layer as control gate on the second nanometer Si layer, and thickness is 10nm, and 15nm also can.
1. select for use p type silicon (resistivity is 1-10 Ω cm) as substrate
2. the formation of ground floor tunneling medium layer (can select silicon oxide layer or silicon nitride layer for use)
2.1 tunnelling SiO
2The formation of layer
(1) method: PECVD system ionic medium body oxidation
(2) condition: O
2Throughput: 27sccm; Underlayer temperature: 250 ℃; Power source frequency: 13.56MHz, power: 80W; Air pressure: 320mTorr; Time: 10min
(3) form SiO
2Layer: thickness is about 1-2nm, and barrier height is 3.1eV
2.2 the formation of tunnelling SiNx layer
(1) method: deposit SiNx layer in the PECVD system
(2) condition:
SiH
4/ NH
3Flow: 5sccm/45sccm; Underlayer temperature: 250 ℃; Power source frequency: 13.56MHz, power: 30W; Air pressure: 320mTorr; Time: 50s.
(3) form the SiNx layer: thickness is about 3-5nm, and barrier height is 1.4eV
The formation of ground floor nanometer silicon layer can select for use in the PECVD system successively growth/etching (layer by layer) method (referring to 3.1) or earlier growth amorphous silicon (a-Si) layer use thermal annealing (referring to 3.2) to form the nanometer silicon layer then
3.1 growth/etching (layer by layer) method successively
(1) method: first deposit a-Si layer, the H2 plasma etching use in the back, just can form the nc-Si layer after so repeating several cycles, anneals 30 minutes at last to improve nc-Si layer quality under 900 ℃ of conditions in nitrogen atmosphere
(2) condition:
A) deposit a-Si
SiH
4Flow: 2sccm; H
2Flow: 80sccm; Deposition time: 120s; Underlayer temperature: 250 ℃; Air pressure: 710mTorr; Power source frequency: 13.56MHz, power: 50W
B) H2 plasma treatment: close SiH
4Gas circuit (only keeps H
2Gas circuit), processing time 60s.Other condition is identical during with deposit.
The final nc-Si crystallite dimension that forms is about 2-7nm, the density of nano-silicon＞5 * 10 by repetition period numerical control system
11Cm
-2
3.2 first deposit a-Si layer is after thermal annealing forms the method for nanometer silicon layer
(1) deposit a-Si layer condition
SiH
4Flow: 8sccm; Ar flow: 10sccm; Air pressure: 310mTorr; Power source frequency: 13.56MHz, power: 30W; Time: 20-70s
(2) thermal annealing condition
A) quasistatic method for annealing: in nitrogen atmosphere, kept 1 hour under 1100 ℃ of conditions
B) the thermal transient annealing method that combines with conventional thermal annealing: in the nitrogen atmosphere, keep 50-150s after with the step-length of 100 ℃/s temperature being risen to 800-1000 ℃, after the cooling, with the step-length of 10 ℃/min temperature is risen to 1000 ℃ or 1100 ℃ again after maintenance 1 hour
(3) form the nc-Si crystallite dimension between 2-7nm, concrete size is by the a-Si layer thickness decision of original deposit, the density of nano-silicon＞5 * 10
11Cm
-2
4. second layer tunneling medium layer forms (condition is with 2)
5. second layer nanometer silicon layer forms (condition is with 3)
6. the formation of medium control gate (SiNx layer)
(1) method: deposit SiNx layer in the PECVD system
(2) condition:
SiH
4/ NH
3Flow: 5sccm/45sccm; Underlayer temperature: 250 ℃; Power source frequency: 13.56MHz, power: 30W; Air pressure: 310mTorr; Time: 100s; The thickness of deposit SiNx layer: 10nm.
7. deposit polysilicon, the photolithographic source drain region, phosphonium ion injects, and annealing forms n
+Source-drain area, low temperature deposition SiO
2Layer, photolithographic source, leakage, grid region fairlead, evaporation of aluminum anti-carves and waits these several steps consistent with conventional MOSFET device technology.
Claims (3)
1, based on the semiconductor non-volatile floating-gate memory of two-layer nano silicon structure, with p type silicon (resistivity is 1-10 Ω cm) as substrate (20), source-drain electrode (22,28) is characterized in that being provided with earlier the SiO that the ground floor tunneling medium layer forms in the both sides of substrate on substrate
2Layer (23), thickness is 1-2nm or SiNx layer, thickness is 3-5nm; Be the first nanometer Si layer (24) then, crystallite dimension is 2-7nm; Second layer tunneling medium layer also is SiO on the substrate
2Layer (26), thickness is 1-2nm or SiNx layer, thickness is 3-5nm; Be the second nanometer Si layer then, crystallite dimension is 2-7nm; Deposit forms control silicon nitride medium layer on the second nanometer Si layer, and thickness is 8-20nm; On silica or the silicon nitride medium layer is polysilicon gate.
2, based on the preparation method of the semiconductor non-volatile floating-gate memory of two-layer nano silicon structure: adopt and the microelectronic technique preparation technology of compatibility mutually; It is characterized in that the SiO that tunneling medium layer forms on p type silicon substrate in the PECVD system
2Directly form the nanometer silicon layer with growth/lithographic method successively on the layer, pass through SiH earlier
4Deposit a-Si, successively growth/etching (layer by layer) method or earlier growth amorphous silicon (a-Si) layer form the nanometer silicon layer with the method for the method of thermal annealing then: the method for growth/etching (layer by layer) successively: first deposit a-Si layer, after use H
2Plasma etching so repeats several (2-10) all after dates and just can form the nc-Si layer, anneals 30 minutes at last to improve nc-Si layer quality under 900 ℃ of conditions in nitrogen atmosphere; Or in the PECVD system earlier growth amorphous silicon (a-Si) layer use the method (leave out: or the method for laser crystallization) of thermal annealing to form the nanometer silicon layer then: the method that forms the nanometer silicon layer through thermal annealing: quasistatic method for annealing: in nitrogen atmosphere, kept 1 hour under 1100 ℃ of conditions; The thermal transient annealing method that combines with conventional thermal annealing: in the nitrogen atmosphere, keep 50-150s after with the step-length of 100 ℃/s temperature being risen to 800-1000 ℃, after the cooling, with the step-length of 10 ℃/min temperature is risen to 1000 ℃ or 1100 ℃ again after maintenance 1 hour.The thermal annealing method is meant the method that conventional high temperature furnace quasistatic method for annealing or thermal transient annealing combine with conventional thermal annealing.
3, according to the preparation method of the described semiconductor non-volatile floating-gate memory based on two-layer nano silicon structure of claim 2, it is characterized in that the formation method of tunnel oxide silicon layer: at PECVD system ionic medium body the logical oxygen of silicon is carried out oxidation: underlayer temperature: 250 ± 30 ℃; Air pressure: 320 ± 50mTorr; Time: 10 ± 5min; The SiO that forms
2Layer: thickness is about 1-2nm; The formation method of tunnelling SiNx layer: deposit SiNx layer feeds SiH in the PECVD system
4/ NH
3Flow: 5sccm/45sccm; Underlayer temperature: 250 ± 30 ℃; Power source frequency: 13.56MHz, power: 30W; Air pressure: 320 ± 50mTorr; Time: 50 ± 10s.Form the SiNx layer: thickness is about 3-5nm.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800199A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Method for manufacturing flash memory |
| CN102831923A (en) * | 2011-06-14 | 2012-12-19 | 旺宏电子股份有限公司 | Thermal assisting dielectric charge catch flash memory |
| CN105576124A (en) * | 2016-01-14 | 2016-05-11 | 中国计量学院 | Dual-layer floating gate flexible organic memory device and preparation method therefor |
-
2007
- 2007-03-23 CN CNB2007100210601A patent/CN100483744C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800199A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Method for manufacturing flash memory |
| CN101800199B (en) * | 2010-03-12 | 2015-05-06 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory |
| CN102831923A (en) * | 2011-06-14 | 2012-12-19 | 旺宏电子股份有限公司 | Thermal assisting dielectric charge catch flash memory |
| CN102831923B (en) * | 2011-06-14 | 2015-09-30 | 旺宏电子股份有限公司 | Heat assists dielectric charge catch flash memory |
| CN105576124A (en) * | 2016-01-14 | 2016-05-11 | 中国计量学院 | Dual-layer floating gate flexible organic memory device and preparation method therefor |
| CN105576124B (en) * | 2016-01-14 | 2018-06-19 | 中国计量学院 | A kind of double-layer floating gate flexibility organic memory device and preparation method thereof |
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| CN100483744C (en) | 2009-04-29 |
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