CN101017811A - Multi-chip stack structure - Google Patents
Multi-chip stack structure Download PDFInfo
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- CN101017811A CN101017811A CNA2006100074316A CN200610007431A CN101017811A CN 101017811 A CN101017811 A CN 101017811A CN A2006100074316 A CNA2006100074316 A CN A2006100074316A CN 200610007431 A CN200610007431 A CN 200610007431A CN 101017811 A CN101017811 A CN 101017811A
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- chip
- stack structure
- semiconductor
- semiconductor chip
- chip stack
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The disclosed multi-chip stack structure comprises: a chip support member, multiple semiconductor chips ladder-type stacking on last member, and at least one passive element set on the support member corresponding to the lower part of overhung stacking chip on the support member. This invention applies the passive element as filler to prevent aero-hole during packing and extruding, or as barrier member to prevent impacting chip when the bonding wire away the injecting mold entrance, and provides a arrangement area for passive element by setting the passive element on said position.
Description
Technical field
The invention relates to a kind of multi-chip stack structure, particularly about a kind of a plurality of stack architectures with monolateral weld pad chip.
Background technology
Because the increase of miniaturization of electronic products and high-speed cruising demand, need to improve single semiconductor package performance and capacity to meet the demand of miniaturization of electronic products, the semiconductor package part structure is a trend with multicore sheet encapsulation (Multichip package), by two or more semiconductor chips are combined in the single encapsulating structure, reduce the integrated circuit volume, and improve electrical functionality.Be that multichip packaging structure can be with two or more chip portfolios in single encapsulating structure, the restriction minimum that system running speed is subjected to.In addition, multichip packaging structure can reduce the length of chip chamber connection line, thereby reduces signal delay and access time.
Common multichip packaging structure adopts side-by-side (side-by-side) multichip packaging structure, plural chip is installed in side by side the main installed surface of same substrate.It is bigger that but the shortcoming of this side-by-side multichip packaging structure is an encapsulation volume, because this same chip area can strengthen along with the increase of core number.
For solving above-mentioned existing issue, often use the chip that stacking method is installed to be increased in recent years, the storehouse mode is had nothing in common with each other according to the design and the wire bond processing procedure of chip.As memory card architecture is a kind of high-capacity flash memory circuit module of integrating a plurality of chips, flash chip (the flash memory chip) weld pad that it is surperficial concentrates design on one side, therefore, when chip stack, adopt step-wise manner to carry out storehouse, these stack chips are exposed outside be located at its weld pad on one side, be convenient to the follow-up wire bond operation of carrying out.
Fig. 1 is a United States Patent (USP) the 6th, 900, a kind of multi-chip stack structure that discloses for No. 528, it is a plurality of chips of storehouse on chip bearing member 10, so that first chip 11 is installed on the chip bearing member 10, second chip 12 is with an offset distance and not hinder the wire bond operation of first chip, 11 weld pads 110 be principle, storehouse is on this first chip 11, the 3rd chip 13 is with an offset distance and not hinder the wire bond operation of second chip, 12 weld pads 120 be principle, storehouse is on this second chip 12, so that form the ladder chip stack structure; Then carry out the wire bond operation again, utilize a plurality of bonding wires 14 to make this first, second and third chip 11,12,13 be electrically connected to this chip bearing member.
Though above-mentioned ladder chip stack structure is saved the space than chip form side by side, and can first stack chip, carry out the wire bond operation again, and form the packing colloid that coats this stack chip and bonding wire by Encapsulation Moulds compacting journey, quicken process operations; Wherein, for impacting this bonding wire, the mould stream that reduces Encapsulation Moulds compacting journey cause bank to topple over (sweep) or fracture (broken), injection molding mouth (mold gate) the G position of this Encapsulation Moulds compacting journey certainly will be parallel with bonding wire cloth set direction, its possible example is shown in Fig. 2 A or Fig. 2 B, make its bonding wire end away from injection molding mouth G (shown in Fig. 2 A), or make its bonding wire end towards injection molding mouth G (shown in Fig. 2 B).
But, shown in Fig. 2 A, when bonding wire end during away from injection molding mouth G, in Encapsulation Moulds compacting journey, when this injection molding mouth G injects potting resin and forms the packing colloid that coats this ladder chip stack structure, directly impact this ladder chip stack structure overhanging portion of chip at the middle and upper levels because of the potting resin mould fails to be convened for lack of a quorum, therefore, cause the upper strata chip to peel off problem (shown in dotted line) easily.
Relatively, shown in Fig. 2 B, when bonding wire end during towards injection molding mouth G, in Encapsulation Moulds compacting journey, when this injection molding mouth G injects potting resin and forms the packing colloid that coats this ladder chip stack structure, influence because of being subjected to mould to flow back to stream, easily at the overhanging portion formation gas hole v of this ladder chip stack structure, even cause when subsequent heat treatment and reliability testing, producing puffed rice (popcorn) effect, cause the generation of the bad problem of encapsulating products.
In addition, Fig. 3 is a United States Patent (USP) the 6th, 040, the semiconductor device floor map that discloses for No. 622, electrical functionality for electronic products such as raising said memory card, certainly will in encapsulating structure, set up, but these passive devices 35 generally are laid in chip 31 both sides, will cause the encapsulating structure planar dimension to increase like this as passive devices 35 such as electric capacity, resistance or inductance elements.
Therefore, how to provide a kind of multi-chip stack structure of avoiding in Encapsulation Moulds compacting journey, to produce problems such as gas hole or upper strata chip are impacted by mould stream to cause to peel off, can effectively provide passive device to lay the zone simultaneously, become present problem demanding prompt solution.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of multi-chip stack structure, avoids that stack chip is subjected to mould stream to impact the problem of peeling off that causes in Encapsulation Moulds compacting journey.
A further object of the present invention is to provide a kind of multi-chip stack structure, avoids producing gas hole problem in Encapsulation Moulds compacting journey.
Another purpose of the present invention is to provide a kind of multi-chip stack structure, and the laying zone of passive device can fully be provided.
For realizing above-mentioned and other purpose, the invention provides a kind of multi-chip stack structure, this multi-chip stack structure comprises: a chip bearing member; A plurality of semiconductor chips, with step-wise manner storehouse successively on this chip bearing member; And at least one passive device, connect put on this chip bearing member corresponding to this ladder stacked semiconductor chip hang at home and abroad semiconductor chip below.In this semiconductor chip stack architecture, the weld pad of upper and lower layer semiconductor chip is positioned at the same side, and upper strata semiconductor chip skew lower floor semiconductor chip preset distance, it is directly upwards regional to avoid covering lower floor's semiconductor chip weld pad, is electrically connected to this chip bearing member for these semiconductor chips by bonding wire.
Multi-chip stack structure of the present invention mainly on the chip bearing member in the ladder chip stack structure corresponding to outside hang chip a side set in advance passive device, in Encapsulation Moulds compacting journey, to should stepped core sheet stack architecture bonding wire holding row level with both hands when the injection molding mouth, can utilize this passive device to avoid the gas hole to produce as filling member; Relatively, corresponding parallel during when the bonding wire end away from the injection molding mouth, can utilize this passive device to avoid mould stream directly to impact chip as block piece, cause chip to peel off problem; Simultaneously since this passive device connect put on this chip bearing member corresponding to stack chip outside outstanding part below, can fully provide passive device to lay the zone, avoid existing passive device to be laid in the chip both sides and cause usable floor area to increase, thereby reduce the planar dimension of encapsulating structure.
Description of drawings
Fig. 1 is a United States Patent (USP) the 6th, 900, the generalized section of the multi-chip stack structure of No. 528 announcements;
Fig. 2 A is that the generalized section that the upper strata chip is peeled off problem takes place when Encapsulation Moulds compacting journey existing multi-chip stack structure;
Fig. 2 B is the generalized section that gas hole problem takes place when Encapsulation Moulds compacting journey existing multi-chip stack structure;
Fig. 3 is a United States Patent (USP) the 6th, 040, the semiconductor device floor map of No. 622 announcements;
Fig. 4 A and Fig. 4 B are section and the floor map of multi-chip stack structure embodiment 1 of the present invention; And
Fig. 5 is the generalized section of multi-chip stack structure embodiment 2 of the present invention;
Embodiment
Embodiment 1
Fig. 4 A and Fig. 4 B are the section and the floor map of multi-chip stack structure of the present invention.As shown in the figure, this multi-chip stack structure comprises: a chip bearing member 40; A plurality of semiconductor chips 41, with step-wise manner storehouse successively on this chip bearing member 40; And at least one passive device 45, connect put hang at home and abroad corresponding to this ladder stacked semiconductor chip on this chip bearing member 40 semiconductor chip below.
This chip bearing member 40 is substrate structures.These a plurality of semiconductor chips 41 that carry out storehouse are flash chips, its planar dimension is basic identical, and be provided with a plurality of weld pads 410 monolateral, keep supplying layer semiconductor chip 41 and have a lateral deviation of weld pad 410 from lower floor's semiconductor chip 41 1 preset distances, and make upper strata semiconductor chip 41 can not keep off the weld pad 410 straight upwards zones of lower floor's semiconductor chip 41, carry out respectively this semiconductor chip 41 of storehouse successively, formation has the outstanding ladder chip stack structure of monolateral chip outward, and expose outside the respectively weld pad 410 of this semiconductor chip 41, thereby be electrically connected to this chip bearing member 40 by many bonding wires 44 for these semiconductor chips 41.
In the present embodiment, the injection molding mouth G that injects potting resin when the cloth set direction of this bonding wire 44 and this multi-chip stack structure of encapsulation is parastate, and this bonding wire end correspondence is located at the side away from this injection molding mouth G, i.e. the corresponding side towards this injection molding mouth G of outer outstanding chip part of this ladder stack chip.
This passive device 45 is electric capacity, resistance or inductance element etc., for connect put hang corresponding to this ladder stacked semiconductor chip 41 China and foreign countries on this chip bearing member 40 chip below.
Like this, not only can improve the overall structure electrical functionality, can utilize this passive device 45 as block piece simultaneously, avoid potting resin mould stream directly to impact this ladder chip stack structure, cause chip to peel off problem by this passive device 45.
Embodiment 2
Fig. 5 is the generalized section of multi-chip stack structure embodiment 2 of the present invention.Multi-chip stack structure and the foregoing description of present embodiment are roughly the same, main difference is that this bonding wire end correspondence is located at the side towards this injection molding mouth G, promptly the outer outstanding chip part correspondence of this ladder stack chip is away from the side of this injection molding mouth G, like this, this connects puts on chip bearing member 40, and the passive device 45 that hangs the chip below corresponding to this ladder stacked semiconductor chip at home and abroad can be used as filling member, avoids the generation in gas hole in the Encapsulation Moulds compacting journey.
Therefore, multi-chip stack structure of the present invention mainly be on the chip bearing member of ladder chip stack structure corresponding to outside hang chip a side set in advance at least one passive device, in Encapsulation Moulds compacting journey, bonding wire that should stepped core sheet stack architecture is held level with both hands row when the injection molding mouth, can utilize this passive device to avoid the generation in gas hole as filling member; Relatively,, can utilize this passive device to avoid mould stream directly to impact chip, cause chip to peel off problem as block piece when the bonding wire end is corresponding parallel during away from the injection molding mouth; Simultaneously since this passive device connect put on this chip bearing member corresponding to stack chip outside outstanding part below, can fully provide passive device to lay the zone, avoid existing passive device to be laid in the chip both sides and cause usable floor area to increase, thus the planar dimension of reduction encapsulating structure.
Claims (11)
1. a multi-chip stack structure is characterized in that, this multi-chip stack structure comprises:
One chip bearing member;
A plurality of semiconductor chips, with step-wise manner storehouse successively on this chip bearing member; And
At least one passive device, connect put on this chip bearing member corresponding to this ladder stacked semiconductor chip hang at home and abroad semiconductor chip below.
2. multi-chip stack structure as claimed in claim 1 is characterized in that, this chip bearing member is a substrate structure.
3. multi-chip stack structure as claimed in claim 1 is characterized in that this semiconductor chip is a flash chip.
4. multi-chip stack structure as claimed in claim 1, it is characterized in that this semiconductor chip is monolateral to be provided with a plurality of weld pads, when this semiconductor chip of storehouse successively, can expose outside the respectively weld pad of this semiconductor chip, formation has the outstanding ladder chip stack structure of monolateral chip outward.
5. multi-chip stack structure as claimed in claim 4, it is characterized in that, in this semiconductor chip stack architecture, the weld pad of upper and lower layer semiconductor chip is positioned at the same side, and upper strata semiconductor chip skew lower floor semiconductor chip one preset distance, it is directly upwards regional to avoid covering lower floor's semiconductor chip weld pad, is electrically connected to this chip bearing member for these semiconductor chips by bonding wire.
6. multi-chip stack structure as claimed in claim 1 is characterized in that this semiconductor chip is electrically connected to this chip bearing member by many bonding wires.
7. multi-chip stack structure as claimed in claim 6 is characterized in that, the injection molding mouth that injects potting resin when this bonding wire cloth set direction and this multi-chip stack structure of encapsulation is parastate.
8. multi-chip stack structure as claimed in claim 7 is characterized in that, this bonding wire end correspondence is located at the side away from this injection molding mouth.
9. multi-chip stack structure as claimed in claim 7 is characterized in that, the corresponding side towards this injection molding mouth of outer outstanding chip part of this ladder stack chip.
10. multi-chip stack structure as claimed in claim 7 is characterized in that, this bonding wire end correspondence is located at the side towards this injection molding mouth.
11. multi-chip stack structure as claimed in claim 7 is characterized in that, the corresponding side away from this injection molding mouth of outer outstanding chip part of this ladder stack chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100074316A CN101017811A (en) | 2006-02-10 | 2006-02-10 | Multi-chip stack structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100074316A CN101017811A (en) | 2006-02-10 | 2006-02-10 | Multi-chip stack structure |
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| Publication Number | Publication Date |
|---|---|
| CN101017811A true CN101017811A (en) | 2007-08-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100074316A Pending CN101017811A (en) | 2006-02-10 | 2006-02-10 | Multi-chip stack structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017107174A1 (en) * | 2015-12-25 | 2017-06-29 | Intel Corporation | Flip-chip like integrated passive prepackage for sip device |
| CN114975414A (en) * | 2022-04-29 | 2022-08-30 | 盛合晶微半导体(江阴)有限公司 | Stacked memory POP packaging structure and packaging method thereof |
-
2006
- 2006-02-10 CN CNA2006100074316A patent/CN101017811A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017107174A1 (en) * | 2015-12-25 | 2017-06-29 | Intel Corporation | Flip-chip like integrated passive prepackage for sip device |
| US11101254B2 (en) | 2015-12-25 | 2021-08-24 | Intel Corporation | Flip-chip like integrated passive prepackage for SIP device |
| CN114975414A (en) * | 2022-04-29 | 2022-08-30 | 盛合晶微半导体(江阴)有限公司 | Stacked memory POP packaging structure and packaging method thereof |
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