CN101017508A - SoC software-hardware partition method based on discrete Hopfield neural network - Google Patents

Abstract

This invention relates to one SoC software and hardware division method based on discrete Hopfield neutral network, which comprises the following steps: adopting pattern description method to divide the software and hardware problem into one detail combination optimization problem to introduce SoC division problem new module; then according to the division property, re-defining discrete Hopfield neural network element, energy function, operation equation and parameters; dividing the discrete Hopfield network as division formula on SoC chip functions.

Description

A kind of SoC software/hardware division methods based on discrete hopfield neural network

Affiliated technical field

The present invention relates to the software/hardware collaborative design and the neural network algorithm technical field of SoC chip, especially relate to a kind of SoC software/hardware division methods based on discrete hopfield neural network.

Background technology

SoC (System-on-a-Chip), be called for short SOC (system on a chip) or System on Chip/SoC, as a kind of new model of embedded system, single computer systems function required hardware integrated circuit and embedded software have been realized to finish in an IC (Integrated Chip integrated circuit (IC) chip) lining usually.Compare with traditional embedded system, SoC has many tangible advantages, as volume is little, low in energy consumption, reliability is high and higher cost performance etc., shortcoming is that complicacy rising, design cost height, construction cycle are long, has changed the overall design framework of previous machine system fully.SoC is the IC of a customization normally, but generally is made up of hardware cell, the application of general microprocessor core programming in logic relevant hardware-accelerated circuit and corresponding embedded software.The SoC chip design combines IC and (comprises Analogous Integrated Electronic Circuits and digital integrated circuit, even radio frequency integrated circuit) content of design and embedded software (comprising embedded OS and built-in application program) exploitation two aspects, the emphasis that still not national " Policies for Encouraging the Development of Software Industry and IC Industry " (i.e. No. 18 files) are supported, and be the research focus of academia and the new technology that industry member is widelyd popularize application.

At present in the development approach of SoC, collaborative simulation is relative with the co-verification method ripe, and have some EDA (ElectronicDesign Automation electric design automation) instrument in application, to obtain good effect, as the Seamless CVE of Mentor Graphics company, the Eagle I of Synopsys company and the DSM of Celoxica company etc.That is that all right is ripe for the method for designing of SoC (as the software/hardware collaborative design), and the EDA design tool mainly uses existing IC design tool to slap together, and many technical barriers wait to break through.Wherein, to divide (Software-hardware Automated Partitioning) automatically be a major issue to the software/hardware of SoC.

The increased popularity on market along with SoC technology and product, according to its structure, the function of SoC is not to adopt hardware to realize, and partial function adopts software to realize improving greatly the performances such as dirigibility of SoC.It is a committed step of SoC software/hardware collaborative design (Hardware-software Co-design) method that the software/hardware of SoC is divided (being called for short SoC divides) automatically, it has determined which function of SoC to be realized by hardware, which function should be realized by software, it is divided the result and directly has influence on SoC Products Development efficient and quality, this is a traditional problem of Computer Systems Organization, also is the new problem that current SoC design faces.In addition, the SoC division also is that the embedded system of configurable (Re-configurable), the embedded system and the embedded system of application relevant (Application-specific) generate the important foundation of (Automatic Generation) research and development automatically.

In the face of the SoC partition problem, some researchers are from different angles, propose the automatic division methods of each purpose software/hardware for satisfying different target calls, mainly comprised simulated annealing, genetic algorithm, ant algorithm, tabu search algorithm, Petri Nets, integral linear programming etc.But, because the SoC system is very complicated, on problems such as SoC modeling, constraint condition and multiobject refinement, the design of optimization derivation algorithm, division evaluation of result and system architecture, it is bigger that modeling and algorithm are found the solution difficulty, it is optimum that many algorithms in past are difficult to guarantee to divide the result, or suboptimum.Relevant research was made slow progress in recent years, had only obtained preliminary application in some eda tools.

Summary of the invention

It is a np complete problem that SoC divides, and its main target is that the behaviour with SoC optimally is being assigned on the software/hardware system architecture of SoC under certain constraint condition.In some research, SoC is divided as the comprehensive part of SoC software/hardware.The behaviour of SoC generally adopts task image (Task Graph) modeling, and for software, a task is the set with a series of arithmetic operations clear and definite interface, coarseness, is usually expressed as an algorithmic procedure, an object or a member; For hardware, a task is a specific I P (Intellectual Property intellecture property) module, has function, interface and constraint clearly.

The object of the present invention is to provide a kind of SoC based on discrete hopfield neural network to divide and optimized derivation algorithm, solved the technical scheme that its technical barrier adopts and be:

1, adopts the describing method of graph theory, the SoC partition problem is converted into a concrete combinatorial optimization problem, introduced a new model of SoC partition problem, successfully realized the modeling of SoC partition problem, this helps to understand the essence that SoC divides, and separates searching algorithm for devise optimum and lays a solid foundation.

2, according to SoC partition problem model, adopt discrete hopfield neural network to search for its optimum solution, the neuron that has redefined discrete hopfield neural network is represented, energy function, operation equation and coefficient, to satisfy the particular requirement that SoC divides.

Main application of the present invention is: adopt the discrete hopfield neural network algorithm, the function of SoC chip is carried out software/hardware divide realization automatically, this method can be used as the key algorithm of SoC software/hardware collaborative design step in the relevant eda tool.Compare with similar algorithms such as ant algorithms with genetic algorithm, this algorithm optimal solution search space dwindles, and difficulty reduces greatly, significantly is better than preceding two kinds of algorithms search time.Simultaneously, software/hardware of the present invention is divided the working time that the result has obviously shortened the SoC program under certain hardware area constraint condition.

Before explaining, some nouns, symbol and the formula that at first use in the define system:

G: a directed acyclic graph, that is the task image of a SoC behaviour, G=(V, E)

V: the task node set that will divide, V={v ₁, v ₂..., v _n}

E: represent between two nodes the directed edge of control or data dependence/correspondence, E={e _Ij, v _i, v _j∈ V, i ≠ j}

The quantity of the task node of N:G, N=|V|

One of P:G is soft, and hardware is divided

V _H: be divided into the node subclass of hardware, V _H V

V _S: be divided into the node subclass of software, V _S V

S (v _i) (or s _i): v _iThe cost that software is realized

H (v _i) (or h _i): v _iHard-wired cost

C (v _i, v _j) (or c _Ij): v _iAnd v _jCommunications cost, if their in different subclass (hardware subset or software subsets).And the communications cost between same node subclass interior nodes is ignored.

c _j: c _JiSum, $c_i=\underset{j=1,j\≠i}{\overset{N}{\mathrm{\Σ}}}{c}_{\mathrm{ji}}$

H _P: divide the hardware cost sum of P, $H_P={\mathrm{\Σ}}_{v_i\∈V_H}{h}_i$

S _P: divide the software cost sum of P, $S_P={\mathrm{\Σ}}_{v_i\∈V_S}{s}_i$

C _P: divide the communications cost sum of P, $C_P={\mathrm{\Σ}}_{v_i\∈V_S,v_j\∈V_H\mathrm{or}{v}_i\∈V_H,v_j\∈V_S}{c}_{\mathrm{if}}$

g _p(V _H, V _S): the entire system cost of dividing the family

f _P(V _H, V _S): the entire system performance of dividing P

Description of drawings

Fig. 1 is a SoC partition problem model synoptic diagram of the present invention.

Fig. 2 is a discrete hopfield neural network structural representation of the present invention.

Embodiment

Further describe thought of the present invention below in conjunction with accompanying drawing.

Fig. 1 is a SoC partition problem model synoptic diagram of the present invention

Definition 1 (division of k road).(V, E), it is exactly the set P={p of searching bunch that the k road is divided for given G= ₁, p ₂..., p _k, satisfy:

$\left\{\begin{array}{c}{p}_i\⊆V,1\≤i\≤k\\ \underset{i=1}{\overset{k}{\mathrm{\∪}}}{p}_i=V\\ p_i\∩p_j=\mathrm{\φ},1\≤i,j\≤k,i\≠j\end{array}\right.---\left(1\right)$

When k=2, P is called as two-way and divides, and it means in goal systems, considers to have only the situation of a software subset (as a general microprocessor) and a hardware subset (as an ASIC or FPGA); When k＞2, P is called as multichannel and divides, and it means in goal systems, considers the situation of a plurality of software subsets (as a plurality of general microprocessors) and a plurality of hardware subset (as a plurality of ASIC or FPGA).Therefore, according to the structure of goal systems, SoC divides and can be divided into two-way division and multichannel division.Because it is the basis that multichannel is divided that two-way is divided, and in the research and development that are widely used in being correlated with, therefore, in the present invention, is not having under the situation of special declaration, divides and generally refer to the two-way division.

Definition 2 (SoC divisions).For given P=(V _H, V _S), V _H∪ V _S=V and V _H∩ V _S=φ, SoC divides the mathematical model that can be expressed as following combinatorial optimization problem:

$\left\{\begin{array}{c}\max f_P(V_H,V_S)\\ s.t.C_{\min }\≤g_p(V_H,V_S)=H_P+S_P+C_P\≤C_{\max }\\ v_i\∈V,e_v\∈E,1\≤i,j\≤n,i\≠j\end{array}\right.---\left(2\right)$

Wherein, C _Min＞0 and C _Max＞0 is respectively the minimum value and the maximal value of the given cost of SoC.

In fact, the SoC partition problem is exactly the optimum point C that how to seek an overall situation.

Fig. 2 is a discrete hopfield neural network structural representation of the present invention

1) neuronic expression

A N node with N neuronic neural network corresponding to task image G, there are a kind of one-to-one relationship in i neuron and node i, have one and import U _iWith output V _iBetween funtcional relationship.Neuronic output valve is determined by following formula:

$V_i=f\left(U_i\right)=\left\{\begin{array}{c}0,\mathrm{if}{U}_i>0\\ 1,\mathrm{if}{U}_i\≤0\end{array}\right.---\left(3\right)$

Wherein, neuron output value V _i=0, expression v _i∈ V _HV _i=1, expression v _i∈ V _S

Be the local optimum problem of avoiding starting condition to cause, neuronic input value should be limited in a certain scope.c _IjMean value U _AvgThe task node that adopts all to link to each other calculates, therefore, and the upper limit U of neuron input _MaxWith lower limit U _MinPress following setting:

$U_{\mathrm{avg}}=\frac{2}{N}{C}_P,$ $U_{\min }=\frac{U_{\mathrm{avg}}}{2},$ $U_{\max }=\frac{U_{\mathrm{avg}}}{2}---\left(4\right)$

$U_i=\left\{\begin{array}{cc}{U}_{\min },\mathrm{if}& U_i<U_{\min }\\ U_{\max },\mathrm{if}& U_i>U_{\max }\end{array}\right.---\left(5\right)$

2) energy function

Corresponding to constraint condition and objective function that SoC divides, the energy function of Hopfield neural network comprises following two parts:

$E=\frac{A}{2}{E}_1+\frac{B}{2}{E}_2---\left(6\right)$

$E_1=\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}{f}_i^2(\underset{j=1}{\overset{N}{\mathrm{\&Sigma;}}}(h_j{V}_i(1-V_j)+s_j(1-V_i)V_j+c_{\mathrm{ij}}(V_i(1-V_j)+(1-V_i)V_j))-C_{\min })---\left(7\right)$

$E_2=-\mathrm{\&alpha;}\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}\left(\underset{j=1,j\&NotEqual;i}{\overset{N}{\mathrm{\&Sigma;}}}({\mathrm{\&beta;}}_i{V}_i(1-V_j)+(1-V_i)V_j)\right)---\left(8\right)$

Wherein, A and B are two positive coefficients, will further determine their value in " 4) operation equation coefficient determine " part.α represents the system architecture acceleration rate, is SoC after software/hardware is divided and the performance fiducial value between pure hard-wired SoC; β i represents the hardware task acceleration rate, is the performance fiducial value of a task node between hardware realization and software/hardware realization, for different task nodes different values is arranged.

Function f in equation (7) _i(x) determine by following formula:

$f_i\left(x\right)=\left\{\begin{array}{c}x+C_{\min }-(h_i+s_i+c_i),\mathrm{ifx}<-C_{\min }+(h_i+s_i+c_i),\\ 0,\mathrm{if}0\&le;x\&le;C_{\max }-C_{\min },\\ x-C_{\max }+(h_i+s_i+c_i),\mathrm{ifx}>C_{\max }-(h_i+s_i+c_i).\end{array}\right.---\left(9\right)$

E ₁Expression constraint condition, E ₂The expression objective function is one of a SoC performance relatively value.Simultaneously, when the SoC performance after software/hardware is divided reaches maximal value, E ₂Get its minimum value.

3) operation equation

I neuronic operation equation is:

$\frac{d{U}_i}{\mathrm{dt}}=-\frac{\&PartialD;E}{\&PartialD;V_i}$

$=-A{f}_i(\underset{j=1}{\overset{N}{\mathrm{\&Sigma;}}}(h_j{V}_i(1-V_j)+s_j(1-V_i)V_j+c_{\mathrm{ij}}(V_i+V_j-2V_i{V}_j))-C_{\min })\&times;$

$\left(\underset{j=1}{\overset{N}{\mathrm{\&Sigma;}}}(h_j(1-V_j)-s_j{V}_j+c_{\mathrm{ij}}(1-2V_j))\right)-\frac{B}{2}\mathrm{\&alpha;}\underset{j=1,j\&NotEqual;1}{\overset{N}{\mathrm{\&Sigma;}}}(({\mathrm{\&beta;}}_i+1)V_j-{\mathrm{\&beta;}}_i)---\left(10\right)$

For further avoiding the local optimum phenomenon occurring and obtain high-quality separating in the limited time, " noise " condition D will be added on the operation equation (10), that is:

$D=\mathrm{\&eta;}(1-2V_j)=\left\{\begin{array}{c}+\mathrm{\&eta;},\mathrm{if}{V}_j=0\\ -\mathrm{\&eta;},\mathrm{if}{V}_j=1\end{array}\right.---\left(11\right)$

But if " noise " condition D is added in the state update rule always, the state of neural network may hypermetamorphosis, to such an extent as to a locally optimal solution all can't obtain.Therefore, as condition [t/T ₀] 〉=when λ satisfies, condition D will be dropped in the operation equation, and wherein [●] is one and rounds operational character, λ=T ₀-(t * T ₀) T _Max-1, T ₀Be a positive coefficient, T _MaxIt is the maximum step number of iteration.

4) the operation equation coefficient determines

Coefficient A is by the mean value of task node cost Determine, that is:

$\stackrel{\&OverBar;}{\mathrm{\&omega;}}=\frac{H_P+S_P}{N}---\left(12\right)$

Coefficient is by U _AvgDetermine, set $A\stackrel{\&OverBar;}{\mathrm{\&omega;}}={\mathrm{KBU}}_{\mathrm{avg}}$ , wherein k is a regulating constant.Generally speaking, get K=1/3, B=1, T ₀=10, T _Max=200, η=U _Avg/ (3+10 * ρ).Here, ρ is the limit generation rate (0＜ρ≤1) of figure G.

α and β _iIt is one group of empirical value.Usually be respectively the random value in scope [1.5,2] and [2,4].

When SoC is realized by software fully, $C_{\min }=\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}{S}_i$ It is minimum cost; When SoC is realized by hardware fully, $C_{\max }=\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}{h}_i$ It is maximum cost.For making scheme practical more, reasonable, be with the minimum cost revision $C_{\min }=2\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}{S}_i.$

Claims (3)

1, a kind of SoC (System-on-a-Chip System on Chip/SoC or SOC (system on a chip)) software/hardware division methods based on discrete hopfield neural network, it is characterized in that: adopt the discrete hopfield neural network algorithm, the function of SoC chip is carried out software/hardware divide realization automatically.Compare with similar algorithms such as ant algorithms with genetic algorithm, this method optimal solution search space dwindles, and difficulty reduces greatly, significantly is better than preceding two kinds of algorithms search time.Simultaneously, the software/hardware of this method is divided the working time that the result has obviously shortened the SoC program under certain hardware area constraint condition.

2, SoC software/hardware division methods according to claim 1, it is characterized in that: this method adopts the describing method of graph theory, the automatic partition problem of SoC software/hardware is converted into a concrete combinatorial optimization problem, introduced a new model of SoC partition problem, this helps to understand the essence that SoC divides.

3, SoC software/hardware division methods according to claim 1, it is characterized in that: this method is according to the characteristics of SoC partition problem, the neuron that has redefined discrete hopfield neural network is represented, energy function, operation equation and coefficient, to satisfy the particular requirement that SoC divides.

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