CN101009528B

CN101009528B - Method and system structure for implementing the synchronized digit sequence TU3/TU12/TU11 mixed low-rank crossing

Info

Publication number: CN101009528B
Application number: CN2006101576593A
Authority: CN
Inventors: 潘剑侠; 孙一翎
Original assignee: Hangzhou Electronic Science and Technology University
Current assignee: Hangzhou Dianzi University; Hangzhou Electronic Science and Technology University
Priority date: 2006-12-14
Filing date: 2006-12-14
Publication date: 2011-04-20
Anticipated expiration: 2026-12-14
Also published as: CN101009528A

Abstract

A method and system structure which realizes the synchronous number sequence TU3/TU12/TU11 amalgamated low order traversing uses data RAM of 2X258 byte to store data, and uses RAM of 2X90 byte to store control word. The address arrangement of the control matrix RAM is, the address of 0-83RAM is used to store control word of 252 bytes TU12/TU11 and back 252 bytes TU3, the control word of front 6 bytes TU3 are stored in the 84-89 of RAM. Every VC4 which constructs the cross module is used to generate three read addresses of said control matrix RAM, they are separately corresponding with TU3, TU12 and TU11, according to different output business style, one address is selected as the read address of the control matrix RAM to read out control word. Compared with current technique, said method and system structure can save two thirds of the control matrix RAM, the read-write times of CPU is also decreased two thirds.

Description

Realize the method and system that Synchronous Digital Hierarchy TU3/TU12/TU11 mixed low-rank intersects

Technical field the present invention relates to the transmission technology of digital information in light/technical field of telecommunications, particularly relate to use time division multiplexing, be the network technology of feature with digital function of exchange.

The raising day by day that the development of background technology modern optical transmission network and service dispatching require makes the low order interlace algorithm capacity of SDH (Synchronous Digital Hierarchy, Synchronous digital hierarchy) equipment increasing.(virtual container is to be used for supporting the message structure that the SDH channel layer connects Virtualcontainer) to VC, is the information terminal of SDH passage.Low order interlace algorithm generally adopts RAM (read-write memory) to realize full intersection.Traditional low order interlace algorithm method writes RAM to the data line of each VC4 among the SDH (261 byte), reads successively according to corresponding 261 control words of intersection gating matrix again.This is for the intersection of low capacity, and needed RAM resource is also fewer.But for jumbo intersection, for example 40G intersects, and chip operation needs the data RAM of 8.6Mbit and the gating matrix RAM of 2.3Mbit in the 155MHz clock, and this has occupied very large tracts of land in chip piece, has also brought the problem of power consumption and chip internal wiring.

In addition, other unit such as cross unit and clock, master control integrate in the SDH equipment now, and the object of CPU management is more and more, and is very high to the disposal ability requirement of CPU.Increasing along with the SDH cross-capacity, the corresponding increase of the capacity of gating matrix, the access time of CPU also significantly improve, for example for the low order interlace algorithm of 40G, CPU needs more than 10 ten thousand times write operation under worst case, and it is very high that this disposal ability for CPU requires.

The low order that the Chinese invention patent application CN1671095A that name is called " a kind of full method of intersecting of Synchronous Digital Hierarchy low order time-division that realizes " discloses a kind of TU3/TU12 of being used for is intersected implementation entirely, preceding 18+63 the data that it need only buffer memory delegation begins just can be intersected and dateout, thereby saved the hardware memory resource, reduced the equipment time-delay.Intersect but the disclosed technical scheme of described CN 1671095A can't realize the mixed low-rank of TU3/TU12/TU11, the quantity of its saving hardware memory resource is still limited.

The summary of the invention the technical problem to be solved in the present invention is to avoid above-mentioned the deficiencies in the prior art part and proposes a kind of method and system of realizing that Synchronous Digital Hierarchy TU3/TU12/TU11 mixed low-rank intersects, the data RAM of using this method and system to need is the same with conventional method, but gating matrix RAM has only 1/3rd of conventional method, thereby has saved the hardware memory resource greatly.

The present invention solves the problems of the technologies described above and is achieved by the following technical solution: propose a kind of method that realizes that Synchronous Digital Hierarchy TU3/TU12/TU11 mixed low-rank intersects, use the low order data RAM store data of 2X258 byte exactly, deposit control word with the gating matrix RAM of 2X90 byte; Each input VC4 produces the low order data RAM write address of 0-257, and each output VC4 produces gating matrix RAM and reads the address; 8 VC4 are multiplexing on a bus, form a Cross module; Wherein, the address arrangement of gating matrix RAM is, deposits the control word of 252 byte TU12/TU11 and the control word of 252 the byte TU3 in back with the 0-83 address ram, and the control word of 6 the byte TU3 in front leaves the 84-89 address of RAM in.

The present invention solves the problems of the technologies described above and can also further realize by coming by the following technical solutions: proposes a kind of system that realizes Synchronous Digital Hierarchy TU3/TU12/TU11 mixed low-rank intersection, being used for the design system clock work is the application-specific integrated circuit (ASIC) of 40G at 155MHz and cross-capacity, Here it is, with the low order data RAM store data of 2X258 byte, deposit control word with the gating matrix RAM of 2X90 byte; The address arrangement of gating matrix RAM is, deposits the control word of 252 byte TU12/TU11 and the control word of 252 the byte TU3 in back with the 0-83 address ram, and the control word of 6 the byte TU3 in front leaves the 84-89 address of RAM in; Multiplexing on a 8bit bus 8 VC4, use 256 VC4,32 buses altogether; The intersection of 256X256 VC4 needs 32 256X8VC4 Cross modules, and each input VC4 produces the low order data RAM write address of a 0-257, each output VC4 produces 3 gating matrix RAM and reads the address, difference corresponding TU3, TU12 and TU11, and according to different outgoing traffic types, select the read address of an address, read control word as gating matrix RAM; Each VC4 has 0-2 and two counters of 0-3, and this two counter is according to output of outgoing traffic type selecting: the TU12/TU3 business is output as the 0-3 counter, and the TU11 business is output as the 0-2 counter; According to the selection output of control word, outgoing traffic type sum counter, the address of reading that produces data RAM.

Compare with prior art, beneficial effect of the present invention is: traditional low order interlace algorithm method writes RAM to the data line of each VC4 among the SDH (261 byte), reads successively according to corresponding 261 control words of intersection gating matrix again.But adopt the inventive method and system then can save nearly 2/3rds gating matrix RAM, the read-write number of times of CPU has also reduced by 2/3rds.The gating matrix RAM of 40G low order interlace algorithm can reduce to 0.77Mbit from 2.3Mbit, and the read-write number of times of CPU is reduced to 40,000 times from more than 100,000 times.

Description of drawings Fig. 1 is the mapping structure of each tributary unit TU3/TU12/TU11, and the Chinese implication of POH is among the figure: path overhead (Path overhead);

Fig. 2 is the schematic diagram of system 256X8 VC4 low order interlace algorithm module of the present invention;

Fig. 3 is the modular system schematic diagram of system 256X256 VC4 low order interlace algorithm of the present invention.

Embodiment further elaborates the present invention below in conjunction with the preferred embodiment shown in the accompanying drawing.The present invention realizes that the data RAM of the method and system needs that Synchronous Digital Hierarchy TU3/TU12/TU11 mixed low-rank intersects is the same with conventional method, but gating matrix RAM has only 1/3rd of conventional method.As shown in Figure 1, investigate TU3, TU12, the mapping structure of TU11 in a VC4 respectively.Therefrom as can be seen:

1) TU3 repeats 86 times with 1-3

2) TU12 repeats 4 times with 1-63

3) TU11 repeats 3 times with 1-84

4) TU3 is Duoed 6 bytes than TU11/TU12

Intersect for simple TU3 or TU12 or TU11, utilize 2 ping-pong rams (write time, another is read), only need the data RAM of a 2X3 byte, 2X63 byte, 2X84 byte respectively.But for the hybrid cross of their combination in any, if TU12 and TU11 mix, because that they have on time slot is overlapping, so can only use 2X258 byte data RAM store data.Can deposit control word with the RAM of a 2X90 byte for gating matrix RAM.Arrange as follows:

0-83RAM deposits the address control word of 252 byte TU12/TU11 and the control word of 252 the byte TU3 in back, and the control word of 6 the byte TU3 in front leaves the 84-89 address of RAM in.Compare with 261 bytes, this method has been saved nearly 2/3rds gating matrix RAM, and the read-write number of times of CPU has also reduced by 2/3rds.The gating matrix RAM of 40G low order interlace algorithm can reduce to 0.77Mbit from 2.3Mbit, and the read-write number of times of CPU is reduced to 40,000 times from more than 100,000 times.

Consider ASIC (application-specific integrated circuit (ASIC), application specific IC) She Ji concrete condition, be operated in 155MHz and 40G (256 VC4) cross-capacity is an example with the system clock of chip, can be multiplexing on a 8bit bus 8 VC4,256 VC4 need 32 buses altogether.Fig. 2 is the Cross module schematic diagram of 256X8VC4, and the intersection of 256X256VC4 needs 32 256X8VC4 Cross modules, as shown in Figure 3.

In Fig. 2, each input VC4 produces the low order data RAM write address of a 0-257.Each output VC4 produces 3 gating matrix RAM and reads the address, and corresponding TU3, TU12 and TU11 according to different outgoing traffic types, select the read address of an address as gating matrix RAM respectively, read control word.Each VC4 has 2 counters: 0-2 counter and 0-3 counter.Counter is according to the professional output of output: TU12/TU3 of outgoing traffic type selecting 0-3 counter, the professional output of TU11 0-2 counter.According to the selection output of control word, outgoing traffic type sum counter, the address of reading that produces data RAM:

If type of service is TU12/TU3, counter is 0, and control word is the address of reading of data RAM; Counter is 1, and control word adds 63 addresses of reading for data RAM; Counter is 2, and control word adds 126 addresses of reading for data RAM; Counter is 3, and control word adds 189 addresses of reading for data RAM.

If type of service is TU11, counter is 0, and control word is the address of reading of data RAM; Counter is 1, and control word adds 84 addresses of reading for data RAM; Counter is 2, and control word adds 168 addresses of reading for data RAM.

It can be unit for unit or with TUG2 with TUG3 (tributary unit group, Tributary unit group) that type of service is selected, if be unit with TUG3, each VC4 only needs the selection of 3 slot cycles; If with TUG2 is unit, each VC4 is with the selection of 21 slot cycles.The generation of address and service selection signal or to be that 8 VC4 are earlier multiplexing produce again perhaps produces multiplexing more earlier.Fig. 2 is multiplexing after producing earlier.

In Fig. 3, the module among Fig. 2 is duplicated 32 parts, just become the intersection of 256X256VC4.The control of the write address of each module and incoming traffic type can be shared among Fig. 3.

Claims

1. method that realizes that Synchronous Digital Hierarchy TU3/TU12/TU11 mixed low-rank intersects is characterized in that:

With the low order data RAM store data of 2X258 byte, deposit control word with the gating matrix RAM of 2X90 byte; Each input VC4 produces the low order data RAM write address of 0-257, and each output VC4 produces gating matrix RAM and reads the address; 8 VC4 are multiplexing on a bus, form a Cross module;

The address arrangement of gating matrix RAM is, deposits the control word of 252 byte TU12/TU11 and the control word of 252 the byte TU3 in back with the 0-83RAM address, and the control word of 6 the byte TU3 in front leaves the 84-89 address of RAM in;

The address of reading that utilizes each VC4 that constitutes Cross module to produce 3 described gating matrix RAM, difference corresponding TU3, TU12 and TU11, and, select the read address of an address as gating matrix RAM according to different outgoing traffic types, read control word.

2. system that realizes that Synchronous Digital Hierarchy TU3/TU12/TU11 mixed low-rank intersects, being used for the design system clock work is the application-specific integrated circuit (ASIC) of 40G at 155MHz and cross-capacity, it is characterized in that:

With the low order data RAM store data of 2X258 byte, deposit control word with the gating matrix RAM of 2X90 byte; The address arrangement of gating matrix RAM is, deposits the control word of 252 byte TU12/TU11 and the control word of 252 the byte TU3 in back with the 0-83RAM address, and the control word of 6 the byte TU3 in front leaves the 84-89 address of RAM in;

Multiplexing on a 8bit bus 8 VC4, use 256 VC4,32 buses altogether; The intersection of 256X256VC4 needs 32 256X8VC4 Cross modules, and each input VC4 produces the low order data RAM write address of a 0-257, each output VC4 produces 3 gating matrix RAM and reads the address, difference corresponding TU3, TU12 and TU11, and according to different outgoing traffic types, select the read address of an address, read control word as gating matrix RAM; Each VC4 has 0-2 and two counters of 0-3, and this two counter is according to output of outgoing traffic type selecting: the TU12/TU3 business is output as the 0-3 counter, and the TU11 business is output as the 0-2 counter; According to the selection output of control word, outgoing traffic type sum counter, the address of reading that produces data RAM.

3. according to the system of the described realization Synchronous Digital Hierarchy of claim 2 TU3/TU12/TU11 mixed low-rank intersection, it is characterized in that:

Determine that gating matrix RAM reads the address and is, if type of service is TU12/TU3, counter is 0, and control word is the address of reading of data RAM; Counter is 1, and control word adds 63 addresses of reading for data RAM; Counter is 2, and the system word adds 126 addresses of reading for data RAM; Counter is 3, and control word adds 189 addresses of reading for data RAM; If type of service is TU11, counter is 0, and control word is the address of reading of data RAM; Counter is 1, and control word adds 84 addresses of reading for data RAM; Counter is 2, and control word adds 168 addresses of reading for data RAM.

4. according to the system of the described realization Synchronous Digital Hierarchy of claim 2 TU3/TU12/TU11 mixed low-rank intersection, it is characterized in that:

It is unit that type of service is selected with TUG3, and each VC4 needs the selection of 3 slot cycles; The generation of address and service selection signal or to be that 8 VC4 are earlier multiplexing produce again perhaps produces multiplexing more earlier.

5. according to the system of the described realization Synchronous Digital Hierarchy of claim 2 TU3/TU12/TU11 mixed low-rank intersection, it is characterized in that:

It is unit that type of service is selected with TUG2, and each VC4 selects with 21 slot cycle ground; The generation of address and service selection signal or to be that 8 VC4 are earlier multiplexing produce again perhaps produces multiplexing more earlier.