CN101008883A

CN101008883A - Non-volatile semiconductor large capacity image memory

Info

Publication number: CN101008883A
Application number: CN 200610016570
Authority: CN
Inventors: 魏仲慧; 李敏洁; 何昕; 王军; 刘岩俊
Original assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Current assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority date: 2006-01-26
Filing date: 2006-01-26
Publication date: 2007-08-01

Abstract

This invention relates to one non-loss semiconductor large volume image memory in remote sensor technique field, which comprises image data write interface, image data backup module, memory array, image data output module, memory controller, wherein, the image data write interface and outer camera machine are connected with output end connected to input end of memory array and to image data backup module input end; the image data backup module output end and memory array input end are connected.

Description

A kind of non-volatile semiconductor large capacity image memory

(1) technical field

The invention belongs to a kind of non-volatile semiconductor large capacity image storage apparatus that is applied in the remote sensing survey technical field.

(2) background technology

In the remote sensing survey technology, no matter be spaceborne or the aerial remote sensing measurement, a large amount of digital pictures that the digital high-speed video camera is taken all need jumbo memory device, the digital picture that storage remote sensing survey real-time obtains.In the memory device in modern times, semiconductor memory has progressively replaced magnetic tape station, becomes the mainstream technology of memory device in the remote sensing survey technology.The storage medium of semiconductor large capacity storer mainly contains dynamic RAM (DRAM) and flash memory (FLASH), yet the work of this respect belongs to the high-tech category, and developed country all strictly blocks this, and we are difficult to find relevant technical information.

Be that Changchun Institute of Optics, Fine Mechanics and Physics, CAS adopts the semiconductor large capacity image memory of dynamic RAM (DRAM) as storage medium with the most approaching prior art of the present invention at home, applied for national defence patent in calendar year 2001, the patent No. is: 01128228.2, as shown in Figure 1, comprise that view data writes incoming interface 1, image memory bank 2, controller 3, data transmission interface 4, control computer interface 5, address generator 6, data bus 7, address bus 8, control bus 9, control computer 10; Control computer 10 is charge centers of this semiconductor large capacity storer, and under its control, semiconductor large capacity image memory is finished the work of self check, shooting and three kinds of patterns of transmission, and the subject matter of its existence is: canned data will be lost after the power down.

(3) summary of the invention

In order to overcome the shortcoming that prior art exists, the objective of the invention is to solve the problem that canned data is not lost after the power down, adopt flash memory (FLASH) as storage medium, designed non-volatile semiconductor large capacity image memory.

The technical problem to be solved in the present invention is: provide a kind of non-volatile semiconductor large capacity image memory, to realize storing image data real-time.The technical scheme of technical solution problem is: under the control of Memory Controller, the great amount of images data that ccd video camera is taken are write incoming interface through data, real-time storage is in memory array, afterwards, Memory Controller produces certain time sequence, with being stored in view data in the memory array, be transferred to processing and analysis that the view data process computer carries out view data through data outputting module.

Detailed content of the present invention such as Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 and shown in Figure 7, comprise that view data writes incoming interface 11, view data backup module 12, memory array 13, view data output module 14, Memory Controller 15, control bus 16, address bus 17 and data bus 18, wherein view data is write incoming interface 11 as shown in Figure 3, comprises the buffer 20 of Camera Link interface chip 19, four The parallel combined; View data backup module 12 comprises static RAM (SRAM) 21 of four The parallel combined and controller buffer 22, address buffer 23 as shown in Figure 4; Memory array 13 comprises impact damper 25, controller buffer 26, address buffer 27, data buffer 28 and eight storer submodules 24 as shown in Figure 5, and these eight storer submodules 24 constitute eight level production lines; Each storer submodule 24 comprises four flash chips 29 as shown in Figure 6; In view data output module 14, adopt USB (universal serial bus) (USB) interface, give the view data process computer image data transmission; Memory Controller 15 comprises single-chip microcomputer 30 and field programmable gate array (FPGA) 31,32 as shown in Figure 7, is the control maincenter of system, produces the needed whole sequential of system works.

The input end that view data is write incoming interface 11 is connected with outside ccd video camera, output terminal is connected with the input end of memory array 13, with image data storage to memory array 13, also the input end with view data backup module 12 is connected, and view data is backuped in the view data backup module 12; The output terminal of view data backup module 12 is connected with the input end of memory array 13, with the backup image data storage in memory array 13, the input end of memory array 13 is accepted the view data that view data is write the backup of the view data of incoming interface 11 or view data backup module 12, the output terminal of memory array 13 is connected with the input end of view data output module 14, be input in the view data output module 14 and go being stored in view data in the memory array 13, the output terminal of view data output module 14 is connected with the input end of the view data process computer of outside, and view data is sent to processing and the analysis that the view data process computer carries out view data; Memory Controller 15 is write incoming interface 11, view data backup module 12, memory array 13 and view data output module 14 with view data respectively by control bus 16 and is linked to each other, Memory Controller 15 links to each other with view data backup module 12, memory array 13 respectively by address bus 17, and Memory Controller 15 is write incoming interface 11, memory array 13 and view data output module 14 with view data respectively by its data bus 18 and linked to each other.

View data is write incoming interface 11 as shown in Figure 3, wherein the input end of Camera Link interface chip 19 is connected with outside ccd video camera, output terminal is connected with the input end of four parallel impact dampers 20, the output terminal of four parallel impact dampers 20 is connected with memory array 13 with view data backup module 12 respectively, and control bus 16 is connected with four parallel impact dampers 20 respectively.

View data backup module 12, as shown in Figure 4, wherein the input end of address buffer 23 links to each other with address bus 17, output terminal is connected with the address end of four parallel static RAMs (SRAM) 21, the address information on the address bus 17 is transported to the address port of four parallel static RAMs (SRAM) 21; The input end of controller buffer 22 links to each other with control bus 16, output terminal is connected with the control end of four parallel static RAMs (SRAM) 21, the control information on the control bus 16 is transported to the control end of four parallel static RAMs (SRAM) 21; The data terminal of four parallel static RAMs (SRAM) 21 is connected with the data output end that view data is write incoming interface 11, and also the data input pin with memory array 13 is connected, and view data is backed up and the view data that backs up is deposited in the memory array 13.

Memory array 13 as shown in Figure 5, wherein the input end of impact damper 25 is write the data terminal of incoming interface 11 with view data respectively, the data terminal of view data backup module 12 is connected, output terminal is connected with the data terminal of eight storer submodules 24, it is the data channel that view data is write incoming interface 11, view data backup module 12 and storer submodule 24, the input end of controller buffer 26 is connected with control bus 16, and output terminal is connected with the control port of eight storer submodules 24; The input end of address buffer 27 is connected with address bus 17, output terminal is connected with the data terminal of eight storer submodules 24, the input end of data buffer 28 is connected with data bus 18, output terminal is connected with the data terminal of eight storer submodules 24, and Memory Controller 15 and memory array 13 can be carried out the exchange of information such as state and order by data buffer 28; The output terminal of memory array 13 is connected with the input end of view data output module 14, will be stored in image data transmission in the memory array 13 in view data output module 14.

In the storer submodule 24 as shown in Figure 6, comprise four parallel flash chips 29, the data terminal of storer submodule 24 is connected with the output terminal of address buffer 27, the output terminal of data buffer 28, the output terminal of impact damper 25, the input end of view data output module 14 respectively, and the control end of view data output module 14 is connected with the output terminal of controller buffer.

Memory Controller 15 as shown in Figure 7, the data terminal of single-chip microcomputer 30 is connected with the I/O end of field programmable gate array (FPGA) 31, the output terminal of field programmable gate array (FPGA) 31 is connected with the input end of field programmable gate array (FPGA) 32.

Field programmable gate array (FPGA) 31 links to each other with control bus 16, address bus 17, data bus 18 respectively, sends the control signal that view data is write incoming interface 11, and accepts the status signal that view data is write incoming interface 11 by data bus 18; Send the control signal and the address signal of view data backup submodule 12; Field programmable gate array (FPGA) 32 is connected with control bus 16, address bus 17, data bus 18 respectively, send control signal, address signal and the command signal of memory array 13, and accept the status signal of memory array 13 by data bus 18; Send the control signal of view data output module 14, and by the status signal of data bus 18 acceptance patterns as data outputting module 14.

The principle of work explanation:

Under Memory Controller 15 controls, finish buffer memory, backup, storage and the output of view data, and read the state of storer, its work is monitored.Under the control of Memory Controller 15, with view data in a certain order buffer memory to view data write incoming interface 11, write in the incoming interface 11 in the data in the buffer 20 in reads image data, view data is write respectively in view data backup module 12 and the memory array 13.If find mistake when storing image data, the corresponding data that need to make mistakes are carried out reprogramming, and this must be with the writing data into memory array in the view data backup module 12.Afterwards, Memory Controller 15 produces the certain time sequence signal, the view data of memory array 13 is read, and pass to the view data process computer by view data output module 14, carries out recovery, demonstration and the processing of image.

Good effect:

The non-volatile semiconductor large capacity image memory biggest advantage is that canned data is not lost after the power down, also have low in energy consumption, reliability is high, volume is little, in light weight, advantage such as cost performance preferably, owing to adopted USB (universal serial bus) (USB) interface, easy for installation, for the image data storage equipment of space flight, aviation field provides new solution.

(4) description of drawings

Fig. 1 is the structured flowchart of prior art, Fig. 2 is a structured flowchart of the present invention, Fig. 3 is the structured flowchart that view data is write incoming interface 11, Fig. 4 is the structured flowchart of view data backup module 12, Fig. 5 is the structured flowchart of memory array 13, Fig. 6 is the structured flowchart of storer submodule 24, and Fig. 7 is the structured flowchart of Memory Controller 15.

(5) embodiment

The present invention implements by structure shown in Figure 2, and wherein the CameraLink interface chip 19 write in the incoming interface 11 of view data is selected DS90CR286 for use, and buffer 20 is selected first in first out storage (FIFO) IDT7205 for use.

Four parallel static RAMs (SRAM) 21 in the view data backup module 12 are selected IDT71256 for use, are used for carrying out data backup; Controller buffer 22 and address buffer 23 are selected 74HC244 for use.

Flash chip 29 in the storer submodule 24 is selected K9F1G08U0A for use, and whole storage space is made up of 32 such chips; Impact damper 25 is selected 74LVC244 for use, and data buffer 28 is selected 74LVC245 for use, and controller buffer 26 and address buffer 27 are selected 741LVC244 for use.

Single-chip microcomputer 30 in the Memory Controller 15 is selected AT89C51 for use, and field programmable gate array (FPGA) 31 and 32 is selected XC2S200 for use.

Data outputting module 14 mainly is made up of USB (universal serial bus) (USB) 2.0, interface chip CY7C68013.

Claims

1, a kind of non-volatile semiconductor large capacity image memory, comprise that view data writes incoming interface, control bus, address bus and data bus, it is characterized in that also comprising view data backup module (12), memory array (13), view data output module (14), Memory Controller (15); The input end that view data is write incoming interface (11) is connected with outside ccd video camera, output terminal is connected with the input end of memory array (13), also the input end with view data backup module (12) is connected, the output terminal of view data backup module (12) is connected with the input end of memory array (13), the output terminal of memory array (13) is connected with the input end of view data output module (14), and the output terminal of view data output module (14) is connected with the input end of the view data process computer of outside; Memory Controller (15) is write incoming interface (11), view data backup module (12), memory array (13) and view data output module (14) with view data respectively by control bus (16) and is linked to each other, Memory Controller (15) links to each other with view data backup module (12), memory array (13) respectively by address bus (17), and Memory Controller (15) is write incoming interface (11), memory array (13) and view data output module (14) with view data respectively by its data bus (18) and linked to each other.

2, by the described a kind of non-volatile semiconductor large capacity image memory of claim 1, the input end that it is characterized in that address buffer (23) in the view data backup module (12) links to each other with address bus (17), output terminal is connected with the address end of four parallel static RAMs (SRAM) (21), the input end of controller buffer (22) links to each other with control bus (16), output terminal is connected with the control end of four parallel static RAM SRAM (21), the data terminal of four parallel static RAM SRAM (21) is connected with the data output end that view data is write incoming interface (11), and also is connected with the data input pin of memory array (13).

3, by the described a kind of non-volatile semiconductor large capacity image memory of claim 1, the input end that it is characterized in that impact damper (25) in the memory array (13) is write the data terminal of incoming interface (11), the data terminal of view data backup module (12), the data terminal of view data output module (14) with view data respectively and is connected, output terminal is connected with the data terminal of eight parallel storer submodules (24), the input end of controller buffer (26) is connected with control bus (16), and output terminal is connected with the control port of eight reservoir submodules (24); The input end of address buffer (27) is connected with address bus (17), output terminal is connected with the data terminal of eight parallel storer submodules (24), the input end of data buffer (28) is connected with data bus (18), output terminal is connected with the data terminal of eight parallel storer submodules (24), and the output terminal of memory array (13) is connected with the input end of view data output module (14).

4, by the described a kind of non-volatile semiconductor large capacity image memory of claim 1, it is characterized in that in the Memory Controller (15), the data terminal of single-chip microcomputer (30) is connected with the I/O end of on-site programmable gate array FPGA (31), the output terminal of on-site programmable gate array FPGA (31) is connected with the input end of on-site programmable gate array FPGA (32), on-site programmable gate array FPGA (31) respectively and control bus (16), address bus (17), data bus (18) links to each other, and on-site programmable gate array FPGA (32) respectively and control bus (16), address bus (17), data bus (18) connects.