CN102117342A - Peripheral component interconnect (PCI) Express bus-based multiband infrared image real-time acquisition system and method - Google Patents
Peripheral component interconnect (PCI) Express bus-based multiband infrared image real-time acquisition system and method Download PDFInfo
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Abstract
The invention discloses a peripheral component interconnect (PCI) Express-based multiband infrared image real-time acquisition system and a PCI Express-based multiband infrared image real-time acquisition method. The system comprises an embedded host with a PCI Express x8 channel and a real-time image acquisition card, wherein the real-time image acquisition card comprises a field programmable gate array (FPGA) chip, a high-speed caching double data rate 2 synchronous dynamic random access memory (DDR2SDRAM), differential I/O interfaces connected with a multiband infrared detector and a PCI Express x8 card insertion part. The acquisition method for the system comprises that: the FPGA chip of the acquisition card simultaneously reads multiband infrared image data from the differential I/O interfaces, caches the read multiband infrared image data into the DDR2SDRAM, performs PCI Express bus bandwidth allocation after finishing acquiring an image frame, transmitting the data of the image frame to the host by a PCI Express x8 bus for real-time display and storage, and simultaneously caches the acquired data of the next image frame. The invention has the advantage of integrating a plurality of infrared band data discrete acquisition systems to form the multipath, high-speed, synchronous and real-time acquisition system which is miniature and highly portable.
Description
Technical field
The present invention relates to acquisition technology, be particularly related to and a kind ofly carry out real-time data acquisition and storage system and method between infrared multiband infrared eye and the computing machine based on PCI Express bus, it is applicable to multiband infrared image emerging system and the synchronous real-time display system of multi-band image.
Background technology
Infrared multiband detection system mainly is made up of infrared eye and the real-time acquisition process platform of infrared signal two parts of a plurality of wave bands.Along with the direction of infrared acquisition means towards big face battle array, high frame speed, multiband, real-time detection develops, the also sharp increase of data volume that the image data acquiring system need transmit and handle, and have higher requirement in the collection aspect to the real-time collection of data and multi-wavelength data the time.Traditional infrared image capturing system is based on the image pick-up card of PCI or USB mostly.Because pci bus is a parallel bus, extendability is relatively poor, and when connecting a plurality of equipment, the effective bandwidth of bus will significantly reduce, and transfer rate is slack-off; And be 60MBps based on the theoretic hump speed of the infrared image capturing system of USB, only be applicable to the application scenario that data transfer rate is lower.PCI Express is as the I/O bus standard of a new generation, and is different with the conventional bus structure, and it has adopted point-to-point mode connected in series, solved conventional bus and taken the problem low with bus efficiency.And its regulation bus can have the plurality of specifications of 1 to 32 passage, and the one-way transmission speed of every passage can reach 2.5Gbps.Deficiency in view of traditional in the past infrared image capturing system, can improve the message transmission rate of system greatly based on the data acquisition system (DAS) of PCI Express bus, be to carry out effective solution route that real-time infrared image that big face battle array, high frame frequency, multiband survey is gathered.
On the other hand, the data message that the multi-band image emerging system detects for the multiband infrared eye, need while image data and storage data in time, be that multiwave view data need be aimed in time, could move the real time fusion technology of multi-band image on this basis.A solution is to divide other to gather storage to multiwave data, and then aggregation process.But this scheme will increase the time alignment between multidetector and the difficulty of time-delay control greatly, and the growth that system power dissipation and cost aspect can be at double, also be unfavorable for the miniaturization and the portable requirement of system.PCI Express bus is supported the mode of multichannel data independent transmission, and does not disturb mutually between the passage.Adopt multichannel PCI Express bus to carry out data acquisition, gather when realizing the multiband detector data and have natural advantage aspect portable controlling cost, reduce power consumption, raising system.
In a word, exploitation and development are based on the data acquisition system (DAS) of hyperchannel PCI Express bus, be the multiband that faces the future development, at a high speed, the application requirements of the data acquisition of the infrared detection system of big face battle array and giving birth to, and, established solid foundation for realizing the development of multiband real-time infrared image integration technology.
Summary of the invention
The objective of the invention is to propose a kind of multiband infrared image real-time acquisition device and method based on PCI Express bus, realize the high speed of multiband infrared image, gather in real time and show simultaneously, satisfy the application demand of high data throughput and real-time in the infrared detection system of existing a plurality of wave band, big array.
Hardware unit of the present invention is made up of bus run and the capture card of main frame, PCI Express x8, and capture card comprises three difference I/O interfaces, FPGA control chips and is connected with the memory module of DDR2SDRAM memory bar, and hardware connects as shown in Figure 1.
The configuration requirement of described main frame is: the processor of outfit is Pentiune 4 or the above CPU of Celeron series 1.0GHz, operating system version be Windows2000 the above version of Windows XP SP2, memory bar is the above configuration of DDR2SDRAM 667MHz, 512M, hard disk is the above Primary Hard Drive of 40G SATA, must comprise the interface unit of supporting PCI Express x8 bus run; For miniaturization and portable demand, can adopt the embedded computer module to realize the repertoire of main frame, for example: the COM Express series embedded computer module of Kontron company exploitation, the size that 95mm * 125mm is only arranged, parts and host interface such as the required CPU of integrated main frame mainboard, north bridge chips, South Bridge chip, internal memory.
The bus run of described PCI Express x8 comprises connector (being slot) and two parts of golden finger of PCI Express x8, and the data path that is used to set up between main frame and the capture card is connected with hardware; The slot of described PCI Express x8 is placed on the main frame, the industrial standard (as: PCI ExpressTM card electromechanical specification 1.0a) that this slot accord with PCI SIG tissue provides; The golden finger of described PCI Express x8 is installed on the capture card, must meet identical definition and standard with the slot on the main frame.
Each hardware ingredient need satisfy on the described capture card: described FPGA must comprise stone or soft nuclear (as: Virtex-5LXT, SXT, the FXT Series FPGA that Xilinx company produces of a PCI Express bus protocol, include stone and the Rocket I/O high-speed transceiver GTP of PCI Express LogiCORE IP Endpoim Block, thereby can realize PCI Express bus protocol standard); The clock that described difference I/O interface connects need satisfy the requirement (clock such as detector input data is 10MHz, and the clock frequency that then connects the difference I/O interface of this detector must be not less than 10Mhz) of detector input clock; The memory bar of described DDR2SDRAM memory module must satisfy and is DDR2667MHz, configuration more than the 256MHz.
When described acquisition system is carried out collecting work: earlier send acquisition instructions to capture card by the bus run of main frame by PCI Express x8, after the FPGA of capture card received instruction, control difference I/O interface received the view data of multiband detector among the DDR2SDRAM of capture card and carries out buffer memory; After the current image frame data buffering for the treatment of all detectors is finished, FPGA control sends the present image frame data of buffer memory among the DDR2SDRAM to main frame by PCI Express x8 bus, and meanwhile capture card also will carry out the collection and the buffer memory work of next image frame data constantly according to aforesaid operations; Treat main frame after bus reception image frame data is finished, main frame carries out showing synchronously in real time and the image storage of multiband infrared image.
Data acquisition flow of the present invention is:
Step 4, the DDR2 SDRAM control module on the capture card among the FPGA writes the data that receive in the FIFO buffer cell in the ping-pong buffer of DDR2SDRAM;
Step 6, after the equal buffer memory of current frame image data for the treatment of the multiband detector is finished, DDR2SDRAM control module on the capture card among the FPGA will buffer memory be good in DDR2SDRAM image frame data send the DDR2-PCIE buffer memory FIFO of distributing to, meanwhile FPGA also will carry out next collection buffer memory work of image frame data constantly in the ping-pong buffer of DDR2SDRAM;
Step 7, the FIFO buffer cell on the capture card among the FPGA is transferred to the image frame data of DDR2-PCIE buffer memory FIFO by the PCI Express bus control unit among the FPGA;
Step 8, PCI Express bus control unit on the capture card among the FPGA with image frame data according to the DMA data-transmission mode, on the bus run of PCI Express x8, send to main frame, and all upload in the image frame data of multiband detector and send to interrupt to main frame with the PIO pattern after finishing;
Step 9, main frame receive after the look-at-me that capture card sends by the PIO pattern on PCI Express bus, and main frame is read the data of picture frame, carry out showing synchronously in real time and operation that image is stored of multiband infrared image;
Step 10, when gathering end, capture card transmits the view data that current detector detects to main frame, and no longer carry out the collecting work of next time chart picture frame, and after finishing, the multiband infrared image data transmission notifies main frame in the mode of interrupting, main frame carries out the demonstration of infrared image of a plurality of wave bands and the operation of image storage then, closes the operational module of whole acquisition system at last.
The technical characterictic of the present invention aspect hardware unit is: the first, and adopt the bus interface of the PCI Express of x8 passage to carry out data transmission and communicate by letter between capture card and the main frame.PCI Express bus is the bus of carrying out point-to-point serial communication between two equipment, can support the duplex channel of x1, x2, x4, x8, x16 on bus links, and the speed that data send and receive on each duplex channel can reach 2.5Gbps.Adopted the PCI Express bus of x8 passage among the present invention, theoretic data rate can reach 20Gbps (being 2.5GB/s), compare the traditional use pci bus and the data collection and transfering system of usb bus, message transmission rate increases greatly, is more suitable for the development and application that the data of mass data transfers and multidetector are imported simultaneously.
The second, described capture card carries out the collection and the transmission of view data to the signal of the infrared eye of three wave bands, and the requirement of mating the data-interface and the transmission time sequence of different-waveband infrared eye flexibly by the characteristics of utilization difference I/O interface.The pairing multiband infrared eye of described acquisition system is respectively short-wave infrared detector, medium wave infrared eye and Long Wave Infrared Probe, and they are responsible for surveying the infrared image in the own wavelength band respectively.Use the difference I/O interface of LVDS J30-51 to be connected between capture card and the multiband infrared eye, can mate the data-interface of three kinds of infrared eyes that may have different separately formal definitions flexibly.
The 3rd, described main frame adopts the embedded computer module, and size is 95mm * 125mm only, has reduced the weight and volume of system greatly, makes acquisition system small and exquisite, portable, and can play a role in limited space.
Collecting method of the present invention is mainly realized by the functional unit in the FPGA on the capture card.Functional unit in this FPGA mainly comprises PCI Express bus control unit, flow control and channel scheduling unit, DDR2SDRAM control module, difference I/O interface unit and four parts of FIFO buffer cell, as shown in Figure 3.The major technique of this collecting method is characterised in that:
The first, comprise the integrated end points design of PCI Express in the described PCI Express bus control unit, and will order with data and separate transmission with different patterns.On PCI Express bus, order is with the PIO mode transfer, and data are with the DMA mode transfer.
The second, described flow control and channel scheduling unit also carry out bus bandwidth to three road transmission of infrared eye data on the PCIExpress bus and distribute and flow control.The present invention uses the VC pseudo channel technology of PCI Express bus, by being the VC pseudo channel of the distribution of flows varying number of different detectors, thereby distinguish data by the time amount of bandwidth; Described control module is also carried out flow control to each VC pseudo channel, and these VC pseudo channel buffer zones are corresponded on the FIFO of identical size, thereby guarantees the load balancing between each VC pseudo channel.
The present invention has following three main advantages:
One, message transmission rate height, throughput of system are big.Because capture card passes through the PCI Express bus of x8 passage when main frame transmission data, according to protocol specification, its x1 passage one-way transmission bandwidth can reach 250MB/s in theory, x8 passage one-way transmission bandwidth can reach 2GB/s, and in the reality test, x1 passage one-way transmission speed is 120MB/s, and x8 passage one-way transmission speed can reach 900MB/s.
Two, real-time synchronous transmission.In the view data of three wave band infrared eyes in transmission course, FPGA is by FIFO buffering, DDR2 SDRAM ping-pong buffer and PCI Express VC pseudo channel technology, the data of multiband detector can be carried out at a high speed, synchronous, real-time transmission.
Three, small and exquisite, concentrated, portable.Main frame among the present invention adopts the embedded computer module, has reduced the size and the weight of system greatly, is easy to carry; The acquisition system of a plurality of infrared band detectors that capture card among the present invention is integrated, the independent of each infrared band detector gathered and Presentation Function, unified being integrated on a capture card circuit and the main frame, help carrying out ambulant site test and concentrated data processing, and conveniently carry out the unified maintenance work of acquisition system.
Description of drawings
Fig. 1 is based on the image capturing system structural drawing of PCI Express.
Inner each logic function unit structural representation of Fig. 2 FPGA.
Fig. 3 PCI Express bus control unit structural representation.
The algorithm flow chart of Fig. 4 multiband infrared image acquisition system.
Embodiment
With reference to the accompanying drawings specific implementation method of the present invention is further described in detail below.Fig. 1 is based on the image capturing system structural drawing of PCI Express.Hardware unit of the present invention is: a main frame and a capture card that has PCI Express x8 golden finger that has x8 passage PCI Express slot, contain on the capture card difference I/O interface, of three J30-51 standards embedded FPGA and memory module that is connected to the DDR2SDRAM memory bar of PCI Express stone.
Described main frame adopts the embedded computer module of the ETXexpress-PC of Kontron company, size dimension is 95mm * 125mm, concrete configuration is: the CPU of Intel (R) Core (TM) 2 Duo SL9400 (1.86GHz), the internal memory of 2G DDR3SDRAM 1067MHz, the hard disk of SATA 250GB is equipped with the operating system of Windows XP Professional SP2.Main frame is responsible for sending collection " beginning " instruction and is gathered " end " instruction, and the control capture card carries out collecting work and finishes collecting work; And main frame corresponds to the real-time demonstration of carrying out each wave band infrared image on a plurality of windows respectively with capture card image transmitted frame data and shows simultaneously.Functional unit on the main frame is divided into driver and two parts of application program.Driver is responsible for communicating and data transmission with capture card, and application program is responsible for the data of the multiband infrared eye that the capture card transmission is next and is carried out showing in real time, synchronously and the image storage of independent window.
The clock frequency of described PCI Express x8 channel bus is 200MHz, and bandwidth is 64bit.The PCIExpress bus provides high speed, high-performance, point-to-point, differential signaling link for interconnect equipment, and has adopted 2.5Gbps high-speed-differential transceiver on each link.Because Physical layer has adopted the 8b/10b coding in PCI Express 1.0 protocol specifications, therefore theoretic data rate can reach 2.5Gbps * 80%=2.0Gbps (being 256MB/s).Because packet has added certain redundant data for the data of transmission in the agreement in generative process, and main frame to PCI Express bus exist interrupt response and etc. pending time-delay, thereby actually record single pass data transmission rate and be about 120MB/s, the transfer rate of PCI Express x8 passage can reach 900MB/s, is enough to satisfy the requirement of data transmission of extensive, the two-forty of multichannel infrared picture data.
Use the difference I/O interface of LVDS J30-51 to be connected between described capture card and the multiband infrared eye, can mate the data-interface that three kinds of detectors have different formal definitions separately.The infrared eye of three wave bands that are connected with difference I/O mouth on the capture card among the present invention is respectively: 320 * 240 yuan of HgCdTe (mercury cadmium telluride) LONG WAVE INFRARED focus planardetector of being responsible for long wave 8-12um band detection, be responsible for 256 * 320 yuan of HgCdTe (mercury cadmium telluride) medium wave infrared focal plane detector of medium wave 3-5um band detection, and 64 * 64 yuan of InGaAs of responsible shortwave 1-3um band detection (indium gallium arsenic) short-wave infrared focus planardetector.
Fpga chip is the core control part in the real-time capture card of multiband infrared image on the described capture card.Fpga chip among the present invention adopts the FPGA of the Virtex-5LX50T model of Xilinx company, chip internal the is integrated integrated endpoint module of PCI Express (as the stone resource of PCI Express) of a kind of LogiCORE of being called as IP Endpoint Block and the GTP high data rate transceiver (can realize the high speed data transfer of 2.5Gbps and the 8B/10B encoding and decoding of PCI Express protocol specification, this part can be used as the electric physical layer transceiver module on the PCI Express bus) of Rocket IO.Fpga chip on the capture card powers on by the 12V power lead on the PCI Express x8 golden finger, and this voltage is converted to 5V voltage through the voltage transformation module on the collection plate and powers to fpga chip.Used reference clock is that the clock crystal oscillator by 100MHz provides.This fpga chip is the main supporting body of capture card part in the whole collection algorithm, and it includes a plurality of functional units of capture card algorithm part, and specifically as shown in Figure 2, the back is described in detail according to Fig. 2.
Described DDR2SDRAM adopts the memory bar of 800MHz, 256MB, and data bit width is 64bit, and clock is provided by the clock crystal oscillator of 200MHz, and read-write speed theoretical value can reach 6.25GB/s, and the actual data rate that records is 2.5GB/s.In the present invention, DDR2 SDRAM distributes a pair of ping-pong buffer for each wave band infrared eye, and the size of each buffer zone is the size of a picture frame.In some application scenarios, sometimes can transmit to main frame again after the image data frame of buffer memory a period of time, thereby a pair of ping-pong buffer district of corresponding time span need be provided each wave band infrared eye, this also is a reason of selecting DDR2 sdram memory bar rather than DDR2 sdram memory chip or Flash chip for use.Because same memory bank can be equipped with the memory bar of different capabilities size in hardware system, according to varying in size of the time length difference of data cached frame in the system, data volume, can be adjusted into the memory bar of suitable capacity, and the read or write speed of DDR2 SDRAM is higher than the Flash chip far away, therefore can accomplish that in DDR2 SDRAM part volume-variable, transfer rate are fast, the collection of the detection data big for following data volume, that cache-time is long, speed is fast is prepared.
Fig. 2 is inner each logic function unit structural representation of FPGA.The main functional modules of the capture card algorithm that solid box partly realizes for FPGA among the figure, frame of broken lines are partly represented the outer member that is associated with module among the FPGA.
Functional unit as the FPGA inside of major control chip on the capture card comprises: PCI Express bus control unit, flow control and channel scheduling unit, the difference I/O interface unit that is connected with detector, DDR2 SDRAM control module and cell fifo.
In data acquisition, at first the command signal sent of main frame is given the GTP high-speed transceiver via PCI Express x8 link transmission; GTP sends the signal data stream that receives to the package operation of separating that PCI Express stone carries out PCI Express packet, by PCI Express stone the order data payload that parses is passed to identification and the parsing that PIO order Transmit-Receive Unit carries out order then, and be transferred to state and command control unit is carried out corresponding command response logic: if the order that main frame sends is to gather initiation command, state and command control unit send the collection sign on to difference I/O interface unit, and difference I/O unit begins to receive the detection data of three infrared band detectors; And state and command control unit send sign on to flow control and channel scheduling unit, and stable, continuous data transmission path is set up by cell fifo and DDR2SDRAM control module are controlled in flow control and channel scheduling unit; State and command control unit are also controlled the DMA data transmission unit, according to DMA data transmission sequential detection data is sent to PCI Express stone by this unit, carry out the packet generating run of PCI Express bus specification defined by PCI Express stone, send the packet that generates to the GTP high-speed transceiver then, on PCI Express x8 link, send the data to main frame by GTP, and state and command control unit control PIO order Transmit-Receive Unit send look-at-me to main frame after the complete image data frame having transmitted.If the order that main frame sends is to gather the finish command, state and command control unit send instruction to flow control and channel scheduling unit, whether the first data to DDR2 SDRAM control module inquiry present frame in this unit cushion is finished, wait for that its buffering finishes, then signal is finished to state and command control unit transmission present frame in this unit, and close the difference input-buffer FIFO of cell fifo, stop to receive data fifo; State and command control unit inquire present frame finish signal effectively after, then send the instruction that stops data collection to difference I/O interface unit; State and command control unit wait for that the DMA data transmission unit sends data among the DDR-PCIE buffer memory FIFO in the cell fifo after PCI Express stone finishes to, control PIO order Transmit-Receive Unit sends look-at-me to main frame, and closes the DMA data transmission unit and by Control Flow control and channel scheduling unit the DDR2-PCIE buffer memory FIFO in the cell fifo is closed.
The structure of described PCI Express bus control unit as shown in Figure 3, it comprises the GTP of high-speed data transmitting-receiving, PCI Express stone logical block, state and the command control unit of realizing PCI Express bus protocol, PIO order Transmit-Receive Unit and DMA data transmission unit.Described PCI Express stone logical block is based on the stone resource of LogiCORE IP Endpoint Block among the FPGA of the Virtex-5L X50T of Xilinx company, realize that PCI Express bus protocol specification data bag generates and packet is separated package operation, and pseudo channel VC technology and flow control technique in the supporting bus protocol specification; Described GTP is based on the functional unit of high-speed data transceiver, be responsible between PCI Express stone logical block and PCI Express x8 bus path, according to the packet on the electrical standard transmitting-receiving PCI Express bus physical link of bus specification definition; The order that described state and command control unit send main frame is resolved and is controlled among the FPGA other functional units and carries out Host Commands, and the various status informations (as: state finished of the record of Host Command, current image frame metadata cache, upload state that image frame data finishes etc.) of capture card in the record gatherer process; Described PIO order Transmit-Receive Unit is responsible for receiving the order that main frame sends with the PIO pattern on PCI Express bus, and after finishing the image frame data of uploading, sends interrupt request singal to main frame with the PIO pattern; Described DMA data transmission unit be responsible for upload number of image frames according to this mode transfer of DMA on PCI Express bus.
Described flow control and channel scheduling unit, will be at initial phase according to the form and the size of the image of the infrared eye of three wave bands, the DDR2SDRAM ping-pong buffer that distributes a pair of fifo buffer and corresponding size for each detector respectively, make the size of a pair of DDR2 sdram buffer of each detectors be the twice of this detector one two field picture size, and note the address information of the DDR2 SDRAM ping-pong buffer of each detector; In data acquisition, DDR2 SDRAM control module is passed to the address information of uploading buffer zone that is used among the DDR2SDRAM under the work at present state deposit the current frame buffer district of difference input data and carry out PCI Express transmission in this unit, by DDR2 SDRAM control module DDR2 SDRAM is carried out concrete data read-write operation, if the current frame data buffering is finished, then can detect DDR2 SDRAM control module is finished signal to present frame effective set; Described flow control also will distribute the difference input fifo buffer of corresponding size according to the message transmission rate of different infrared eyes with the channel scheduling unit, mates the infrared eye of different transmission rates; Because the view data flow difference of multiwave infrared eye, described flow control and channel scheduling unit are by the administrative mechanism of the VC tunnel of use PCI Express, the detector data path big for the view data flow distributes a plurality of tunnels, the detector data path little for image data amount distributes less tunnel, come to be the data transfer bandwidth on each detector division PCI Express x8 bus thus, VC tunnel one on the link has 8, numbering is from 0～7, the VC number that the data path of each detector can be assigned with, be no more than 8 at most, minimumly be not less than 1; And, described flow control and channel scheduling unit be provided with according to the distribution condition of VC on each detector data path its corresponding DDR2-PCIE the FIFO buffer memory size and with the mapping relations of VC tunnel, thereby make the view data of each detector can be on PCI Express bus by at a high speed, synchronously, real-time Transmission.
Described difference I/O interface unit mainly docks with the data-interface of wave band infrared eye, this unit can be according to the sequential requirement of the data transmission of different-waveband infrared eye, carry out the reception of view data, and data-interface definition according to different detectors, data layout is adjusted into unified data ordering pattern, and the difference that is sent to corresponding detector among the FPGA is then imported the buffer memory that carries out view data in the fifo buffer.
Described DDR2 SDRAM control module, the input-output operation of the data of control detector in the ping-pong buffer of DDR2 SDRAM.In data acquisition, DDR2 SDRAM control module reads the view data of detector from difference input fifo buffer, and stores the current frame buffer district of detectors in DDR2 SDRAM into.When the view data of the present frame of each detector among the DDR2 SDRAM all store finish after, constantly be set to upload buffer zone in the current frame buffer district by DDR2 SDRAM control module at next, and unification reads into the data of this buffer zone in the FIFO buffer memory of DDR2-PCIE of detectors.Meanwhile, the control of DDR2 SDRAM control module is with the current frame buffer district of another buffer zone as this moment, buffer memory is by the image frame data of gathering that sends in the difference input FIFO buffer memory, thereby the data that guarantee the multiband detector can be by continuous, real-time receiving.
Described cell fifo, the data channel that in FPGA inside is three wave band infrared eyes is exactly distributed the fifo buffer of three pairs of associations, one of them buffer zone is the difference input-buffer FIFO at the detector data input, and another buffer zone is the DDR2-PCIE buffer memory FIFO that sends the image frame data of uploading as the DDR2SDRAM control module to PCI Express bus control unit.
Fig. 4 has shown the algorithm flow of multiband infrared image acquisition system.
Whole system operation flow process as we can see from the figure: system powers on after the beginning, and capture card and main frame at first all are introduced into the initial phase of system, enters waiting status at each self-initialize back capture card that finishes, and waits for the command signal that receives from main frame;
When acquisition system begins collecting work, the application program of main frame is sent the collection initiation command with the PIO pattern to capture card on PCI Express x8 bus, the PIO of FPGA control chip inside order Transmit-Receive Unit receives this order on the capture card, sends the parse operation that state and command control unit carry out order then to; When learning this order for after gathering initiation command, described state and command control unit send the instruction of work to difference I/O interface unit, flow control and channel scheduling unit, FIFO buffer cell, DDR2 SDRAM control module; Difference I/O interface unit begins to read in the view data that three infrared band detectors detect, then view data is deposited among the difference input FIFO corresponding in the FIFO buffer cell, through DDR2 SDRAM control module data are deposited in the DDR2 SDRAM current frame buffer district again, and detect the storing state of the data of three band detectors in DDR2 SDRAM current frame buffer district, when detected store status is---if the current frame buffer district of three detectors does not all finish buffering, the detector data that then needs to continue not finishing buffering is proceeded buffer memory, step is with above-mentioned data acquisition, if the current frame buffer district of three detectors has all finished buffering, then enter the operation of ping-pong buffer, soon the current frame buffer district of the good data of buffer memory is adjusted into and uploads buffer zone, upload to main frame for data and to prepare, and another buffer zone is adjusted into next current frame buffer district of data acquisition system (DAS) constantly, carries out above-mentioned data acquisition; The image data transmission that system will upload in the buffer zone is given DDR2-PCIE buffer memory FIFO corresponding in the FIFO buffer cell, passes to PCI Express stone and gives main frame with image data transmission by GTP on PCI Express x8 bus with the DMA data-transmission mode through the DMA data transmission unit then; By the time behind this image frame data end of transmission of all detectors, send interrupt request by PIO order Transmit-Receive Unit mode with PIO on PCI Express bus to main frame, and detect current coomand mode, owing to be " collection initiation command ", then capture card turns back to the mode of operation of uploading image frame data; The driver of main frame receives the view data of each detector in the corresponding host memory space on the PCI Express bus, and the interrupt request of the image frame data end of transmission of wait capture card transmission, in case receive this look-at-me, the driver of main frame is given notice to the application program of main frame, and driver is inquired about the coomand mode of current host side, if beginning acquisition, then remove current look-at-me and return the state that receives data, use ping-pong buffer mechanism in internal memory, to receive next view data constantly, the application program of the main frame image frame data that reads three detectors from internal memory shows when the operation interface of application program carries out three band images then, and with data with stored in file format in the hard disk of main frame.
When acquisition system finishes collecting work, the application program of main frame is sent collection the finish command with the PIO pattern to capture card on PCI Express x8 bus, the PIO of FPGA control chip inside order Transmit-Receive Unit receives this order on the capture card, sends the parse operation that state and command control unit carry out order then to; When learning that this order is for after gathering the finish command, described state and command control unit can check at first whether the current frame buffer district of three detectors among the DDR2 SDRAM all finishes data buffering, if buffering is not finished, then proceed the operation of data acquisition, be that difference I/O interface unit reads in the view data that three infrared band detectors detect, then view data is deposited among the difference input FIFO corresponding in the FIFO buffer cell, through DDR2 SDRAM control module metadata cache is entered in the DDR2 SDRAM current frame buffer district again; After waiting for that current frame buffer is finished, close next operation of data acquisition constantly, the data of promptly closing difference I/O unit read in cell fifo in difference input-buffer FIFO; Carry out the operation of ping-pong buffer again, the current frame buffer district of the good data of buffer memory is adjusted into uploads buffer zone, then with the DDR2-PCIE buffer memory FIFO in the view data process FIFO buffer cell, in the DMA data transmission unit, pass to PCI Express stone and on PCI Express x8 bus, give main frame image data transmission by GTP with the DMA data-transmission mode, by the time behind this image frame data end of transmission of all detectors, send interrupt request by PIO order Transmit-Receive Unit mode with PIO on PCI Express bus to main frame, detect current coomand mode at last, owing to be " collection the finish command ", then capture card is closed each unit, power cut-off; The driver of main frame will receive the view data of each detector on the PCI Express bus, the interrupt request that capture card sends behind the wait image frame data end of transmission, in case receive this look-at-me, the driver notice of main frame shows and hard-disc storage when the application program of main frame is carried out the image frame data of three detectors, inquire about the current command forms of host side then, if for finishing acquisition, the then application program of main frame and driver end operation no longer carry out next Data Receiving constantly and the operation of demonstration, storage.
Claims (3)
1. multiband infrared image real-time acquisition system based on PCI Express bus, it comprises bus run and the capture card of main frame, PCI Express x8, it is characterized in that:
Described main frame adopts the embedded computer module;
Described capture card comprises three difference I/O interfaces, FPGA control chips and is connected to the memory module of DDR2 sdram memory bar;
Adopt the bus interface of the PCI Express of x8 passage to carry out data transmission and communicate by letter between described main frame and the capture card;
When described acquisition system is carried out collecting work: earlier send acquisition instructions to capture card by the bus run of main frame by PCI Express x8, after the FPGA of capture card received instruction, control difference I/O interface received the view data of multiband detector among the DDR2 SDRAM of capture card and carries out buffer memory; After the current image frame data buffering for the treatment of all detectors is finished, FPGA control sends the present image frame data of buffer memory among the DDR2 SDRAM to main frame by PCI Express x8 bus, and meanwhile capture card also will carry out the collection and the buffer memory work of next image frame data constantly according to aforesaid operations; Treat main frame after bus reception image frame data is finished, main frame carries out showing synchronously in real time and the image storage of multiband infrared image.
2. multiband infrared image real-time collecting method based on the described system of claim 1 is characterized in that may further comprise the steps:
Step 1, main frame sends " beginning to gather " instruction to the real-time capture card of multiband infrared image, is carried out the work of data acquisition and transmission by capture card:
Step 2, the PCI Express bus control unit of FPGA receives with the PIO pattern on PCI Express x8 bus after " beginning to gather " instruction of main frame transmission on the capture card, opens the difference I/O interface unit of FPGA, prepares to carry out the reception of data;
Step 3, capture card links to each other with the data channel of a plurality of wave band infrared eyes by difference I/O interface, and be responsible for data that the multiband detector is detected simultaneously and receive into, and in the FIFO buffer cell, carry out buffer memory by the difference I/O interface unit of FPGA inside;
Step 4, the DDR2 SDRAM control module on the capture card among the FPGA writes the data that receive in the FIFO buffer cell in the ping-pong buffer of DDR2 SDRAM;
Step 5, flow control on the capture card among the FPGA and channel scheduling unit carry out the rate-matched and the flow allocating on PCI Express bus of multidetector, thereby dispose the state of DDR2-PCIE buffer memory FIFO corresponding on each band detector data acquisition path;
Step 6, after the equal buffer memory of current frame image data for the treatment of the multiband detector is finished, DDR2 SDRAM control module on the capture card among the FPGA will buffer memory be good in DDR2S DRAM image frame data send the DDR2-PCIE buffer memory FIFO of distributing to, meanwhile FPGA also will carry out next collection buffer memory work of image frame data constantly in the ping-pong buffer of DDR2 SDRAM;
Step 7, the FIFO buffer cell on the capture card among the FPGA is transferred to the image frame data of DDR2-PCIE buffer memory FIFO by the PCI Express bus control unit among the FPGA;
Step 8, PCI Express bus control unit on the capture card among the FPGA with image frame data according to the DMA data-transmission mode, on the bus run of PCI Express x8, send to main frame, and all upload in the image frame data of multiband detector and send to interrupt to main frame with the PIO pattern after finishing;
Step 9, main frame receive after the look-at-me that capture card sends by the PIO pattern on PCI Express bus, and main frame is read the data of picture frame, carry out showing synchronously in real time and operation that image is stored of multiband infrared image;
Step 10, when gathering end, capture card transmits the view data that current detector detects to main frame, and no longer carry out the collecting work of next time chart picture frame, and after finishing, the multiband infrared image data transmission notifies main frame in the mode of interrupting, main frame carries out the demonstration of infrared image of a plurality of wave bands and the operation of image storage then, closes the operational module of whole acquisition system at last.
3. a kind of multiband infrared image real-time collecting method according to claim 2 based on the described system of claim 1, it is characterized in that: the rate-matched and the flow allocating on PCI Express bus that carry out multidetector in the flow control described in the step 5 and channel scheduling unit are the VC pseudo channel technology of utilization PCI Express bus, by being the VC pseudo channel of the distribution of flows varying number of different detectors, thus distinguish data by the time amount of bandwidth; Described control module is also carried out flow control to each VC pseudo channel, and these VC pseudo channel buffer zones are corresponded on the FIFO of identical size, thereby guarantees the load balancing between each VC pseudo channel.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101118568A (en) * | 2007-09-19 | 2008-02-06 | 中国科学院上海技术物理研究所 | Device and method for outputting signal of emulation infrared detector |
| CN101901278A (en) * | 2009-12-18 | 2010-12-01 | 中国科学院西安光学精密机械研究所 | High-speed data acquisition card and data acquisition method |
-
2011
- 2011-01-21 CN CN 201110024558 patent/CN102117342A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101118568A (en) * | 2007-09-19 | 2008-02-06 | 中国科学院上海技术物理研究所 | Device and method for outputting signal of emulation infrared detector |
| CN101901278A (en) * | 2009-12-18 | 2010-12-01 | 中国科学院西安光学精密机械研究所 | High-speed data acquisition card and data acquisition method |
Non-Patent Citations (1)
| Title |
|---|
| 《红外技术》 20110120 兰春嘉等 《基于PCI Express的高速红外图像采集系统》 37-40 1-3 第33卷, 第1期 * |
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