CN101005059A - Copper metallized barrier layer structure of integrated circuit or semiconductor device and its preparing method - Google Patents

Copper metallized barrier layer structure of integrated circuit or semiconductor device and its preparing method Download PDF

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CN101005059A
CN101005059A CN 200710071667 CN200710071667A CN101005059A CN 101005059 A CN101005059 A CN 101005059A CN 200710071667 CN200710071667 CN 200710071667 CN 200710071667 A CN200710071667 A CN 200710071667A CN 101005059 A CN101005059 A CN 101005059A
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barrier layer
integrated circuit
semiconductor device
layer structure
copper metallized
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CN100521188C (en
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王颖
赵春晖
曹菲
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Harbin Engineering University
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Harbin Engineering University
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Abstract

The invention discloses structure of copper metallized barrier layer in IC or semiconductor device. The invention includes a substrate, as well as Zr adhesion layer, barrier layer and Zr buffer layer set up on the substrate. The barrier layer is setup between the Zr adhesion layer and the Zr buffer layer, which is setup at top most. The invention improves capability of Cu for anti electromigration, performance of barrier layer, adhesiveness between layers, as well as reduces contact resistance. The invention possesses features of high production efficiency, easy of use, and no specific technique and devices required on preparing technique.

Description

A kind of integrated circuit or semiconductor device copper metallized barrier layer structure and preparation method thereof
(1) technical field
The invention belongs to the semiconductor device fabrication field, particularly a kind of integrated circuit or semiconductor device copper metallized barrier layer
Technical field.
(2) background technology
Along with further dwindling of very lagre scale integrated circuit (VLSIC) characteristic size, the integrity problem that the RC of interconnection line postpones and electromigration causes becomes the key point that influences circuit speed gradually.Because Cu has low resistivity and high deelectric transferred performance, make it become a kind of desirable intraconnections material and replace traditional Al wiring.But the Cu atom is easy to diffuse into oxide or dielectric material, forms the low puncture of interconnection line, and can be diffused into formation deep energy level trap in the silicon soon, or generates Cu with silicon (＜200 ℃) reaction at a lower temperature 3Si causes the contamination of active area and causes junction leakage and threshold voltage shift, even makes component failure.Therefore, need between Cu and oxide and dielectric material, get involved the barrier layer and stop that effectively Cu spreads in Si, also improve the binding ability of Cu film and matrix simultaneously.
Refractory metals such as Ti, W, Ta, Mo and Cr become the material that adopts the earliest in the diffusion impervious layer research owing to having high-melting-point, good attachment characteristic and high conductivity.But because thermal stability is not high, Cu easily is diffused into the Si substrate by the crystal boundary of these heating resisting metals, forms Cu 3Si causes losing efficacy mutually.The silicide of heating resisting metal such as TaSi, also can be owing to the reaction temperature of Si and Cu the low Cu interconnect failure that causes; Afterwards, the researcher finds to introduce nitrogen in high melting metal layer can limit diffusion by the rapid diffusion passage that improves in the grain boundary, thereby improves its barrier properties.Therefore the nitride for refractory metal has also carried out a large amount of research, as nitride such as TiN, WN, MoN, TaN and CrN, and finds that recently Zr base barrier layers such as TaZr, TiZr, ZrN, ZrSiN, ZrCN, ZrAlN, TiZrN have more excellent performance.
(3) summary of the invention
The object of the present invention is to provide a kind of special process and special installation, production efficiency height, the integrated circuit that is easy to promote the use of or semiconductor device copper metallized barrier layer structure and preparation method thereof of need not.
The object of the present invention is achieved like this:
1, a kind of integrated circuit or semiconductor device copper metallized barrier layer structure, Zr adhesion layer, barrier layer, Zr resilient coating that it comprises substrate and is provided with on substrate, the barrier layer is arranged between Zr adhesion layer and the Zr resilient coating, and the Zr resilient coating is arranged on topmost;
2, a kind of integrated circuit or semiconductor device copper metallized barrier layer structure and preparation method thereof:
(1) growth Zr layer on substrate, the THICKNESS CONTROL of this thin layer is at 10-100nm;
(2) with step (1) gained substrate growth barrier layer, film thickness monitoring is at 10-200nm;
(3) with step (2) gained substrate growth Zr layer, the THICKNESS CONTROL of this thin layer is at 10-100nm;
(4) with step (3) gained substrate growth Cu film or Cu alloy film, film thickness monitoring is at 200～2000nm;
(5) step (4) gained substrate was annealed 40-80 minute in 300～420 ℃ protective atmosphere, slowly reduce to room temperature then.
The present invention also has some technical characterictics like this:
1, described substrate is microelectronic component or integrated circuit (IC) chip;
2, described barrier layer is Zr base barrier layer, is TaZr, TiZr, ZrN, ZrSiN, ZrCN, ZrAlN or TiZrN;
3, described Zr resilient coating is provided with Cu film or Cu alloy film, and to be Cu not high with solid solubility therein and the alloy film that can form at element S n, Mg, Al, Cr or the Zr that crystal boundary is separated out for the Cu alloy film;
4, described growth barrier layer, Zr layer utilize the method for CVD, PVD or ALD;
5, described growth Cu film or Cu alloy film utilize CVD, PVD or electric plating method;
6, described protective atmosphere is N 2Atmosphere, Ar atmosphere, N 2/ H 2Mixed atmosphere or Ar/H 2Mixed atmosphere.
The present invention proposes a kind of integrated circuit or semiconductor device copper metallized barrier layer structure and preparation technology thereof; growth Zr/ barrier layer/Zr sandwich structure on semiconductor chip; and on this structure, grow Cu film or Cu alloy film; with gained semiconductor chip annealing in process in protective atmosphere, slowly reduce to room temperature then.The present invention has improved performance, the interlayer adhesion on Cu anti-electromigration ability, barrier layer greatly and has reduced aspect such as contact resistance, and preparation technology need not special process and special installation, production efficiency height, is easy to promote the use of.
(4) description of drawings
Fig. 1 is the sandwich barrier system schematic diagram of Zr adhesion layer, barrier layer, Zr resilient coating.
(5) embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments:
In conjunction with Fig. 1, a kind of integrated circuit of the present invention or semiconductor device copper metallized barrier layer structure comprise substrate 10 and are arranged between Zr adhesion layer 11 and the Zr resilient coating 13 on the Zr adhesion layer 11 that is provided with on the substrate, barrier layer 12, Zr resilient coating 13, barrier layer 12 that Zr resilient coating 13 is arranged on topmost.On adhesion layer on the Zr, also be provided with Cu film or Cu alloy film 14.
Embodiment 1:
(1) with the HF acid (HF: H of silicon chip in dilution 2O=1: with a large amount of deionized water rinsings, putting into the base vacuum degree after nitrogen dries up is 2 * 10 after 1 minute in ultrasonic cleaning 20) -5In the vacuum chamber of Pa.
(2) the Zr film of employing radio frequency reaction magnetron sputtering about 20nm of deposition of thick on silicon chip.Reaction vacuum degree in the vacuum chamber is 0.3Pa; Sputtering power 150W; Substrate bias during sputter is-200V.
(3) the ZrSiN film of employing radio frequency reaction magnetron sputtering about 50nm of deposition of thick on step [2] gained substrate.Reaction vacuum degree in the vacuum chamber is 0.3Pa; Gas flow rate N2/Ar is 4sccm/16sccm; Sputtering power 300W; Substrate bias during sputter is-200V.
(4) the Zr film of usefulness radio frequency reaction magnetron sputtering about 20nm of deposition of thick on step [3] gained silicon chip.Reaction vacuum degree in the vacuum chamber is 0.3Pa; Sputtering power 150W; Substrate bias during sputter is-200V.
(5) sample does not go out vacuum chamber after the deposition ZrSiN film, adopts the Cu-Zr alloy film of the thick about 200nm of DC pulse magnetron sputtering method regrowth in pure Ar atmosphere, and the air pressure of vacuum chamber is 0.1Pa, and sputtering power is 200W.
[6] with step (5) gained semiconductor chip at sample in vacuum (2 * 10 -3Pa) and H 2/ N 2Annealing is 60 minutes in the mixed atmosphere of (volume ratio is 1: 9), slowly reduces to room temperature then.
Embodiment 2:
(1) with SiO 2With a large amount of deionized water rinsings, putting into the base vacuum degree after nitrogen dries up is 2 * 10 after the ultrasonic cleaning of/Si substrate -5In the vacuum chamber of Pa.
(2) the Zr film of employing radio frequency reaction magnetron sputtering about 10hm of deposition of thick on silicon chip.Reaction vacuum degree in the vacuum chamber is 0.3Pa; Sputtering power 150W; Substrate bias during sputter is-200V.
(3) the ZrN film of employing radio frequency reaction magnetron sputtering about 20nm of deposition of thick on step [2] gained substrate.Reaction vacuum degree in the vacuum chamber is 0.3Pa; Gas flow rate N2/Ar is 2sccm/18sccm; Sputtering power 300W; Substrate bias during sputter is-200V; Underlayer temperature is 200 ℃.
(4) the Zr film of usefulness radio frequency reaction magnetron sputtering about 10nm of deposition of thick on step [3] gained silicon chip.Reaction vacuum degree in the vacuum chamber is 0.3Pa; Sputtering power 150W; Substrate bias during sputter is-200V.
(5) sample does not go out vacuum chamber after deposition ZrSiN film, adopts the Cu-Zr alloy film of the thick about 200nm of DC pulse magnetron sputtering method regrowth in pure Ar atmosphere, and the air pressure of vacuum chamber is 0.1Pa, and sputtering power is 200W.
[6] with step (5) gained semiconductor chip at sample in vacuum (2 * 10 -3Pa) and N 2Annealing is 60 minutes in the atmosphere, slowly reduces to room temperature then.

Claims (8)

1, a kind of integrated circuit or semiconductor device copper metallized barrier layer structure, it comprises substrate, it is characterized in that it also is included in Zr adhesion layer, barrier layer, the Zr resilient coating that is provided with on the substrate, the barrier layer is arranged between Zr adhesion layer and the Zr resilient coating, and the Zr resilient coating is arranged on topmost.
2, a kind of integrated circuit according to claim 1 or semiconductor device copper metallized barrier layer structure is characterized in that described substrate is semiconductor chip or integrated circuit.
3, a kind of integrated circuit according to claim 1 or semiconductor device copper metallized barrier layer structure is characterized in that described barrier layer is Zr base barrier layer, is TaZr, TiZr, ZrN, ZrSiN, ZrCN, ZrAlN or TiZrN.
4, the preparation method of a kind of integrated circuit according to claim 1 or semiconductor device copper metallized barrier layer structure, it is characterized in that described Zr resilient coating is provided with Cu film or Cu alloy film, to be Cu not high with solid solubility therein and the alloy film that can form at element S n, Mg, Al, Cr or the Zr that crystal boundary is separated out for the Cu alloy film.
5, the preparation method of a kind of integrated circuit or semiconductor device copper metallized barrier layer structure is characterized in that:
(1) growth Zr layer on substrate, the THICKNESS CONTROL of this thin layer is at 10-100nm;
(2) with step (1) gained substrate growth barrier layer, film thickness monitoring is at 10-200nm;
(3) with step (2) gained substrate growth Zr layer, the THICKNESS CONTROL of this thin layer is at 10-100nm;
(4) with step (3) gained substrate growth Cu film or Cu alloy film, film thickness monitoring is at 200～2000nm;
(5) step (4) gained substrate was annealed 40-80 minute in 300～420 ℃ protective atmosphere, slowly reduce to room temperature then.
6, the preparation method of a kind of integrated circuit according to claim 5 or semiconductor device copper metallized barrier layer structure is characterized in that described growth barrier layer, Zr layer utilize the method for CVD, PVD or ALD.
7, the preparation method of a kind of integrated circuit according to claim 5 or semiconductor device copper metallized barrier layer structure is characterized in that described growth Cu film or Cu alloy film utilize CVD, PVD or electric plating method.
8, the preparation method of a kind of integrated circuit according to claim 5 or semiconductor device copper metallized barrier layer structure is characterized in that described protective atmosphere is N 2Atmosphere or Ar atmosphere, N 2, H 2Mixed atmosphere or Ar, H 2Mixed atmosphere.
CNB2007100716670A 2007-01-19 2007-01-19 Copper metallized barrier layer structure of integrated circuit or semiconductor device and its preparing method Expired - Fee Related CN100521188C (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005384A (en) * 2010-09-16 2011-04-06 哈尔滨工程大学 Method for low temperature annealing of copper metallized self-formed barrier layer
CN106816375A (en) * 2015-11-30 2017-06-09 英飞凌科技奥地利有限公司 Semiconductor devices and the method for forming semiconductor devices
CN112242350A (en) * 2020-10-19 2021-01-19 西安文理学院 Al for copper interconnection line2O3ZrN double-layer diffusion barrier layer and preparation method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005384A (en) * 2010-09-16 2011-04-06 哈尔滨工程大学 Method for low temperature annealing of copper metallized self-formed barrier layer
CN102005384B (en) * 2010-09-16 2012-02-01 哈尔滨工程大学 Method for low temperature annealing of copper metallized self-formed barrier layer
CN106816375A (en) * 2015-11-30 2017-06-09 英飞凌科技奥地利有限公司 Semiconductor devices and the method for forming semiconductor devices
US10332793B2 (en) 2015-11-30 2019-06-25 Infineon Technologies Austria Ag Self-organizing barrier layer disposed between a metallization layer and a semiconductor region
CN106816375B (en) * 2015-11-30 2020-12-08 英飞凌科技奥地利有限公司 Semiconductor device and method of forming a semiconductor device
CN112242350A (en) * 2020-10-19 2021-01-19 西安文理学院 Al for copper interconnection line2O3ZrN double-layer diffusion barrier layer and preparation method thereof

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