CN1008594B - Digit time slot of using in the digital branch exchange and signal bus - Google Patents

Abstract

Switch on a digital small exchanger system, this system can adopt and concentrate exchange or disperse these two kinds of technology of exchange.It almost is general with parallel bus that this switch has between subscribers feeder card module.One can have a time slot bus with upper module can transmit speech PCM or data-signal in a time slot.Bus also has a signal bus, selects subscribers feeder card module by a uniline and a central control module conversation, to keep the versatility of this bus with this bus.Between selected user's card module and central control module, signal message also transmits by the pair of parallel circuit.

Description

Digit time slot of using in the digital branch exchange and signal bus

The present invention relates to Private Branch Exchange PBX used in the digital telephone field (PBX), particularly about a time slot bus and a signal bus used in the digital branch exchange that can transmit speech and data-signal.

Private Branch Exchange PBX is used in the current telephone system more and more.A Private Branch Exchange PBX links the phone in office, building or the factory.In small exchanger system anyone can both talk and the expense and time that need not to use outside line and equipment with the another one people within this system.

Small exchanger system becomes digital day by day.Telephoner's analogue voice signal is converted into digital signal.These digital signals send out by small exchanger system.In addition, Private Branch Exchange PBX also is used for transmitting Computer signal more and more.This part ground is owing to use the cause of personal computer in family and office.

The heart of this system, Private Branch Exchange PBX couples together the telephoner in the native system as shown in Figure 1, if want that Private Branch Exchange PBX also can be connected with outside line when small exchanger system people in addition makes a phone call, also can couple together the line of the telephoner of outside and native system simultaneously.In general, module or " subscribers feeder plug-in unit " that Private Branch Exchange PBX has some.Each subscribers feeder plug-in unit is received on the phone or " terminal " of some, will make it to be connected with each other with one group of circuit that is called " bus " between the subscribers feeder plug-in unit simultaneously, and this bus is also referred to as " backplane bus " sometimes.This bus as the bus among Fig. 1 10, has a time slot bus.The time slot bus can transmit the digital signal or the computer data of speech.

In a digital branch exchange, can under a certain speed, take a sample to voice signal, typical speed is per second 8000 times (8KHZ), resulting voltage sampling is converted into numeral, is typically " μ rule " or " A rule " coding of 8.Resulting position order (8000 * 8 or 64K bps) is known as the pulse code modulation (pcm) of original speech signal.Digital branch exchange transmits and exchanges to another place to PCM signal this in the native system.At last, the PCM signal is converted into analogue voice signal again people can be heard.

The PCM signal transmits on bus 10, transmits in certain time interval or time slot at these signals on the bus 10.Can transmit the data flow of PCM64K bps in each time slot, each speech channel of sending into or exporting is general so just need a time slot.Certainly, a time slot also can be used for transmitting computer data signal under the speed of 64K bps.

Except a time slot bus, bus 10 also has a signal bus.Except pcm encoder voice signal and data-signal, a digital branch exchange also must transmission " signal " or the control information relevant with individual speech or FPDP with exchange.Such as, for a rotary dialing phone, whether whether the important point is to know phone " off-hook ", dial or the like.Like this, the information that Private Branch Exchange PBX just must have way to collect signal there from each voice port is wanted to be sent to a control device to this information simultaneously and is got on, and the way that this control device adopts speech for example to link affacts on this information.

All digital branch exchanges all must have certain time slot bus and signal bus.Be accompanied by having of these buses a lot of target and the problems of conflict mutually.Comprising:

(a) versabus peace row bus wiring." position " that a bus in canonical system has some; Each position has a Bussing connector to match with a module or subscribers feeder plug-in connector, a module is received on the bus, if in each Bussing connector of bus, same signal is on the identical position, and this bus is exactly " general " so.On a general bus, any one module can link to each other with any position in the bus.The benefit of this system is tangible.

A completely parallel bus topolopy can satisfy the requirement of a versabus.This can be arranged on the printed circuit board (PCB) at an easy rate.No matter how much quantity of the position in the bus is, can receive on any point at an easy rate.

If have only the circuit of minority not parallel,, on each current potential breakpoint with on each distinguished position the circuit of different numbers is being arranged so such as a star topology is arranged around the control device.So, this bus is just no longer general.

(b) in the maximum data transfer bandwidth of specifying under the peak signal speed.

Several operating characteristics characteristics of a bus are subjected to the restriction of maximum exchange signal speed on the bus.Such as, exchange velocity is limiting maximum total line length faster, also can produce radio frequency interference simultaneously.On the other hand, fast speeds but can transmit more information with less circuit.Therefore, under the situation of certain switching signal maximal rate, signal as much as possible should transmit with this maximal rate, so that it is wide to obtain maximum data carousel.

(c) time slot allocation flexibly

Because different modules can be used for the speech channel of different numbers, the target of a versabus just means, the time slot that a fixed number should not be arranged for the bus location of any one appointment is even adopting under the situation of concentrating time gas exchange (Fig. 2 (a)), also be like this.On the contrary, time slot should be assigned on each module, and is desired as special system configuration.

(d) the addressable ability of each module

Although be parallel bus terminals and have versatility, need some equipment and select each to be used for the subscribers feeder card module of certain operations; These operations comprise as sending and received signal information, register and reset etc.But, provide independent " module selection " line parallel bus terminals that has destroyed again to be wanted and the structure that obtains versatility for each module.

(e) time gas exchange of concentrating or disperseing

On existing Private Branch Exchange PBX, using two kinds of different time gas exchange technology." concentrate " exchange shown in Fig. 2 (a).In this time gas exchange technology, there is bar time slot bus to transmit voice signal and data-signal in logic.Article one, bus is used for the output time slot signal of central control unit is sent to the subscribers feeder card module that comprises each port circuit, and another bus is used for transmitting the time slot signal of importing in opposite direction.Each bar bus has the time slot of a special use to be used for each port of system.Such as, a voice port " X " always is arranged in its PCM signal on the input time slot X, and receives the PCM signal on an output time slot X.

Because central control unit receives all input time slot signals and speech on all output time slots or data-signal are sent to the subscribers feeder plug-in unit, the time slot interchange circuit in the central control unit can carry out all these connections.Such as, connectivity port X and Y, the time slot interchange circuit in the central control unit is programmed preface, the PCM sampling of delivering on the input time slot X is stored, and they are sent on the outer output time slot Y; Also can store the PCM signal of delivering on the input time slot Y and they are sent on the output time slot X simultaneously.

In " dispersion " exchange, shown in Fig. 2 (b), have only a single time slot bus in logic, and do not have concentrated time slot interchange circuit.On the contrary, each subscribers feeder card module all has the time slot interchange circuit of a part, this circuit can be received the input signal that obtains from any one port on any one time slot on the time slot bus, and this circuit can also be listened to the signal on any one time slot and they are delivered on any one output port simultaneously.

After this technology, for connectivity port X and Y, central control unit can be distributed a pair of time slot, and as P and Q, they are unnecessary to have any fixing relation with X and Y.Then, it just indicates the local time slot interchange circuit of port x to transmit on time slot P and receive on time slot Q.Indicate Y on P, to receive simultaneously transmitting on the Q.

In general, selecting the problem of the time gas exchange that concentrated time gas exchange still disperses for use is that the economic benefit of the technology that can adopt during according to the performance of switching technology and design is decided.Such as, dispersion technology can more effectively utilize time slot, because time slot is not to distribute to idle port, and concentration techniques is general relatively more cheap, because it only needs a time slot interchange circuit.

The present invention can reach above-mentioned a lot of targets and solve or alleviated above-mentioned a lot of problems greatly.

The invention relates to each module of Private Branch Exchange PBX with a lot of modules has a port at least and is used for getting in touch and delivers to signal that Private Branch Exchange PBX goes and the signal that comes from Private Branch Exchange PBX; There are some parallel circuits to be used for transmitting signal between each module; Simultaneously be used for limiting the required number of time slot of signal on the communication line and be used for starting module and in predetermined a part of time slot, communicate also being connected to clock apparatus on the module, make more than one module in same time slot, to communicate.

Parallel like this, in the present invention communication line provides a versabus.In addition, farthest increase transfer rate and do not needed to improve the exchange velocity of time slot.

Each module can be addressed respectively.Each module has a device that produces signal, be used for discerning this module, in addition with above-mentioned recognition device be connected with clock apparatus to also have a device to be used for be that module is selected time slot, like this, on the circuit in the time slot selection device connection line, by selected time slot signal to module address.

The present invention not only can be used for concentrated time gas exchange but also can be used for disperseing time gas exchange.Except the subscribers feeder card module with outside port, Private Branch Exchange PBX has a central control module.In concentrating exchange, central control module is sent to the subscribers feeder card module to signal by first group in the parallel circuit, and the signal that comes from the subscribers feeder card module by second group of received of parallel circuit.This control module also the 3rd group by parallel circuit sends control information module to and receives information from module.Concerning disperseing exchange, control module has a device, and this device is used for passing through first group of line transmissioning signal by control module in predetermined time slot, also is used for sending the control module of control information indication on the 3rd group of circuit simultaneously and ends.The subscribers feeder module itself has a device and links to each other with the 3rd group of circuit, is used for by first or second group of line transmissioning signal, is used for receiving in predetermined time slot the signal on first or second group of circuit simultaneously.In these time slots, the structure of Private Branch Exchange PBX is with dispersing mode work.

Can understand the present invention better by detailed description with reference to the accompanying drawings.

Shown in Figure 1 is the profile diagram of digital branch exchange;

Fig. 2 A shows one in the structure of concentrating the digital branch exchange of working under the exchanged form; Fig. 2 B shows the structure at the digital branch exchange that disperses to work under the exchanged form.

Shown in Figure 3 is the details drawing of time slot bus of the present invention and signal bus.

Fig. 4 shows clock operation of the present invention and time slot timing.

It shown in Fig. 5 A the used time slot decoding circuit of subscribers feeder card module that is connected with time slot bus among Fig. 3; The timing operation of circuit is shown among Fig. 5 B.

Shown in Fig. 6 A be with each subscribers feeder card module that signal bus among Fig. 3 is connected on module select the circuit detail drawing; The timing operation of circuit is shown among Fig. 6 B.

Shown in Figure 7 is the central control module circuit that is used for driving the subscribers feeder card module selection circuit of signal bus among Fig. 3.

Shown in Figure 8 is central control module and subscribers feeder card module circuit, the input information of signal bus (IN), output information (OUT) and (Reset) circuit that resets coupling among these circuit and Fig. 3.

Shown in Figure 1 is the structure of a digital branch exchange.This switch generally has a central control module 11 and subscribers feeder module 12A-D.Central control module 11 carries out the centralized control of this switch, such as collecting signal message there from each module 12A-D, and the work between the Coordination module 12A-D.Typical subscribers feeder card module 12A-D has many ends, speech and data are sent to switch or sends here from switch by these ports.Each port all has independent communication line 13A-13C, and equipment such as phone are promptly received on the terminal of above-mentioned circuit one end.Other subscribers feeder card module (as 12D) may link to each other with trunk line 130, and trunk line links to each other with another one Private Branch Exchange PBX (with another small exchanger system), perhaps receives this kind equipment of total telephone system and gets on.Central control module 11 is to be connected by a bus 10 with subscribers feeder card module 12A-D.

Shown in Figure 3 is detail drawing by a bus of the present invention, and this bus is particularly useful in the little exchange of numeral.By connector 14A-14D these lines are received on the subscribers feeder card module.According to the design object of versatility, all buses are all parallel fully, exception be that single module's address terminal is received on the ground wire 41 selectively.This point is discussed later.

Bus among Fig. 3 is divided into three groups.First group is one group of clock line 21-23.Second group is set of time- slot line 24,25, and speech PCM signal between the module of Private Branch Exchange PBX and data all are to transmit by these time slot lines.The 3rd group is one group of holding wire 26-29, and these holding wires are used for the signal message between the delivery module.

Though all bus locations except the module's address signal all are the same, the module of different types can link to each other with each bus location.It is " bus person in charge's device " that a module is particularly arranged, because it provides clock and other modules of other main control signals then to respond these signals.In fact, this module is known as " central control unit ".An advantage of the present invention is exactly that central control module (perhaps any one other module) can be received on any one bus location.

First group of signal among Fig. 3 is clock, provided on circuit 21-23 by central control module.Shown in Figure 4 is in this embodiment of the present invention, the timing of these clocks operation.Signal TCLK A on the circuit 21 is one 2,048MHZ, and the clock of 33% duty cycle, the signal TCLK B on the circuit 22 is a clock that performance is the same, just the phase place with signal TCLKA interlaces 180 °.The importance of the shape of clock signal (or duty cycle) is discussed later among the present invention.The cycle of each clock is 1/(2.048MHZ), just about 488 nanoseconds (ns).

Signal TFRM is a frame signal, and it can continue clock cycle of action in per 125 microseconds (μ S), or moves once in the cycle at per 256 TCLKA or TCLKB.Interval between the continuous T FRM pulse is called one " frame ".In the PCM of μ-Lv or A-rule, this 125 microsecond (μ S) cycle is a standard.

For some maximum clock beat frequencies (being 2.048MHZ in the present embodiment), available number of time slot has been a maximum.In a general time slot bus design, have only a single time slot clock (" TCLK "), this time slot bus only transmits a single PCM signal or data-signal at whole TCLK in the cycle.In cycle, in one 125 microsecond (μ S) frame, limit 256 time slots at one 488 nanoseconds (ns) TCLK.

The present invention adopts two 2.048MHZ, 33% duty cycle clock, and TCLKA and TCLKB can limit two time slots at each 488 nanoseconds (ns) in the clock cycle.

As shown in Figure 4, time slot is divided into two groups, " A " and " B "." A " time slot is to occur when TCLKA is high, and " B " time slot is to occur when TCLKB is high.According to routine, no matter in which group, first time slot that occurs the back appearance at the TFRM signal is No. 0; Remaining is compiled No. 255 in order.Like this, TCLKA, TCLKB and TFRM signal just define 512 time slots, and numbering is from A-0 to A-255 and from B-0 to B-255.

After time slot was defined, speech PCM signal or data-signal were sent in the time on the time slot bus of circuit 24,25 abreast at special slot time.Fig. 3 represents a concentrated time gas exchange system.Two time slot buses are arranged, and bus is used for the TSIN signal (from any one module to central control module) of input time slot signal, and another bus is used for the TSOUT signal (from central control module to other module) of output time solt signal.Each bus of these buses all has 8 bit wides.In any moment (time slot), bus can transmit complete 8 PCM signals or data-signal.

In concentrated time gas exchange system, central control module is comprising the time slot interchange circuit, and it is storing all signals that receive from TSIN input bus 24, and in office when the crack is sent to TSOUT(output the signal that stores) on the bus 25.Like this, central control module just can be received any input time slot signal on any output time solt.

In concentrated time gas exchange system, central control module always drives TSOUT bus 25, but different subscribers feeder card modules drives TSIN bus 24 in different time-gap.On each module, use three-state driver to carry out the multisignal source ability that general operation just can obtain driving TSIN bus 24.For drive TSIN bus 24, the TSIN bus driver on a certain particular module only in the TSIN time slot allocation in this module, just be activated, and in other times, all be cut off.Who just must guarantee that each TSIN time slot can only be by a module drive on module the TSIN time slot allocation for who.

To the module upper type, continuous TSIN time slot can be by different module drive according to time slot allocation.Such as, in Fig. 4, time slot B-0 can be driven by module P, and time slot A-1 can be driven by module Q.In this case, the important point is that module P13TSIN driver will be cut off before the TSIN of module Q driver is activated.Otherwise module P and Q will drive the TSIN bus simultaneously in a short time, and this might make the noise in the system strengthen, and might cause that also driver stress increases (thereby failure rate increase), and this technology with driver is relevant.In ternary transistor-transistor-logic (TTL) bus driver technology of main employing at present, the noise in driver stress and the system may especially severe.

On the one hand, tristate TTL driver (such as the 74LS244 integrated circuit) designs to make every effort to reduce these influences than " connection " principle hurry up according to " disconnection ".Like this, if 74LS244 parts on bus are cut off and another is activated simultaneously, before second driver began to drive bus about 15 nanoseconds (ns), first driver will stop to drive it so.On the other hand, also can not start another driver simultaneously by a driver.For two drivers, difference on the propagation delay in the enable logic circuit, add the distance (is noticeable) of being separated by between two drivers in a bus system, can remove existing these 15 nanoseconds of (ns) safe rangies in 74LS244 parts and the similar driver at an easy rate.

For fear of these problems, clock TCLKA and TCLKB on circuit 21,22 have 33% duty cycle.These clocks are not to connect in 50% time of 488 nanoseconds (ns), and only connect in 1/3rd times in cycle.When adopting such duty cycle, in TSIN and TSOUT bus 24, it is " idle time " that 16% duty cycle all can be arranged between the continuous slot on 25, in this embodiment of the present invention, clock 2.048MHZ, to be 81 nanoseconds (ns) above-mentioned " idle time ", and though the characteristic of driver any all be this number.

Like this, if more a plurality of TCLK clocks are received in the system, duty cycle will be less than (1/ (N)) T, and N is the number of clock here, and T is the cycle of clock, and so just can guarantee has certain " idle time " between time slot.

On the TSIN bus 24 of concentrating time gas exchange, be very important above-mentioned this idle time.For the clock system among the present invention, module only needs to guarantee that it only drives the TSOUT bus when TCLKA or TCLKB are high.Under the situation of 2.048MHZ, each module determines to start in each clock cycle/by the time, have 81 nanoseconds (ns) to be used for propagation delay in the logical circuit.

In concentrated time gas exchange system, each module all has some fixing time slot allocation to give it when system moves.When system was when forming (i.e. installing) with the hardware jumper on the module or is added to parameter on the module with a software initialization degree, these time slots just were assigned with.The whole purpose of concentrating (opposite with dispersion) exchange is exactly to reduce the size and the cost for distributing time slot to spend of each subscribers feeder card module circuit.

The present invention adopts the minimum circuit that distributes time slot to use in module.An important improvement aspect time slot distribution circuit is to have used two-phase time slot clock (TCLKA and TCLKB) again.Although time slot bus 24,25(TSIN and TSOUT) respectively comprise 512 time slots, a special module is arranged in a centralized switching system, therefore its operation must can only connect 256 time slots (select the A group or select the B group) with reference to TCLKA or TCLKB.

From actual use aspect, this A/B divides that to open be important, because 256 time slots can be with one 8 digit counter decoding, and one 9 digit counter of 512 time slots needs.In view of present used counter circuit all is 4 or 8 digit counters, the present invention can save very big expense, because it has only used two 4 (or one 8) counter plugins to carry out time slot decoding, and does not use three 4 (or two 8) counter plugins.

The set of time-slot that another significant contribution of the present invention is to use the switch of minimum number or programmable bit to distribute (addressing) special module to use.Such as, if a module needs 8 time slots, 256 time slots in A group or the B group are divided into 32 groups so, every group of 8 time slots then need 5 figure places to come particular group of addressing.On the other hand, if a module needs 64 time slots, so just have only 4 groups, every group of 64 time slots come addressing with regard to available one 2 figure place.

It shown in Fig. 5 A the exemplary embodiments of time slot decoding circuit in each subscribers feeder card module.This specific embodiments can be deciphered the time slot in A group or the B group, and this depends on the position of switch 38.Selected one group of 256 time slot is divided into 16 groups, every group of 16 time slots; With 39 pairs of specific group addressing of one 4 figure place switch.Time slot 0 to 15 is in 0 group; Time slot 16 to 31 is in 1 group; Time slot 32 to 47 is in 2 groups, and the rest may be inferred by analogy.

Counter 31 is 8 binary counters, and it is exported from the QA(least significant bit) to the QH(highest significant position), it just increases progressively when rising edge appears in the CLK input signal; If but the LOAD input is 1 at the CLK rising edge, this counter will not counted, but the A to H that packs into goes up the input signal that occurs.

Decoder 33 is circuit, and in (Y0-Y15) is exported in its each at most only startup.If one in EN1 or the EN2 input is 0, all output is 0 all just.But, if EN1 and EN2 are 1, will be 1 with input A to the corresponding output of the binary digit among the D so, and all other output will be 0.

TSIN bus driver 35 is three-state drivers, and when its ENABLE is input as 0, its output will be cut off, if ENABLE is 1, will be used to drive TSIN bus 24 at A0 to the input value on the A7 so.

Input register 36 is comprising the d type flip flop that 8 edges trigger.If the CLKENABLE input is 1 when a rising edge appears at the CLK input, D input (TSOUT bus value) will be stored and exist in the trigger so, and will appear at Q output, go so that be sent in the subscribers feeder card module; All At All Other Times in, Q output will be held its previous numerical value.

Inverter 40 and AND gate 32,34 all are the gates of standard.It shown in Fig. 5 B the slip chart of decoding circuit among Fig. 5 A.Suppose that clock TCLKA is selected by switch 38, the binary number in switch 39 be " 0000 ", follows circuit with the time slot in 0 group, and promptly time slot 0 translates to 15.In burst length, on the trailing edge of clock TCLKA, have a corresponding rising edge to appear at the CLK input of counter 31 at TFRM, this counter is sent into counter output QH, QG, QF, QE, QD, QC, QB, QA to numerical value 11110000.4 binary " 1 " will send 1 at the output of the AND gate 31 of 4 inputs.Next time, when the TCLK clock is 1, two inputs of the EN1 of decoder 33, EN2 all will be 1, so the output of choosing (YO) (corresponding with the time slot A-0 on TSIN and the TSOUT bus) also will be 1.For next 15 TCLKA cycle of group, QH-QE will keep 1, and QD-QA one by one counts up to remaining 15 binary values simultaneously, and starts decoder output Y1 successively by time slot A-1 to A-15.

Binary value in the hypothesis switch 39 is not 0000 now, but 1110(is metric 14).Initial value in the counter 31 will be 00010000 rather than 11110000 so.Along with TF RM pulse begins, spend 224 extra clock cycle so that make rolling counters forward arrive first state " 11110000 " then, decoder output in this state (YO) is activated.Like this, the 14th group of time slot (time slot 224 to 239) is decoded.The operation of all the other each groups is identical therewith.

The ENABLE(that AND gate 34 is being controlled three-state driver 35 allows) input, make the method for the TSIN bus operation described according to the front, have only when time slot to be arranged in a group of addressing and to have only when TCLKA is 1, driver could drive TSIN bus 24.The CLKENABLE(clock starting of register 36) input control register 36 makes it can only change its content according to the set of time-slot of addressing.

Signal is exported or sent into to the module time slot bus of the outlet line of decoder 33 and TSIN and TSOUT signal for the internal wiring of module.The internal wiring of module does not belong to the scope of the invention; Moreover the present invention is used for existing subscribers feeder card module and internal wiring thereof.Very clear, logical equivalence can be used for any Digital Logic circuit.Redefine many switches 39 and can cancel inverter 40 among Fig. 5, and " ripple carries output " function of dress just can be cancelled the AND gate 32 of separation in utilizing in the binary counter circuit 31.

Equally, TCLK clock selecting number and time slot packet number must be from switches 40 yet.Other possibility selects to comprise two kinds of ways far from it, a kind of is to transmit these parameters according to the module position on the bus with " hardware connection ", another kind is to adopt the output port position that is addressed to the microprocessor on the module, and makes parameter transmission programmingization fully by the way that a register is deposited.In the embodiment that recommends, TCLK selector switch 38 is functions of bus upper module position, and time slot grouping selector switch 39 can be programme by means of the microprocessor on the module.

The total figure that is shown in Fig. 5 is useful for any amount of time slot, and this quantity should be two power, can be described as 2 ⁿIn these cases, used 8-n switch (switch 39 among Fig. 5), used a 8-n input and door (door 32), also used a n to 2 for time slot group number ⁿDecoder (decoder 33).Always the divide into groups multiple of timeslot number of initial time slot in the group.For example, if the grouping of 8 32 time slots is arranged, that is just 0,32, and 64,96,128,160,192, the 224 time slot places beginning, continuity moves 32 time slots.

Power for non-two, in order to obtain to decipher the desired number of time slot, deletion is about the design of next two high order power.Such as, for the decoding of 14 time slots, the Y15 of decoder 33, Y14 output are not used in module among Fig. 5 A, except for will forbid TSIN bus driver 35 when Y14 or Y15 output signal are 1, must these two outputs are anti-phase, and be connected to and door 34 additional input end on.These two remaining time slots can be used only needs the module of two time slots to get on.

In major part is arranged, comprise among the embodiment that the present invention recommends, always wish to utilize evenly subscribers feeder card module that the time slot expansion is distributed across whole 125 microsecond frames, do like this than resemble be strapped in Fig. 5 B much better together.Can make module between each time slot, have the more time to go to carry out partial operation the time slot expansion, so just reduce the cost of module, reduce its complexity.

The expansion time slot is easy to accomplish, on the counter 31 in Fig. 5 A, QA-QD output and QE-QH output is exchanged as long as the A-D input is imported exchange with E-H again.After the exchange, 0 group of time slot contains time slot 0,16,32 ..., 240, and 1 group of time slot will be 1,17,33 ... 241, by that analogy.

In the operation of the time slot addressing decode of Fig. 5 and Fig. 5 B, it is simultaneous exactly coming in and going out the time slot of inside modules of both direction, even if also be like this under above-mentioned spread scenarios.Yet the signal in the module takes place and receiving lines but requires time slot that enters and the time slot of going out not to take place at one time, most likely requires the two stagger a time slot (488 nanoseconds) or half time slot (244 nanoseconds).

The dislocation of 1 time slot almost can both obtain in the circuit of time slot decoding arbitrarily, and way is to be in due course to use trigger or register delay circuit on the line.Relatively difficulty is the dislocation of 1/2 time slot.But in the present invention,, be easy to obtain the dislocation of 1/2 time slot because quarter-phase clock (TCLKA, TCLKB) is used in exploitation once more.Particularly, referring to Fig. 5 A, if clock TCLKA is by starting the TSIN drivers with door 34, counter 31 and TSOUT register 36 just can be by clock TCLKB regularly so, vice-versa.The EN2 of decoder 33 input can be by TCLKA, TCLKB starting, also can be started simultaneously by two clocks during the decoder output of using inside modules if any special requirement.

Like this, each subscribers feeder card module all has the switch 40 of some, and referring to Fig. 5 A, the tagmeme able to programme that perhaps has some in the module time slot decoding circuit is then even more ideal.This quantity is corresponding with the scale of time slot group, that is to say, be consistent with the number of timeslots of serving this subscribers feeder card module port.In addition, except reduce the quantity of the time slot grouping addressing circuit in the module as far as possible, the present invention has also set the value of switch 40 or tagmeme able to programme, makes different time slot packet allocation give different subscribers feeder card modules, even if disparate modules needs the time slot of varying number.

Such as, supposing has following module, and all modules all must be with the time slot (can think that A group time slot is full of) of B group for simplicity:

Module takes the address assignment address assignment

1# 2# is counted in the title crack

P 16 0-15 192-207

Q 64 64-127 0-63

R 16 128-143 208-223

S 64 192-256 64-127

T 64 ？？？ 128-191

If time slot distributes in order, and every group of time slot must be from such time slot, this time slot number be the multiple of this group scale number, as previously mentioned, the situation that module P, Q, R, S and T are assigned with is shown in address assignment 1#.Module T does not have 64 continuous time slot can supply to utilize.But, in whole one group of 256 time slot, also have the time slot of 96 dispersions altogether to utilize.

So the present invention can programme the addressing of time slot group on each module directly or indirectly with processor.In this embodiment of the present invention, each is organized time slot and can directly programme with the microprocessor on each subscribers feeder card module, there is a central control module processor to give subscribers feeder card module microprocessor with information, and orders it to carry out the best addressing of time slot group by the signal bus that in Fig. 8, will illustrate by one.

The central module microprocessor is at first to specify maximum group when addressing time slot group.Follow second largest group of assigned timeslot number again.Carry out so step by step till the group of minimum is also designated.Use this way, the time slot group can obtain addressing the most effectively.Address assignment 2# is exactly an example.This program that the central module microprocessor is used, the people that this respect is skilled in technique can write out at an easy rate.

As shown in Figure 3, each module has four module's address connector line MOD3-0.These connectors can property-line 41 ground connection, perhaps disconnect with a kind of different pattern on each module position.Like this, 4 module's addresss of 16 different " hardware connections " are just arranged in principle, so that discern each subscribers feeder card module.(clearly, can use some attached module address connectors,, just five lines be arranged) for 32 addresses so that more module's address is provided.

When each module had 4 different bit address, the typical practice of addressing building block technique in the past was to have 4 module to select bus, and central control module is sent into a selected module's address on this bus.4 bit comparators on each module select module bus to compare in the address (MOD3-0) of the hardware connection of institute in if having time with itself, look at whether it is selected.This technology in the past has a shortcoming, and promptly module selects the number of bus many, and one 4 bit address needs four, and required number of buses is more when above if any 16 module's addresss.

Module among the present invention selects bus only to comprise a signal line 26.MS signal on this line 26 can be nearly 512 different module addressings.In our the present preferred embodiment of introducing, this MS line 26 can be 32 different module addressings.

These clocks of TCLKA, TCLKB and TFRM can be determined 512 single time slots together.For MS line 26, the number of " selection time slot " can be less.The number of this " selection time slot " just in time is that number of time slot is by 16 remainders except that gained.Like this, time slot A-1, A-17 and per the 16th time slot from the time slot A to A-241 also are to select time slot A-1.In this arrangement, always have 32 and select time slot, be numbered A-0 to A-15, and from B-0 to B15.If time slot repeats in per 125 microseconds, repeat once about " selection time slot " then per 8 microseconds, because select the number of time slot less.

In the present invention, if the MS signal is " 1 " between corresponding " selection time slot ", then chooses a module, otherwise do not choose this module.By place a suitable model on MS line 26, central control module just can be selected one or several subscribers feeder card modules, also can not select, and also can select whole subscribers feeder card modules.This is an improvement to conventional art, because the practice in the past is to have only 4 parallel buses, can only select user's card module with it very dumbly.

Be the selection logic diagram of each module shown in Fig. 6 A, counter 42 is 4 binary counters, and this counter has output QA to QD, increases progressively during rising edge that this counter occurs in CLK input.But, LOAD on rising edge CLK input is 1, the signal that counter 42 will be packed into and be occurred on the input of A to D.D type flip flop 43 and inverter 44-46 are the logical circuits of standard.

The sequential chart of indication circuit is used for illustrating the work of circuit among Fig. 6 B.Every frame once, counter 42 is loaded into the complement code of module's address numbering, and the module's address numbering obtains from the MOD3-0 connector.Rising edge at each TCLKA or TCLKB clock on the counter 42 increases progressively, and selects which clock by switch 47.On per the 16th rising edge, counter 42 is (counter " state " is the numerical value on output QD, QC, QB, the QA) promptly from 1111 state exchanges to 0000 state.Above-mentioned conversion, especially 1 to 0 conversion on output QD can produce 0 to 1 conversion at the outlet terminal of inverter 45.And this conversion itself counts the existing value of MS line 26 in the d type flip flop 43.Whether the output signal MODSEL of this trigger can indicate this module selected.It is stable till from 1111 to 0000 conversion next time, just after 16 clocks circulations (approximately being 8 microseconds) that this MODSEL signal keeps always.

" the selection time slot " that carry out 1111 to 0000 conversions depends on the module's address numbering.Such as, if the module's address of MOD3-0 number is 0010, switch 47 has been selected TCLKA, so above-mentioned " selection time slot " is exactly A-2.Like this, the MS signal in selecting time slot A-2 has just determined whether this module is chosen in next 8 microseconds.

Utilize two positions of switch 47 just might select 32 different modules.In the embodiment that the present invention recommended, do not use the switch 47 of machinery.On the contrary, the half of subscribers feeder card module the input of its counter 42 clocks is received that TCLKA goes up and in addition the input of half receive on the TCLKB.So, the number of module's address just is increased to 32, from A-0 to A-15 and from B-0 to B-15.

Also need to prove and under the situation that does not change spirit of the present invention, also have some reduction procedures.To should be mentioned that especially, as long as just can save inverter 44,45 simply to the 0-2 bit inversion in the module's address of hardware connection number.Therefore, it is cheapest that module is selected the preferred embodiment of circuit, is made up of 4 inexpensive digit counters 42 and a d type flip flop 43.

The circuit that drives MS line 26 with central control module has a variety of, be a circuit in the central control module shown in Fig. 6 B, sort circuit can be by various situation programmings, an optional subscribers feeder line module, can not select yet optional whole subscribers feeder card module yet.Counter 50 is similar to the counter 42 among Fig. 6 A, but it has only when EN is input as 1 and just counts.The FFRM signal is a frame signal similar to TFRM, but this signal will occur 16 times, that is to say, its not only occurs when time slot 255, also appears at time slot 15,31,47 ... up to 255 the time.This clock is can be at an easy rate by producing TCLKA; The clock circuit of TCLKB and TFRM generates.

A microprocessor 16(in signal MODCEN, MODENA, MODENB and MODN3-0 among Fig. 7 and the central control module is in Fig. 8) be connected, this central control module is to select the microprocessor 61 of subscribers feeder card module can control following these signals:

Do not select any module, MODENA and MODENB are set in 0.

Select all modules, MODENA and MODENB are set in 1, MODEN is set in 0, MODN3-0 is set in 0000.

Select modules A-i, MODENA and MODCEN are set in 1, MODENB is set in 0, and MODN3-0 is set in the i of binary representation.

Select module B-i, MODENB and MODCEN are set in 1, MODENA is set in 0, and MODN3-0 is set on the binary form registration of i.

By this selection of being said above adopting, only need add with two bars circuits 27,28 among Fig. 3, MI(input information) and MO(output information) a very effective serial signal bus just can be made.Shown in Figure 10 is central control module and the circuit that the subscribers feeder card module all needs.On all other subscribers feeder card modules, all use this subscribers feeder card module circuit.UART60, the 70th, general universal asynchronous receiver/transmitter (UART), they send data output end and RXD(reception data at its TXD) input transmission and reception serial information.Under many circumstances, the effect of UART is integrated together with a single chip microcomputer, and what make such as the Intel Company of Gary Fu Niya Santa Clara 8031 is exactly an example.Other element of module among Fig. 8 all is the gate and the parts of standard.

System shown in Fig. 8 compares with the signal bus of the general associated line that designing institute is in the past used, and has some significant advantage.In the signal bus of general associated line, the TXD output signal that the UART that controls from central authorities comes out directly is flowed to the input RXD of all other module UART, the TXD output of all other module UART is that directly " with being connected " drives the RXD input of central control module UART simultaneously, and does not utilize the door 62,61 of MODSEL.The bad result of this practice is:

When central control module transmits information, all modules all must listen to and determine this current information whether at it.

Must there be some technology to be used for preventing that two or several modules from driving MI line 27(simultaneously otherwise their information will be obscured together).General technology is that inquiry, mark are by reaching conflict inspection.

Indivedual malfunctioning modules may be on the MI line information of confusion reigned, thereby make the signal bus of each module all ineffective.

In the present invention, central control module can be selected its desired module of conversation with it at any time.Central control module is to select circuit to realize above-mentioned functions by the module of using the front to say.When selecting some modules, its MODSEL signal is 1.So its TXD UART output is driven on the MI27 by an open-collector NOT-AND gate 62, the signal on the MO line 28 is received on its RXD UART input by an OR-gate 64 simultaneously.If this module is not chosen, the output of AND gate 62 inoperative (floating) so forces RXD UART input to be 1 simultaneously, and this is " free time " state to a common UART.

This ability that central control module can select some specific modules to converse has the unexistent benefit of signal bus system of a lot of general associated lines:

When central control module with the conversation of some particular modules the time, interference-free their UART one by one of other module is in " free time " RXD state.

It is flat-footed selecting the mechanism of which module drive MI line 27.Central control module is selected a subscribers feeder card module, and this module is uniquely can drive MI line 27.

Central control module can not be affected because the hardware and software in individual user's line card module is malfunctioning.Even a module " job insecurity " and the information of confusion reigned on the TXD of its UART output are constantly arranged, central control module only otherwise selected this module just.

Fig. 8 show microprocessor 71 on the subscribers feeder card module be how with central control module on microprocessor 61 conversations, this microprocessor may be the Motorola type equipment of Arizona, a Phoenix.Each microprocessor 71 is handled the operation of itself subscribers feeder card module.The operation of whole Private Branch Exchange PBX PBX is handled in the little processing of central authorities 71, comprises the dispersion time gas exchange that the time slot addressing said the front and back will be said here.Should be understood that in the microprocessor 61,71 each also is coupled with the module of other parts.The particular design of module is depended in this special connection.

Another advantage of the present invention is aspect inquiry.In a signal system with a main controller (central control module) and a plurality of controlled device (other module), main controller can at any time be got in touch with controlled device, and controlled device can only be got in touch with it under the situation that main controller allows.So main controller must have some ways to know has controlled device to want transmission information to give it.Two ways are generally arranged.

Inquiry.Main controller sends information to each controlled device periodically, asks what information whether this module have to give it.

Request sends (RTS) circuit, and each controlled device all has its own logical signal, is called RTSi, and i is meant that module numbers here, and these numberings all send back to main controller by bus.Will transmit when a controlled device has information, it just sends this signal, and simultaneously, main controller is periodically checked all RTS circuits, and converses with that module of keeping the RTS signal.

Inquire about this way and need not to increase extra hardware, but this method is slow and will send and receive the inquiry information (normally coming to nothing) of changeing extraly.The RTS method is faster, while added burden is few, and (controlled device can not be interfered, unless it really has any information to send), but this method needs more hardware, and may also need a non-parallel bus so that the RTS line is drawn back central control module.

RTS of the present invention system does not need extra hardware.As require to send information.A subscribers feeder card module only need be placed continuous " a 0 " logical value in the TXD of its URAT output, wait the reaction of central control module then; This continuous " 0 " is exactly so-called " interruption " state in general UART.

In a common associated line system, the MI line 27 of each module all is braked if a module is sent a continuous interruption.And in the present invention, have only module of having selected that requirement to send when central control module just " interruption " can occur later on.Therefore, central control module can be interpreted as " request sends " to this " interruption ".

In case find to have " interruption ", the module that the microprocessor 61 of central control module just sends for request is sent an information, allows it that the information that will send is sent here.In this, the module that request sends is activated, and eliminates that " interruption " and its information is delivered on the MI line 27.

Another kind method is that central control module can be regardless of this " interruption " but force selected module to take orders.Under any circumstance, when conversing with central control module, a module is removed " interruption " always, has only when it also has information to send just after conversation and sends " interruption ".

Another effect of signal bus among the present invention is to reset.In any digital system, must be when electric power starting system reset to one known state.In addition, some other the time, also want to make system reset, such as when system because certain temporary transient error, and when in operate as normal, having entered unknown state, just need make system reset.For this reason, most systems all are provided with reset button, watchdog timer and other devices.

All have on each module in the modular system of microprocessor, such as what talked about, such situation may occur here, individual modules enters unknown state and the remainder operate as normal of system.In Private Branch Exchange PBX and other system, wish very much device that defective module is resetted and other modules are resetted of installing, because this resetting can cause undesirable work loss usually.

In module selective system of the present invention, be equipped with a new equipment that can module be resetted.As Fig. 3 and shown in Figure 8, have only on (RESET) signal online 29 that resets to be connected to all modules.This signal is driven by an output port position of the microprocessor in the central control module 61.On each subscribers feeder card module, this signal is by an AND gate 65 this area MODSEL signal and it to be combined with each other so that a regional MODRESET signal is provided.

As a certain module is resetted,, send the RESET signal then just central control module is selected this module.Central control module must be noted that " removing selection " (deseleting) this module in the past will " resetting " (RESET) signal eliminate.Such as, central control module may have been selected the another one module, and module will be conversed with it on signal bus.Be noted that in addition having central control module MS drive circuit shown in Figure 7 just might select all modules, make all modules to reset simultaneously, so as rapidly, recovery system work fully.

At last, the present invention can also make time slot bus 24,25 carry out work to disperse exchanged form.Before this, the time slot bus 24,25 among Fig. 3 is all according to concentrated exchanged form narration, shown in Fig. 2 A.Signal bus is provided in the present invention, and or rather, MI line 27, MO line 28 and MS line 26, and relevant circuit make the present invention work in the mode of disperseing exchange.

Rely on microprocessor 61, central control module just can be programmed preface at an easy rate, needn't drive TSOUT bus 25 in certain time slot.By MS line 26, microprocessor 61 can select specific user's line card module and by the microprocessor 71 on this card module, one or several time slot on the TSOUT bus 25 has been assigned to that subscribers feeder card module.Like this, except TSIN bus 26, the subscribers feeder card module can also utilize TSOUT bus 25, transmits PCM speech and data-signal.Microprocessor 61 can also be given other subscribers feeder card module other time slot addressing on the TSOUT bus 25.

Equally, microprocessor 61 also can be given selected subscribers feeder card module the time slot allocation on the TSIN bus 24, so that receive PCM speech and data-signal.So, the time slot bus is divided into two, one is used for transmitting output signal (TSOUT bus 25) and another situation that is used for transmitting input signal (TSIN bus 24) has not just existed.By the operation shown in Fig. 2 A, Private Branch Exchange PBX of the present invention can also carry out work in the mode of the exchange of the dispersion shown in Fig. 2 B.Certainly, TSIN bus 24 drive circuits among Fig. 5 A and TSIN bus 25 drive circuits can improve at an easy rate becomes two-way transmission and mode that can adopt the dispersion exchange.

The embodiment that the present invention has been recommended has done in detail and comprehensively and has introduced above, also has various improvement, change and suitable thing and be used under the situation that does not break away from spirit of the present invention and scope.Therefore, above-mentioned narration and explanation should not thought a kind of restriction to the scope of the invention of determining in the claims.

Claims (28)

1, a digital branch exchange is characterized in that comprising column element down:

Some modules, each module have at least a port to be used for and above-mentioned Private Branch Exchange PBX switching signal;

The circuit that some are parallel is used for communicating between above-mentioned module;

The clock apparatus that is connected with above-mentioned module, be used for determining the required number of time slot of above-mentioned signal on above-mentioned communication line, be used for starting above-mentioned module simultaneously and in predetermined time slot part, converse, thereby a more than module can be conversed in same time slot simultaneously.

2, according to the digital branch exchange of claim 1, it is characterized in that above-mentioned clock apparatus is made up of a plurality of clocks, each clock with same predetermined frequency work and and the another one clock between a phase difference is arranged, at least one clock coupling in the module that each is above-mentioned and the above-mentioned a plurality of clock.

3,, it is characterized in that described clock is two, the phase difference between them is 180 ° according to the digital branch exchange of claim 2.

4, according to the digital branch exchange of claim 1, it is characterized in that above-mentioned clock apparatus comprises that the clock of signal takes place with predetermined interval an energy, this signal can make the above-mentioned time slot of some become frame in above-mentioned interval, and each module comprises here:

One is used for giving the device of above-mentioned module one group of one or more time slot allocation in a framing signals interval;

A device that is coupled with above-mentioned distributor and above-mentioned clock apparatus is used for for each time slot of distributing to above-mentioned module a single signal taking place; Thereby respond above-mentioned single signal, above-mentioned module can be conversed in above-mentioned distributed time slot.

5, according to the digital branch exchange of claim 4, it is characterized in that above-mentioned distributor is to be made up of one group of switch, the numerical statement of switch is shown in the interior at interval time slot group number of a frame signal, and the layout of above-mentioned switch is represented special one group in the above-mentioned frame signal interval.

6,, it is characterized in that above-mentioned one group of form that switch is the batch processing position according to the digital branch exchange of claim 5.

7,, it is characterized in that above-mentioned single signal generation apparatus comprises according to the digital branch exchange of claim 5:

Respond a counter of above-mentioned frame signal and above-mentioned two clocks, when each frame signal begins at interval, be recovered to initial condition and from the above-mentioned clock to each time slot counting, above-mentioned counter sends output signal and represents said counting;

With the logic device that above-mentioned counter is coupled, be used for sending a logical combination of an above-mentioned counter output signal of signal indication;

Respond the decoder of above-mentioned counter output signal and logic device signal, be used for producing one and the corresponding single signal of above-mentioned output signal.

8, according to the digital branch exchange of claim 6, it is characterized in that clock number when being that N, the time of preset frequency are T, the duty cycle of each clock will be less than (1/N) T, thereby can avoid occurring on above-mentioned circuit the signal of conflict.

9,, it is characterized in that N is 2, and the duty cycle of each clock is 1/3T according to the digital branch exchange of claim 8.

10,, it is characterized in that described each module comprises according to the digital branch exchange of claim 1:

The device of signal takes place, and is used for discerning this module;

With the device that above-mentioned identification module and above-mentioned clock apparatus are coupled, be used for selecting a time slot into above-mentioned module;

Thereby in the time slot of above-mentioned selection, a signal with line that above-mentioned time slot selection device connects in an initial predetermined circuit on to above-mentioned module addressing.

11,, it is characterized in that described each module also comprises a device that is coupled with above-mentioned recognition device and at first predetermined circuit, is used for sending a module select signal after above-mentioned module is addressed according to the digital branch exchange of claim 10.

12,, it is characterized in that described each module also comprises according to the digital branch exchange of claim 11:

Input/output device is used for receiving the signal data that comes from one group of scheduled circuit and to described line signaling data;

With the device that above-mentioned module selection unit and above-mentioned input/output device are coupled, be used for when above-mentioned module select signal occurs, above-mentioned input/output device being received on one group of predetermined circuit.

13,, it is characterized in that described input/output device comprises a universal asynchronous receiver/transmitter (UART) according to the digital branch exchange of claim 12; Comprise two lines with above-mentioned one group of predetermined circuit, one is used for transmitting the signal data that is received, and another is used for transmitting the signal data that sends.

14, according to the digital branch exchange of claim 12, above-mentioned input/output device it is characterized in that when will send signal data, this input/output device will produce an output signal, when above-mentioned selection signal occurs, above-mentioned output signal just is sent on one group of above-mentioned predetermined circuit, represents the state of above-mentioned input/output device.

15, according to the digital branch exchange of claim 10, it is characterized in that each module also comprises a device that is coupled with above-mentioned recognition device and second scheduled circuit, when being used for according to this module addressing on above-mentioned second scheduled circuit one signal above-mentioned module is resetted.

16, digital branch exchange with central control module and at least one subscribers feeder card module, this subscribers feeder card module has a port at least, can deliver on the above-mentioned switch and from switch by this port communication signal and to send here, this central control module and this subscribers feeder card module are coupled with a bus; It is characterized in that: this bus has three groups of circuits, first group of circuit is used for determining time slot, second group is used for transmitting signal of communication between above-mentioned central control module and subscribers feeder card module, the 3rd group of circuit is used for transmitting signal message between above-mentioned central control module and subscribers feeder card module, and above-mentioned subscribers feeder card module comprises:

Be used to produce the device that signal is discerned this module;

With above-mentioned identification signal generation device and above-mentioned first group of device that circuit is coupled, be used to above-mentioned module to select a time slot; With above-mentioned time slot selection device and the 3rd group of device that circuit is coupled, be used for coming above-mentioned module addressing according to a signal that during the time slot of selecting, on above-mentioned the 3rd group of circuit, occurs.

17, a kind of digital branch exchange that number of modules is arranged, each module on this digital branch exchange have at least a port to be used for that signal sent to above-mentioned Private Branch Exchange PBX and from this switch received signal; Some communication lines are used for transmitting signal between above-mentioned module; Be used for determining the number of time slot of the signal on above-mentioned communication line with the clock apparatus of above-mentioned module coupling; Also have a central control module that is coupled with above-mentioned communication line, this control module sends signal to first group of module on the communication line; This control module receives module from second group of communication line from the signal of this module, and this control module sends signal to the 3rd group of module on the communication line and receives signal from this module; It is characterized in that:

Above-mentioned control module comprises a device, this device be used for by it in predetermined time slot to above-mentioned first group of line signaling, this device also is used for producing control signal and is illustrated in ending of control module on above-mentioned the 3rd group of circuit; In addition, above-mentioned module also comprises the device of the above-mentioned control signal that is coupled with above-mentioned the 3rd group of circuit and responds, be used for transmitting and receive the signal on above-mentioned first group of circuit, also be used in predetermined time slot, receiving and transmit the signal on above-mentioned second group of circuit.

18, the digital branch exchange according to claim 17 further comprises:

One versabus, this bus comprises first, second and the 3rd group of above-mentioned many communication lines, an one group of clock line and a framing signal line, wherein said versabus allow and are convenient to the operation of concentrating or disperseing of above-mentioned central control module and described other module.

19, the digital branch exchange according to claim 18 further comprises:

The physical location that on described bus, disperses, above-mentioned module connects in above-mentioned discrete physical locations and above-mentioned bus;

The recognition device that connects with above-mentioned each physical location on above-mentioned bus, this recognition device provide the location address code of the physical location that a representative connects with above-mentioned module to the module that connects with above-mentioned bus in this position; With

Distributor in each above-mentioned module, responds above-mentioned location address code and distributes set of time-slot in a framing signals interval, thereby come this module is selected and addressed according to the physical location that connects with module.

20, according to the digital branch exchange of claim 19, it is characterized by: described location address code is to be provided by one group of switch or one group of position of programming; The number of one described switch is represented the length of described location address sign indicating number; The bit of wherein above-mentioned representative address code distributes above-mentioned time slot group according to the described physical location that connects with above-mentioned module on aforementioned bus.

21,, it is characterized in that described module further comprises a programmer, thereby the bit that is used for changing above-mentioned programming changes above-mentioned time slot group according to the digital branch exchange of claim 20.

22,, it is characterized in that described module further comprises according to the digital branch exchange of claim 21:

Resetting means, a reset signal that responds on above-mentioned the 3rd group of circuit makes above-mentioned module reset, above-mentioned resetting means can make the bit of above-mentioned programming reset to a known state.

23, according to the Private Branch Exchange PBX of claim 16, wherein be characterised in that: above-mentioned addressing apparatus carries out addressing according to a signal that occurs on the at first predetermined circuit of one in the 3rd group of circuit.

24, according to the digital branch exchange of claim 23, it is characterized in that; Each module further comprises: with described identification signal generation device and the described initial predetermined joining device of circuit, be used for producing a module and select when above-mentioned module is addressed.

25, according to the digital branch exchange of claim 24, it is characterized in that; Each described module further comprises:

Input/output device is used for a scheduled circuit from the described circuit and receives or send signal data to it; With

With the device that described module selection unit and above-mentioned input/output device connect, be used for when above-mentioned mode select signal occurs, will going up input/output device and above-mentioned preset lines group and connect.

26,, it is characterized in that above-mentioned input/output device comprises a universal asynchronous receiver-transmitter according to the digital branch exchange of claim 25; Comprise a pair of circuit with described scheduled circuit group, a circuit is used to transmit the signal data of reception, and another circuit is used to transmit the signal data that sends.

27, according to the digital branch exchange of claim 25, the communication data that will send is arranged in the wherein said input/output device, described input/output device produces an output signal, when described module select signal occurs, this output signal is placed on the described scheduled circuit group, indicates the state of this input/output device.

28, according to the digital branch exchange of claim 23, it is characterized in that each module further comprises: a device that connects with the above-mentioned identification signal generation device and second scheduled circuit is used for according to the signal on described second scheduled circuit above-mentioned module being resetted when described module is addressed.

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