CN1078029C - Method for arbritrating for access to control channel in data bus system - Google Patents

Abstract

A data transfer system is disclosed which includes a plurality of nodes coupled together by a ring bus transmitting at least a bit of a control channel in each of successive bus cycles. Nodes compete for access to the control channel according to the following method. First, an encoded preamble is generated, having a number of successive states, each state being one of a superior and an inferior state. Second, the control channel bit in a bus cycle is set to a superior state, representing a first state of the encoded preamble. Then, for each of succeeding bus cycles a control channel bit is received. If the preceding control channel bit was set to an inferior state, and the state of the received control channel bit is a superior state, then the node drops out of contention for the control channel and for the remainder of the arbitration cycle sets the control channel bit to the state of the received control channel bit. If the received control channel bit is the same state as the last state of the encoded preamble, then the node acquires access to the control channel. Otherwise, the next state of the encoded preamble is determined, and the control channel bit is set to the next state of the encoded preamble.

Description

A kind of referee method to the visit of a control channel in the data bus system

The present invention relates to data highway system, relate to a kind of ring bus data communication system especially.Data communication system, digital video signal processing system for example, high speed processing data and correspondingly require the bus system of high bandwidth to be used for data to transmit.For example, the data rate of the digital of digital video data of mpeg format is 4 to 8 megabit per seconds.A kind of bus system based on the data of packetizing can provide enough bandwidth.But, realize that the hardware and software of the treatment system of packetizing may be more expensive, make the consumer electronics is not conformed to reality.In addition, packet bus can require excessive " expense " such as the packet transaction time delay, but it can not provide mpeg data to transmit desired high data rate.

A kind of high data rate data transmission bus, it can construct and not need very high expense with a relatively low expense, and this is desirable to the interconnection consumer electronics.

According to one aspect of the present invention, the data transfer bus of a kind of BeeBUS of being called (BBUS) transmits data in the bus cycles, and each cycle comprises at least one position of a control channel.BBUS is a kind of high data rate bus system that digital of digital video data transmits that can be used for.More particularly, the BBUS system is that a kind of total capacity is the bus of the Time Division Multiplexing of 88 megabit per seconds, comes pellucidly data to be sent to a destination node from a source node on the bus with it.BBUS is by sending the word running of 9-position serially from node-to-node on ring.Internodal is to keep by the bus cycles that send 88 9-position words synchronously, and the initialization word of each bus cycles is a bus cycles synchronization character.Because require it is connected to a kind of consumer electronic devices of the consumer electronics bus (calling CEBUS) of technology in the past, the BBUS system comprises the control channel of a compatible CEBUS.Data of carrying the control channel that is used for compatible CEBUS of bus cycles synchronization character.BBUS is designed to be used for carrying eight data channels, and they can classify as piece with the needed capacity of the combination in any that a plurality of channels and channel capacity are provided, as long as total channel quantity is equal to or less than 8, and total partition capacity is equal to or less than 88Mbs.

The control bus that is included in the compatible CEBUS in the BBUS system has a kind of not relating to transmitting the message structure of arbitration.Each equipment has a pre-assigned capacity for surpassing the control channel time slot of 10kbs.Each equipment has the channel capacity that receives message from 31 miscellaneous equipments simultaneously.But, see that receiving equipment once only handles a message.Thereby arbitration will be by receiving equipment, rather than transmitting apparatus is carried out.Receiving equipment comes processing messages in the mode of a circulation, next message.Because message-length is to be approximately 32 bytes, all control channel message will send with this regular length, and all message will begin with identical control cycle time slot.This time slot is that basic operating system is synchronous.Its per 32 control appliance time slot * 32 message time slot takes place once, and approximately 8ms will explain hereinafter.Thereby control channel message can send one every 8ms.(16 device-to-device message can send simultaneously).To the CEBUS control messages approximately is 25ms.

As mentioned above, BBUS transmits information with each bus cycles (comprising 88 9-position words) ground on the control channel of compatible CEBUS.This requires receiving equipment that message is refused, and can cause the possible grid locking (grid lock) and the transmission of a plurality of message.Preferably adopt a kind of control channel transfer approach that alleviates these problems.

Abide by another aspect of the present invention, each node in a kind of like this data communication system competes to rob visit to control channel according to following method.At first, produce the preamble of a coding, it has a plurality of continuums of states, each state or be high-grade state or be the inferior grade state.Secondly, the control channel position in bus cycles is set to high-grade state, first state of the preamble of presentation code.Then, for each continuous bus cycles, receive a control channel position.If last control channel position is to be set to the inferior grade state, and received control channel position is high-grade state, so this node withdraw to control channel compete rob, and all the other time control channel positions of this arbitration cycle are set to the state of received control channel position.If the final state of this coding preamble is to transmit in the previous bus cycles, and received control channel position is and the identical state of final state of the preamble of encoding that this node obtains the access right to control channel so.Otherwise, the NextState of preamble of coding is determined, and the control channel position is set to the NextState of the preamble of this coding.

In the accompanying drawings:

Fig. 1 is a block diagram of abideing by a kind of data highway system of principle of the present invention;

Fig. 2 is the block diagram of signal along the form of the data that node cycle sent illustrated in Figure 1;

Fig. 3 is that prior art is used for a block diagram with the layout of loop configuration interconnecting nodes;

Fig. 4 comes the block diagram of a kind of method of interconnecting nodes with implementing a kind of loop configuration of the present invention;

Fig. 5 is a block diagram that comes the connected node circuitry needed with the input and output cable;

Fig. 6 is the flow chart of abideing by the operation of a data bus system of the present invention;

Fig. 1 is a block diagram of abideing by a kind of data highway system of principle of the present invention.5 nodes, node A, Node B, node C, node D and node E are by having the bus interconnection of loop configuration as shown in Figure 1.Data are sent to next node the ring with the form illustrated from a node in Fig. 2.

In Fig. 2, data word is represented by the series of rectangular of figure middle and upper part.Basic data word in the system comprises 9.8 (bytes) are payload, and 1 as link level control.The 9-bit data word that transmits in bus cycles has 88.Adopting the bit rate clock is 100MHz (being to be 10 nanoseconds in the cycle), and each 9-position word is that 90 nanoseconds are long.Thereby the essential bus cycle in the system was 7920 nanoseconds, or the value of 88 times nine 10 clock cycle nanosecond.Send a synchronization character every 7920 nanoseconds by a bus cycles master.This just provides the payload or 10,984 of 87 data words of per 7920 nanoseconds, 848 byte per seconds.Thereby maximum BBUS data rate is 87878787.88 megabit per seconds.Data word in the data flow is distributed in 8 channels.Each data channel per 0.720 microseconds (90 nanosecond * 8 channel) receive a time slot and send a word.Thereby data channel is the channel with protocol-independent, and it has constant time delay and the capacity of every 11Mbs is had the shake that is less than 1 microsecond.

With reference to Fig. 2, first 9-bit data word of bus cycles is synchronization character (SYNC).Thereafter data word is carried the data of channel 1 (CH1).Transmit the data that the data word of data is carried channel 2 to 8 (CH2 is to CH8) successively thereafter.To each channel, this one-period of data word repeats 87 remaining in these bus cycles time slots.

As describing a control channel of distributing to compatible CEBUS of synchronization character hereinafter in detail.Thereby this control bus has the peak data rate higher slightly than 126 kilobits/s.A little higher than 10 kilobits of the throughput of this control channel/s, it is roughly identical with CEBUS, and this is to adopt the CEBUS CSMA-CD referee method of arbitrating the access right of bus owing to be coupled to the equipment of CEBUS.

The basic physical of BBUS and connectedness electricity are a kind of daisy chain type rings that has an input and an output at each equipment or device.Fig. 3 is a kind of block diagram of layout in the past of the annular structural node of interconnection.Each node among Fig. 3 comprises an input connector (in the signal of the lower left of each node), and an out connector (in the signal of the lower right of each node).The out connector of first cable connected node A and the input connector of Node B.Another root cable, in a similar manner, the input connector (not shown) of the out connector of connected node B and node C, and the input connector that the rest may be inferred from the out connector of a node to next node.Last node shown in Fig. 3 is node E.For forming a ring, a cable is connected to the input connector of node A from the out connector of node E.

For avoiding making the final link in the daisy chain to connect final node and first node, the data in the backhaul pathways can be time-multiplexed with forward path.In the another kind method, to reverse path, each cable can comprise one group of electric wire.A kind of method in back is preferred because time-multiplexed oppositely and the forward path active volume that reduced by half.

Fig. 4 implements the interconnect block diagram of method of the node in a kind of loop configuration of the present invention.At Fig. 4, each cable comprises from a node to the necessary electric wire of next node forward path, and the electric wire that is used for Return Channel from the out connector of final node to the input connector of first node.When the reverse path electric wire is included in the cable, as shown in Figure 4, the BBUS cable of the embodiment of being illustrated requires 8 wires, four in each direction.Also comprise a ground connection/shielding conductor in addition, and comprising one, to be used to refer to a cable be the lead-in wire that is connected to this port.This lead-in wire connects earth connection/shielding conductor.

Fig. 5 is a block diagram that comes the circuit in the necessary node of connected node with the input and output cable.In Fig. 5, an input connector 20 receives a cable from a last node.This cable terminates on the plug 10, and receives electric wire that forms from a last node to the forward path of this node and the electric wire that forms the reverse path from last node to first node.In addition, as indicated above, a lead-in wire in the plug is coupled to a reference (ground connection) current potential.At data and the clock wire of input connector 20, be coupled to the first input end of first switching circuit 30 from forward path.An output of first switching circuit 30 is coupled to an input of an input serial-parallel shift register 40, and an output of input register 40 is coupled to the use circuit of the node (not shown) in a kind of known design scheme.

This use circuit (not shown) of node also is coupled to an input of an output parallel-to-serial shift register 50.An output of output register 50 is coupled to the first input end of second switch circuit 60 and an input of an out connector 70.Out connector 70 receives a cable from next successive nodes.This cable terminates in a plug 90.Plug 90 also comprises the electric wire of the forward path that is formed up to next node, and the electric wire that forms the reverse path from final node to first node.The output of output register 50 is coupled to forward path by out connector 70 and plug 90.

The reverse path electric wire is received at plug 90, and offers out connector 70.Be coupled to one second input of first switch 30 from the input electric wire of reverse path, and one second input that is coupled to second switch 60.An output of second switch 60 is coupled to an output at the reverse path of input connector 20.The output of second switch 60 is coupled to reverse path by input connector 20 and plug 10 then.

Input connector 20 and out connector 70 also have an electric wire that is connected to logical circuit 80.Be coupled to the lead-in wire of the input connector of the earth connection on the plug 10, and the lead-in wire that is coupled to the out connector 70 of the earth connection on the plug 90, all be coupled to logical circuit 80.This line input connector 20 and out connector 70 will by on draw and be height, and plug 10 or 90 will be drop-down by earth terminal be low.First and second corresponding switches 30 and 60 control input end are coupled in the control output end separately of logical circuit 80.

In operation, when a cable is inserted into input connector 20 or out connector 70, logical circuit 80 will detect this situation by the earth potential corresponding to this input connector of input end.With it input signal is delivered to input register and output register 50 is delivered to certain connector 20 or 50 from certain connector (20 or 70).For example, the first node in the chrysanthemum formula chain is not connected to the cable of its input connector 20, but the cable of the out connector 70 that is connected to it is arranged.Logical circuit 80 detects this connection.It regulates first switch 30 so that the input electric wire from reverse path at plug 90 is coupled to input register 40.Output register 50 is coupled to the reverse path of out connector 70.This first equipment is marked as the bus host node.

Similarly, last equipment in the chrysanthemum formula chain has the cable of the input connector 20 that is connected to it, but is not connected to the cable of its out connector 70.Logical circuit 80 detects this connection.It regulates first switch 30 so that the electric wire from forward path at input connector 20 is coupled to input register 40.It is also regulated on the electric wire of second switch 60 with the reverse path that output register 50 is coupled to input connector 20.Equipment in the middle of the chrysanthemum formula chain has the cable that not only is connected to input connector 20 but also is connected to out connector 70.Logical circuit 80 detects this connection.It regulates first switch 30 so that the electric wire from forward path at input connector 20 is coupled to input register 40.Output register 50 is coupled on the electric wire of reverse path of out connector 70.It also regulates second switch 60 with being coupled at the electric wire from reverse path of out connector 70 on the electric wire of the reverse path of input connector 20.The reverse path line is connected without any handling, and they only connect simply by equipment.This layout has reduced the operation of software control node to determine the needs of port connectivity.

If system considers not require cable shield, can adopt the RJ45 connector.In this situation, have or not cable will measure that electric current determines in the connector by readout clock on incoming line and at output line.In the present embodiment, this reading circuit will be connected between input connector 20 and the logical circuit 80, and be connected between out connector 70 and the logical circuit 80, and will provide logical signal whether to exist to logical circuit 80 to indicate bus to connect according to the described result of reading.The employing of RJ45 connector just allows to adopt a kind of relatively cheap cable and printed circuit board (PCB) (PCB) connector, and they may be desirable in consumer electronic systems.

Control channel agreement among the BBUS in CEBUS, adopt similar.Message structure and coding be identical with CEBUS in fact.This has just caused message of about every 25ms.Control channel will be described in detail hereinafter.

BBUS solves synchronously in the following manner.The problem that the ring-like bus of daisy chain type that links to each other through serial link has is that a node must start an initialize process and makes all nodal operations in synchronous regime, handles other initialization operation (as node serial number) then.If a node can become the uncontested main equipment of annular communication, just can greatly simplify this process.Accomplish this point by the bus master being defined as a node that does not have cable to be directly connected to its input connector 20, it can be definite like that as described above.The operation (will describe in detail hereinafter) that bus chief commander's initialization is following:

1) word is synchronous

2) cycle synchronisation

3) node serial number

4) delay compensation.

The form of the data word of BBUS is as follows.The communication of node-to-node is transmitted to the Bits Serial of next node from a node by a 9-position word and finished, and is as indicated above.This word reads in node input shift register 40, is sent to Output Shift Register 50, and (anticipating as shown in Figure 5) sends to next node then.

One of this word, for example, highest significant position is the link level control bit.An example of the definition of control bit is:

The 1=synchronizing information

The 0=payload.

For example, with reference to Fig. 2, each bus cycles begin locate to be inserted into the synchronization character (SYNC) that goes in the data flow, represented by the thick line square frame, comprise nine, this position expanded view as the below that bit data stream is represented is indicated.Highest significant position, represented as the thick line square frame among the on-site expansion figure, be a logical one position.On the other hand, carry the 9-bit data word of second channel 1 word in this one-period, have a highest significant position, also illustrated by the thick line square frame, it is a logical zero position, as indicated in the position expanded view below representing in data flow.

The initialization of daisy chain type ring bus with reference to above, begins synchronously with word.Word is to obtain by host node out connector 70 transmission synchronous codes (will describe in detail hereinafter) at it after system power-up synchronously.This host node begins to check the data of the synchronous character code of word that receives in its input connector 20 places then, find the loopback of this word synchronous code by the input register 40 (being 19 register in preferred embodiments) of checking it, until detect till this word synchronous code.It is a single 9-position word that following description is based on the word synchronous code.But the word synchronous code can be a sequence of two or more code words.After the word synchronous code was detected, it was synchronous just to have obtained word.

Time delay in such node cycle can be the non-integral multiple of 9-position word time, for example handles and the time delay relevant with cable.In order to regulate non-integer word time delay, input shift register 40 can comprise than the more figure place in the needed position of data word of storage.A kind of preferred embodiment as an example input shift register 40 comprises 19.In order to determine time delay, the data in input register 40 were checked in the integer word time.The time delay of a relative integer word time is represented in the position of the 9-bit synchronization word in the 19-bit shift register.This time delay is used for regulating the time of subsequent words.To adjacent node, except host node, clock is accompanied by data, and the time delay of its experience is identical with data, so there is not tangible regularly time delay concerning node.Because host node is based on a reference clock, the time delay of the whole ring of result is tangible to host node.The scope of time delay is subjected to the restriction of cable length and makes it be less than a word, unless in the time delay of the integral words of each node.The 19-position input shift register 40 of each non-host node can be used to, and provides additional needed word time delay in a kind of mode that will be described in more detail below.

Timing signal at each node provides as follows.Each node has two clocks.Input data from input connector 20 to input shift register 40 are by being shifted from the clock that strobe pulse extracts from being close to a last node, and this clock receives at input connector 20 (or be out connector 70 to host node).Each clock also has its inside quartz clock, drives its Output Shift Register 50 and its internal logic circuit with it.Thereby fast or slow point is possible to internal clocking than input clock, but must be corrected.In the input clock situation faster than internal clocking, the additional input clock cycle absorbs an additional input clock cycle by allowing input word additional position of displacement in input shift register 40.In the internal clocking situation faster than input clock, defined data cycle input time of internal clocking is expanded an extra clock cycle, imports data simultaneously and is shifted onto input shift register 40.The above-mentioned effect that has on speed accumulation, that ring dropped to the slowest intra-node clock.

When the end in the input cycle, one-period synchronization character (hereinafter describing) is read into node, and the bus cycles counter of each intranodal reaches synchronous by all cycle rate counters that resets.Thereby, each node experience state identical with last node, the time that postpones a word that receives adds the cable propagation delay.The definition status of each node, except host node, compensate this time delay by the receiving cycle synchronization character and obtain synchronously, for example, if total cable length is restricted to 10 meters, the total time delay by cable is 5 clock cycle at the order of magnitude of 50 nanoseconds or to a 100MHz clock so.Thereby that stores in cable is less than a word.Cable length can be long in the extreme when Return Channel also comprises, and when the design cable driver, the length of interpolation must be paid attention to.Also have, each node has a potential additional time delay, and it is less than a clock cycle.

Above describe and in the essential bus cycle illustrated in Figure 2, be 88 9-position words, or 88 * 9=792 clock cycle, if can design channel counter so that any data channel need be more than the 1Mbs capacity, the additional time slot in this basic channel data counter can distribute by this way so that make shake minimum.When a plurality of nodes adopted big or small arbitrarily data channel, for reaching this purpose, the capacity allocation task was assigned to application layer, and application layer is given to the task of each data channel assignment time slot.

Perhaps, each of 8 main channels that a kind of method that reduces the application expense is a preassignment 11Mbs capacity is less than every channel 1 microsecond to guarantee shake, as schematically shown in Figure 2.These 8 main channels can be distributed now simply, and channel counter will be designed these 8 main channels of distribution in 88 channel time slots, and this also can be shown in Figure 2.Each of 8 time slots is independent each other when determining shake, and can be distributed (but having only a node can use each of 8 channels) by each node independently.Control channel distributes and has the jitter value of 8 microseconds individually.

Synchronous and node addressing must provide certain characteristics about node.These features comprise word synchronous and bus cycles synchronous (they were all above being described), message synchronization, node addressing and the indication (all will be described below) that does not have data to occur in data slot.For this purpose, provide some special uses synchronous and addressing word, and by logical one is being identified them as the highest significant position in the 9-bit data word.In the present embodiment, the node number of system is limited within 32.Thereby needs come the address of recognition purpose ground node with only 5 positions (for example a position 3 that is numbered 0 to 7 byte puts 7 in place) of a byte.The sign of the address of source node is by the implicit expression of time slot, though this message if desired, can send in an additional byte.3 remaining (for example positions 0 to 2) of byte can be used to identify 8 special uses the various functions of definition synchronously and geocoding, as shown in table 1.

Function	The position
										Synchronously	0	1	2	3	4	5	6	7
	Free of data	1	0	0	0	0	0	0	0										0
Word is synchronous										1	1	1	1	1	0	1	0	1
	The device address	1	1	0	1	x	x	x	x										x
Cycle synchronisation										1	1	1	0	1	0	1	0	x
	Title	1	1	0	0	x	x	x	x										x
Resource allocation										1	0	0	1	D	x	x	x	x
	The ring time delay	1	0	1	1	x	x	x	x										x
Increase time delay										1	0	1	0	x	x	x	x	x
	Payload	0	D	D	D	D	D	D	D										D

Table 1

The first capable special-purpose synchronization character of code word 00H (being hexadecimal 00) of having illustrated of table 1, it is used to refer to certain particular time-slot does not have data to occur.This code word is necessary, because time slot always will occur in data flow, and the destination receiving node will monitor each time slot in the channel that is distributed.This word allows source node identification not have data to use to certain particular time-slot.

The second capable word synchronous coding of having illustrated of table 1 is above being described.The position 0 to 2 of this code word equals 111.

The third line of table 1 has illustrated to be used for the addressing coded word of regulation destination-address.When adopting the CEBUS agreement between node, to set up communication channel, do not need this code word.In this case, destination-address is encoded in control channel message, and this describes in industry standard EIA IS-60.Also have, node addressing coding zero keeps for broadcast to use.Host node is a node 1.Therefore, in this system, only allow 31 physical nodes.When a message will be broadcasted, the sender supposes that it will all be received by all nodes.Do not have affirmation, thereby the reception of message is uncertain.

The fourth line of table 1 has been illustrated a bus cycles synchronization character, as shown in Figure 2.In the bus cycles synchronization character, position 0 to 2 equals 110.The least significant bit of bus cycles synchronization character carries a position that is used for control channel, and illustrates with x in table 1, represents that it is a kind of " not paying close attention to " state.When channel counter=0 of mould 88, control channel has a time slot.If the node counts device of host node and message-length counter are 0, host node sends the cycle synchronisation code word.When receiving a bus cycles synchronization character, if it has lost synchronously, can reset its counter of each node.If do not detect the bus cycles synchronization character in a rational time, node just supposes that bus disconnects.

In one embodiment, can distribute to the work that control channel is named node.In this example, do not need to distribute title or number to give node.But in preferred embodiments, host node provides node serial number, is used as the part of initialize process.As indicated above, after word was finished synchronously, host node sent a name word command, and this is shown in the fifth line of table 1, even position 0 to 2 equals 100 and node address position (3 to 7) be set to 00001.Number in the node address position represents that the node address one of transmit leg node is host node in this example.Receive each node of name word command, increase the represented number in node address position, adopt the node address of this number, and the name word command of the node address that has it in the node address position is sent to next node as it.After it had circulated whole loop, when it received this order, host node stopped the circulation of this order.If a node has the time of delay (will be described in more detail below) of two words, it adds 2 to the represented number in node address position of the title word that is received by it.Thereby, the delay-slot of the node address of each node this node.

A link level resource allocation request of the 6th line display word of table 1.The link level resource allocation request equals 001 and can replace control channel message and be sent out by position 0 to 2 is set.2 adjacent data channels of each expression of position 4 to 7, for example the 7 pairs of total capacities in position are that 22Mbs represents time slot 0 and 1; Position 6 expression time slots 2 and 3, the rest may be inferred.Do not have ability to use the simple node of control channel to imagine for those and adopt link level resource allocation request word.When a such node required to visit a bus channel, it sent a resource allocation request to bus, wherein one corresponding 4 to 7 indicated desired a pair of channel, rather than transmission destination message addresses word.When a descendant node receives resource allocation request, if it and not conflict of this request, it does not carry out any change it is sent to next node.If node is using institute's requested resource, it is that position corresponding to the channel of being asked that is using 0, and amended word is sent to next node.Source node then must be from encircling this request of removal.There are not other fair rule or further arbitration.If this request be not changed to any channel loopback under 0 the situation, the node that sends request uses this channel.If this channel is unavailable, the node that sends request is attempted another in four pairs of channels.If do not have channel to use, this procedure termination.Behind long random delay, can recover this process.To the node of the channel of wanting to use longer session and the minority simple node that does not have the control channel ability, can consider to ask method to the use of data channel.

The 7th row signal ring delay adjusting word of table 1, its meta 0-2 equals 011.Usually, each node must be removed it and be placed on this message on the ring.It must know on ring the length with the time delay of whole word time for this reason.This must be determined in initialize process by host node.Host node supposition time delay is at least the quantity of node in the system.Host node is counted the quantity of title order (above describing) desired clock cycle of loopback.This count value is rounded to the next integer of word cycle (9 clock cycle) then and is named as the ring time delay.As indicated above, except each node of host node is in time corrected the cable length of going up a node certainly by receiving synchronization character.Thereby, even the time delay between adjacent node (except host node) can surpass the length of a word, this time delay of recipient's node is appeared as 0.Thereby usually, each node except host node increases the time delay of a word time.Host node observes the overall delay of loop and this delay adjusting to 8 multiple of a word time, the node number that links to each other that removes in the acyclic is less than four.If four of the node delay that links to each other just are adjusted to time-delay the multiples of 4 word times, and system configuration for having four channels, each 22Mbs.The time delay of ring increases by adopting ring delay adjusting word, till total ring time delay is correct.

Last column signal payload data word of table 1.In a payload word, highest significant position is a logical zero, and the remaining bit of 8 positions transmits the data that will send to another node from a node.

Except host node, in initialize process, node is not removed data (situation of exception has dated) from ring.The end of bus cycles synch command indication initialize process.After this bus cycles synch command, each node is removed the quantity that transmits mould 8 (or mould 4) word.Another kind is the embodiment of mould 4, wherein or each node must know that it is in the ring of a time delay 4, or only initial 4 time slots allow to use.The latter implements relatively easily and rationally, this is because when having only 4 nodes, generally can be so not strong to the needs of channel capacity.

When carrying out the bus time slot allocation, must consider the time delay of ring.Just the bus time slot should be the total ring time delay and the mould of channelized frequencies.A kind of method is that the mould of this ring time delay is fixed.Each node is the situation of host node at it, must have the ability of inserting the time delay that can reach two 9-position words at most in its input shift register 40.This time delay also can be used to the time delay of adjustable ring.Thereby each node can be configured to the time delay of introducing one or two word.For comprising the only ring of two or three nodes, thereby it can be conditioned and has the time delay of four words.In other the situation, this ring can be conditioned the time delay with the mould with 8 word times at all.In various situations, delay adjusting is following carries out so for ring.

After total word time delay of ring was measured by host node, if it is not mould 8 (or 4), just sending ring delay adjusting word by host node increased time delay.Receive first node of this word, it does not also increase its time delay, (time delay that is it still is a word), the input word that self-control receives it with second 9-position rather than first 9-position from input shift register 40.By this way, this node is introduced an extra word time delay in loop, and it has the time delay of two words now.This node is removed this word then from bus.Repeat this process and be increased in the ring, and its word time delay is mould 8 (or mould 4) up to the word time delay of correct number.Those of ordinary skill in the art will notice the cable length of ring should be limited in about 18 meters with interior to avoid cable oneself itself to increase more than this situation of the time delay of a word.Utilize a kind of like this system, it is just simple relatively to increase by 8 multiplexing of channel constraints.Basic system's (see figure 2) is 11 cycles, each cycle 8 time slots, 9 of each time slots.Each 88 time slot, a time slot is as the synchronization character that comprises a control channel position.

The BBUS system comprises the control channel of a compatible CEBUS.As stipulating among the industrial standard IS-60, the CEBUS control channel provides per second 10k the maximum bandwidth of position.To the arbitration of the visit of control channel is by on bus high-grade and the use inferior grade state being carried out, very the class liny or the arbitration control channel.The flow chart of Fig. 6 signal hereinafter will be described in detail, and the example of the operation of a BBUS system during arbitrating is provided.As indicated above and as shown in Figure 2, the BBUS system comprises the bus cycles of one 7.920 microsecond, and each bus cycles sends a bus cycles synchronization character.Control channel arbitration information and data are placed in the control channel position of cycle synchronisation word.The maximum data bit rate that this physical layer allows equals bus cycles synchronization character speed.Corresponding to the known data link layer of CEBUS, the gerentocratic agreement of network layer and application layer and system layer can be used to finish this control channel model.Also have, the relevant sublayer of CEBUS medium can be used for the Code And Decode data.

In the discussion hereinafter, place value, 1 and 0, be used to refer to the high-grade or inferior grade status signal in the control channel.For example, when this field is set to the logical one signal, be high-grade status signal, and the inferior grade status signal of acquiescence is the logical zero signal.In a kind of embodiment of reality, this state correspondence can give over to standby.

The CEBUS carrier of arbitration and control channel visit is monitored multiple access competition detection (CSMA-CD) method and be can be used to determine which node has obtained the access right to control channel.Somewhere in the operation of CEBUS must determine whether to start the arbitration to the control channel access right.Now there have been a variety of diverse ways of determining when to start arbitration.For example, when a node is wanted the access control channel, just can start a kind of arbitration.In addition, when a plurality of nodes are wanted the access control channel simultaneously, also can start a kind of arbitration.If a kind of arbitration is necessary, then adopts a kind of existing mode to trigger this arbitration, and trigger this arbitration during greater than a certain predetermined amount of time when bus is in the nonactivated time by the activity of monitoring control channel.

After a kind of arbitration is triggered, want each node of access control channel to calculate 8-locative preposition sign indicating number.In a kind of embodiment preferred, this preamble produces as a random number at each node, and is different to each arbitration.This just allows can satisfy liberally the visit of bus.In addition, each node can be allocated the preamble of the relative priority level of each node of expression in advance.This preamble is used for arbitrating the visit to control channel.The node that control channel is successfully arbitrated is finished the transmission of its message.All other node before attempting the arbitration control channel, must be waited for next up duration (determining like that as described above) at interval.

This preamble and message are transmission destination, are encoded into high-grade and inferior grade state alternate sequence.Symbol is by the state in the control bit of cycle synchronisation word, or a series of state representation in the control bit of consecutive periods synchronization character.Till the transmission of the value of this symbol lasted till next state-transition always.Four basic symbols are arranged: logical one, logical zero, field finishes (EOF) and grouping finishes (EOP).Other symbol, for example preamble field finishes and sign field finishes, and also has, but does not adopt in the example system that is described below.Bus cycles (7.920 microsecond) equal the unit symbol time (UST).

Symbolic coding is as follows:

1 UST＝1

2 UST＝0

3 UST＝EOF

4 UST＝EOP

The carrying symbol (1,0, EOF, any information EOP) can by or high-grade or inferior grade status signal represent, or represent by a series of continuous high-grade or inferior grade status signals.For example, the logical one signal is by single high-grade status signal " 1 " or single inferior grade status signal " 0 " expression.The logical zero signal is by two continuous high-grade status signals " 11 " or two continuous inferior grade status signal " 00 " expressions, and so on.Thereby, position in the preamble " 0101 " is represented by control channel signals (001001), promptly two the expression logical zero signal continuous inferior grade status signals, follow the high-grade status signal of a logical one of a single expression, follow the continuous inferior grade status signals of a logical zero signal of two expressions, then the high-grade status signal of a logical one signal of a single expression.In a kind of similar mode, the identical bits in the preamble (being example 0101) can be represented by control channel signals (110110).This is the elapsed-time standards of determining between the state-transition of value of symbol.

Initial arbitration can be by determining whether that satisfying the non-activation timing condition of control channel determines.Between the non-active period of control channel, the inferior grade status signal is placed in the cycle synchronisation word.Be the definition of some relational language below." control bit field " is the cycle synchronisation word bit that comprises the CEBUS control channel information (CBF).When a node is placed a high-grade state for the first time in CBF, " control channel cycle " (Control Channel Cycle) beginning, and when the node that " grouping finishes " (EndOf Packet) symbol (above defining) is arbitrated by winning or generating period is overtime sent, " control channel cycle " (Control Channel Cycle) finished.(Write Node) is first node of placing high-grade state at first control channel in the cycle in CBF " to write node ".The control channel arbitration cycle begins since then.(Competing Node) competes to rob all nodes of writing node control channel afterwards that are arranged in ring " to compete to rob node "." posterior nodal point " (LateNode) be compete to rob be arranged in ring write the control channel before the node and all nodes that begin to arbitrate in the next bus synchronous cycle.

Refer again to Fig. 1, suppose that node A is that the host node and the supposition node C of bus is " writing node ", node D and E compete to rob node what be in the same bus cycle.Node A and B compete to rob node but are used as " posterior nodal point ", and this is because they begin arbitration in the next bus synchronous cycle.In case certain node initialization a control bus cycle, host node A receives CBF from node E.Otherwise its CBF is set to inferior grade state, 0.

Arbitration rules are as follows:

At first, node can compete to rob to the visit of CEBUS control channel compete rob, suppose that it has satisfied non-the activations timing of all control channels requirement of IS-60.These timing requirements should begin by the high-grade state from the CBF of last observation.

The second, if this node has received a CBF with high-grade state, the CBF that exports from a node must be high-grade state.This regular exceptional situation provides below.The node of not competing to rob to the visit of control channel does not pass to next node to the CBF that is regained with not changing.

The 3rd, if a node is placed on control channel to a CBF with inferior grade state, and in next bus cycles synchronization character, received back a CBF with high-grade state, this node withdraw to control channel compete rob.

The 4th, if node (still) state (based on the preamble at random of coding) of competing to rob control channel and next CBF output be high-grade state, this node should be set to high-grade state by CBF, even it has received a high-grade state.

The 5th, successfully finish the preamble of its coding of transmission and first node of " field end " symbol (defined above) and win the control channel arbitration.

Change CBF's is regular as follows:

At first, after satisfying the non-activation timing of control channel requirement, first node of establishing a high-grade status signal in the bus cycles is to write node.

The second, to write node except this and can change this CBF value, other node can not change this CBF value from high-grade state.

The 3rd, all compete to rob node can change into high-grade state to CBF from the inferior grade state.

The 4th, a node is appointed as this appointment of writing node, can be inherited by any node that CBF is changed into high-grade state from high-grade state.That is, do not write node if a node is not one at first, and it receives the CBF of an inferior grade state, but it changes into high-grade state to CBF according to the preamble of its coding, this node just becomes writes node.

The 5th, if this node receives a CBF (this CBF is not that it was established) on control channel in the last bus cycles, then in the past be appointed as the node loss of writing node and write node state.In addition, this node withdraw to control channel visit compete rob.

By a example, can understand the operation described better with reference to the arbitration operation of signal in flow chart 6.At Fig. 6, arbitration begins in step 600.Step 605 determines whether a node is competing to rob the visit to control channel, for example, if this node has a control messages to send.For the node of not competing to rob to the control channel visit, after the step 605 step 660 and 665, they do not hand on each CBF that is received up to arbitration with not changing finishes.Finishing ("Yes" as a result of step 665) when arbitration, is step 635 (finishing in this step arbitration) after the step 665, and step 640 (competing to rob the node visit control channel of visiting and winning arbitration in this step).

For the node of competing to rob to the visit of control channel, after the step 605 step 610 (producing a preamble) in this step.Competing to rob to the visit of control channel and receiving a node with CBF of inferior grade state becomes and writes node, and starts transmission to its preamble by be set to high-grade state at step 615 CBF.Next CBF receives in step 620.Be step 625 after the step 620, step 625 determines that whether previous CBF state is an inferior grade state the and whether CBF that received is a high-grade state.If (in the "Yes" as a result of step 625), it is high-grade state that another node has changed CBF, that is, another node has become writes node.Thereby, after the step 625 be step 660 (this step present node stop to control channel compete rob, and, as described above, do not change follow-up CBF value, that is, make the CBF value by this node.The "No" as a result of step 625 represents that it is " a writing " node that present node continues, and causing will be in step 625 back execution in step 630.Step 630 determine previous CBF state whether be the final state of preamble also be with the identical state of CBF state that is received.The "Yes" as a result of step 630 represent this node successfully finished the preamble that sends it and, thereby, won this arbitration.After the "Yes" as a result of follows step 630 is step 635 (it finishes arbitration) and step 640 (at this step triumph node visit control channel).The "No" as a result of step 630 represents that all preamble positions also are not sent out and execution in step 650.In step 650, the next CBF state that this node produces is determined by next preamble state and by the rule at the change CBF state of above explaining.After the step 650 is step 620 (receiving next CBF state in this step).

As for further explanation, next be described in three the bus synchronous cycles at first in the arbitration cycle to arbitration operation.In first available bus cycles of arbitration, for example, be illustrated in required time and do not existed control channel to activate in the phase, host node is set to an inferior grade status signal " 0 " to the control bit field (CBF) on the bus synchronous cycle word.Any node of wanting the access control channel all begins by CBF being changed into the preamble of the coding among the CBF that high-grade state " 1 " sends it, and this node becomes and writes node.Not competing to rob subsequent node (being called the non-node of competing to rob) to the visit of control channel notes the high-grade state 1 of the CBF received and its is not passed to next node with having change.Non-ly compete to rob node, before they can compete to rob control channel, when satisfying the non-activationary time of control channel, must wait for next constantly then.Light from this of this arbitration cycle, non-ly compete to rob node the CBF that sends to them is not delivered to next node with having change.Any node before writing node can not be seen the high-grade state 1 among the CBF in these first bus cycles of arbitration cycle.The operation of such node will be described in more detail below.

In two or more nodes competed to rob situation to the visit of control channel, first node was set to the preamble that high-grade state begins to send its coding by its CBF.This is expression in the following manner hereinafter: CBF (cycle #)=state.In this case, be the cycle 1 of arbitration cycle, and the value for high-grade status signal (by 1 the expression), thereby: CBF (1)=1.CBF is set to first node of 1 and knows that it is to write node, because it has received CBF (1)=0.All follow-up arbitration nodes will all be to compete to rob node and all will begin in an identical manner, not transmit CBF (1)=0 by there being change ground, send the preamble of its coding.The CBF value may not change from high-grade state, has finished loop (promptly being write node up to it receives) up to it.Aforesaid, all non-ly compete to rob node received CBF is passed, and no longer compete to rob visit in the cycle control channel at this CC.

In second bus cycles of arbitration cycle, host node detects it and has received CBF (1)=1 and in next bus cycles synchronization character CBF (2)=1 has been set.At host node and write and may have a node between node, it wants the access control channel, but does not observe CBF (1)=1 in the last bus cycles.Such node is called posterior nodal point.It also will begin to send by transmission value CBF (2)=1 preamble of its coding.But it and the former node of writing compete to rob.Value CBF (2)=1 propagates up to its arrival along ring and writes node.This writes node can change into CBF (2)=0 to the state of CBF (2), or continues with CBF (2)=1, and this depends on the next state of preamble of its coding.If the next state of writing in the preamble of coding of node is high-grade state, writes node so CBF (2)=1 is set.On the other hand, if the next state of the preamble of coding is the inferior grade state, writes node so CBF (2)=0 is set.Subsequent node continues the preamble that trial sends their coding similarly.Whether subsequent node of this regular control of setting up above can change the state of CBF (2).

To keep the state of CBF (2) be high-grade state if write node, i.e. CBF (2)=1, so, explained in the rule as mentioned like that, each is follow-up competes to rob the NextState of preamble that node is determined its coding.If the NextState of the preamble of its coding is high-grade state, this node passes through by CBF (2)=1 so, and keep to the control channel visit compete rob.If the NextState of the preamble of its coding is the inferior grade state, this node passes through by CBF (2)=1 so, and withdraw to control channel visit compete rob.In the arbitration cycle after this time, this node does not pass to next node to CBF with having change.

If writing the state that node changes CBF (2) is the inferior grade state, i.e. CBF (2)=0, subsequent node can be established a high-grade state 1 by this change of CBF (2)=1 is set so.If the NextState of the preamble of the coding of a subsequent node is high-grade state 1, this node sends CBF (2)=1 so.When this happens, this node is inherited and is write node state.If the NextState of the preamble of the coding of subsequent node is an inferior grade state, this node passes through by CBF (2)=0 so, and keep to the control channel visit compete rob.

In the 3rd bus cycles of arbitration cycle, host node receives CBF (2)=0 and CBF (3)=0 is set, or receives CBF (2)=1 and CBF (3)=1 is set.A posterior nodal point, adopt and a kind of and toply describe similar mode, determine the NextState of preamble of its coding, and CBF (3)=0 or CBF (3)=1 are set then competing to rob node, or withdraw to control channel visit compete rob, abide by rule as described above all.This process all takes place all posterior nodal points.

At some time point, write node and receive CBF (3).If this is write node and has been provided with CBF (2)=1 in front, it must reclaim CBF (3)=1 so.This is write node and CBF (3) is set then for the NextState in the preamble of its coding, as carrying out in the control channel cycle 2 of arbitration cycle (above describing).If this is write node and has been provided with CBF (2)=0 in front, and receive CBF (3)=0, this is write node and remains and write node so, still be in to the visit of control channel compete rob, and can change into the value of CBF (3) NextState of preamble of its coding.If this is write node and has been provided with CBF (2)=0 in front, but receive CBF (3)=1, it no longer is to write node so, and no longer be in to the visit of control channel compete rob.From arbitration cycle herein, this node does not pass to next node to received CBF with having change.

Above-described operation was proceeded the follow-up bus cycles.Reservation is set to NextState in its preamble of coding to each node of competing to rob of the visit of control channel or CBF, perhaps withdraw to the visit of bus compete rob.After the preamble transmission is finished, still be in the state of each node trial transmission field terminating symbol in competing to rob, the field terminating symbol, aforesaid.Be three continuous high-grade or inferior grade status signals.First node that successfully sends and receive its preamble that follows field terminating symbol coding afterwards closely has won arbitration and can begin its message of transmission in the CBF of bus cycles synchronization character.

For summing up above description, finish and during the field symbols end at preamble, be left this node of writing node and successfully arbitrated visit this node.This state of writing node is inherited by any node that CBF is changed into high-grade state from inferior grade.Write node when this and reclaim one and be placed on the different CBF of CBF in the control channel with it, this writes the loss of state of node.

Be five examples of control bit field value below.Each example is illustrated with forms mode.A node is represented on each hurdle in table.In the table second row has been illustrated the preamble that produces at random competing to rob the node of control channel access right.The third line has been illustrated to abide by the rule that above provides and the preamble of encoding in the table.Aforesaid, first state that preamble is encoded is high-grade state.Remaining row has been illustrated the state of CBF, because it is produced in the follow-up bus cycles by each node.Fourth line is the zero cycle and is illustrated in an arbitration cycle startup nonactivated final cycle of control channel before.

In example 1, node A is a host node, and node D starts before the arbitration, and Node B is one and competes to rob posterior nodal point to the visit of control channel with node D.Host node (node A) in CBF before arbitration cycle the time keep an inferior grade state 0 in interval, as in the cycle 0, and the signal of the first of bus cycles 1.In the bus cycles 1, node D starts arbitration cycle by the high-grade state of establishing among the CBF for first state of the preamble of its coding.Node E and node A compete to rob node, just this signal are passed to Node B in the bus cycles 2.Node B is a posterior nodal point, and gives node C high-grade state transfer.Node C neither compete to rob node, and high-grade state transfer is returned to node D.Node D when it is recovered to CBF (2) in the cycle 2, changes into CBF (2)=0 to it, is illustrated in the NextState in its preamble of coding.

Cycle	Node A	Node B	Node C	Node D	Node E
						Preposition code value		10101101		10001111
The preamble of coding		110010010110		10011001010
						0	0	0	0	0	0
1	0	0	0	1	1
						2	1	1	1	0	0
3	0	1	1	1	1
						4	1	0	0	0	0
5	0	0	0	0	0
						6	0	1	1	1	1
7	1	0	0	0	0
						8	0	0	0	0	0
9	0	1	1	1	1
						10	1	0	0	0	0
11	0	1	1	1	1
						12	1	1	1	1	1
13	1	0	0	0	0
						14	0

Example 1

By node E and A it is passed to Node B in the cycle 3.Node B receives one 0 in cycles 3, but it is changed over one 1, as its NextState of preamble of coding.Node B becomes now writes node.This 1 passes to node D by node C.Node D sends one 0 in the cycle 2 but receives one 1 in the cycle 3.Thereby, node D withdraw to the visit of control channel compete rob.All nodes except Node B become passive now and have change ground the CBF that is received is not passed to next node.At last, Node B successfully sends and receives its and then preamble of the coding of a field terminating symbol, and obtains the access right to control channel.

Cycle	Node A	Node B	Node C	Node D	Node E
						Preposition code value				10001111	01010110
The preamble of coding				10011001010	110110110100
						0	0	0	0	0	0
1	0	0	0	1	1
						2	1	1	1	0	1
3	1	1	1	1	0
						4	0	0	0	0	1
5	1	1	1	1	1
						6	1	1	1	1	0
7	0	0	0	0	1
						8	1	1	1	1	1
9	1	1	1	1	0
						10	0	0	0	0

Example 2

In example 2, node D starts an arbitration cycle by CBF (1)=1 is set as first state of the preamble of its coding, and it is to write node.Node E is one and competes to rob node, and transmits the CBF (1)=1 that it receives from node D.Node A, B and C are the non-nodes of competing to rob, and the CBF value that is received is not passed to next node with having change.In the cycle 2, node D is from node C reception CBF (2)=1 and changing into CBF (2)=0 as the NextState the preamble of its coding.Node E receives CBF (2)=0 in the cycle 2.But the NextState in the preamble of the coding of node E is 1.Thereby node E is provided with CBF (2)=1, and becomes and write node.In the cycle 2, node D is provided with CBF (2)=0, but in the cycle 3, node D receives CBF (3)=1.Thereby node D knows it and lost arbitration, and withdraw to the visit of control channel compete rob.Herein, all nodes except node E all withdraw to the visit of control channel compete rob, and the CBF value that received is passed to next node with not having change.Node E sends its preamble of complete coding and field terminating symbol subsequently at last, and obtains the access right to control channel.

Cycle	Node A	Node B	Node C	Node D	Node E
						Preposition code value				10001111	10110110
The preamble of coding				10011001010	10010110100
						0	0	0	0	0	0
1	0	0	0	1	1
						2	1	1	1	0	0
3	0	0	0	0	0
						4	0	0	0	1	1
5	1	1	1	1	1
						6	1	1	1	0	0
7	0	0	0	0	0
						8	0	0	0	1	1
9	1	1	1	0	0
						10	0	0	0	1	1
11	1	1	1	0	0
						12	0	0	0

Example 3

In example 3, node D comes a arbitration cycle in the start-up period 1 by CBF (1)=1 is set.Node E is one and competes to rob node, and the CBF (1)=1 that receives is passed to node A.Node A, B and C are the non-nodes of competing to rob, and it does not pass to next node to the CBF value that is received with having change.In the cycle 2, node D receives CBF (2)=1.NextState in the preamble of the coding of node D is 0, so node D is provided with CBF (2)=0.Node E receives CBF (2)=0.But the NextState in the preamble of node E also is 0, thus node E keep to the visit of control channel compete rob, and CBF (2)=0 is set.In the cycle 3, process is identical.In the cycle 4, node D receives CBF (4)=0.The NextState of the preamble of its coding is 1, so node D is provided with CBF (4)=1.Node E receives CBF (4)=1 from node D.As in the cycle 1, the NextState of its preamble is 1, competes to rob and be provided with CBF (4)=1 so node E keeps.In the cycle 5, node D receives CBF (5)=1.The NextState of its preamble is 1, so node D is provided with CBF (5)=1.Node E receives CBF (5)=1.But the NextState of its preamble is 0.Thereby node E withdraw to the visit of control channel compete rob, and the CBF value that is received is not passed to node A with having change in the remaining time of arbitration cycle.Finish node D successfully sends its preamble of coding and field terminating symbol subsequently, and obtains the access right to control channel.

Cycle	Node A	Node B	Node C	Node D	Node E
						Preposition code value				11110111	11110111
The preamble of coding				101011010	101011010
						0	0	0	0	0	0
1	0	0	0	1	1
						2	1	1	1	0	1
3	0	0	0	1	0
						4	1	1	1	0	1
5	0	0	0	1	1
						6	1	1	1	1	1
7	1	1	1	0	0
						8	0	0	0	1	1
9	1	1	1	0	0
						10	0	0	0	1	1
11	1	1	1	1	1
						12	1	1	1	1	1
13	1	1	1	0

Example 4

At 4, two kinds of preambles that produce at random of example all is identical.Node D starts an arbitration cycle by CBF (1)=1 is set in the cycle 1.Node E is one and competes to rob node and receive CBF (1)=1.It also is provided with CBF (1)=1.Node A, B and C are the non-nodes of competing to rob, and it does not pass to next node to the CBF value that is received with having change.In the cycle 2, node D receives CBF (2)=1.NextState in the preamble of its coding is 0, so CBF (2)=0 is set.Node E receives CBF (2)=0.The NextState of its preamble is 0, so its keeps competing to rob, and CBF (2)=0 is set.Because the preamble of coding all is identical, so this process continued up to the cycle 9.In the cycle 10, node D is provided with first state of CBF (10)=1 as field terminating symbol (in above definition).To in 9 initial similar modes of cycle, node E also sends a field terminating symbol and CBF (10)=1 is set.This process continued up to the cycle 13.In the cycle 13, node D reclaims the final state of field terminating symbol and obtains access right to control channel.No matter first of message is logical one (it is with 0 single transmission) or logical zero (it is with two 1 continuous transmissions), first state that is placed on control channel is 0.Node E receives CBF (13)=0, but it has sent CBF (12)=1.Thereby it withdraws from and competes to rob, and node D obtains the access right to control channel.

Cycle	Node A	Node B	Node C	Node D	Node E
						Preposition code value		11110111		11110111
The preamble of coding		101011010		101011010
						0	0	0	0	0	0
1	0	0	0	1	1
						2	1	1	1	0	1
3	0	0	0	1	0
						4	1	1	1	0	1
5	0	0	0	1	1
						6	1	1	1	1	1
7	1	1	1	0	0
						8	0	0	0	1	1
9	1	1	1	0	0
						10	0	0	0	1	1
11	1	1	1	1	1
						12	1	1	1	1	1
13	1	1	0

Example 5

Except Node B was a posterior nodal point, example 5 was closely similar with example 4.The preamble of Node B and D all is identical.Node D starts an arbitration cycle by CBF (1)=1 is set in the cycle 1.Node A, C and E are the non-nodes of competing to rob, and it does not pass to next node to the CBF value that is received with having change.As example 4, the preamble of Node B and the coding of node D all is identical, and each keep to the visit of control channel compete rob up to the cycle 10.In the cycle 10, node D begins to send a field terminating symbol.In the cycle 11, Node B also begins to send a field terminating symbol.Also have, two nodes keep to the visit of control channel compete rob up to the cycle 12.In the cycle 13, Node B receives CBF (13)=1, the preamble of its its coding of expression and the successful transmission of field terminating symbol subsequently.Thereby Node B is obtained the access right to control channel.As example 4, Node B begins the transmission of its message by CBF (13)=0 is set.Node D receives CBF (13)=0, and withdraw to the visit of control channel compete rob.

Claims (6)

1. comprise in the data communication system of a plurality of nodes that ring bus is coupled a kind of, this ring bus sends at least one position of a control channel in each of continuous bus cycles, each node arbitration may further comprise the steps a kind of method of the access right of control channel in an arbitration cycle:

Produce the preamble with coding of multiple continuous state, each state is one of high-grade state and inferior grade state;

Being arranged on a control channel position in the bus cycles is high-grade state, represents one first state of the preamble of this coding;

To each of subsequently bus cycles:

Receive a control channel position;

If a last control channel position is set to the inferior grade state, and the state of the control channel position that is received is high-grade state, withdraw from so to control channel compete rob, and this is competed the cycle of robbing At All Other Times, the control channel position is set to the state of the control channel position that received;

As if a last control channel position is the final state that is set to the preamble of this coding, and identical with the control channel position that is received, and obtains the access right of control channel so;

Otherwise, the next state of the preamble of definite coding, and this control channel position is set to the next state of the preamble of this coding.

2. the method for claim 1, before this produces step, further comprising the steps of:

Determine the whether non-activation of this control channel; And

Only when being non-activation, this control channel begins this arbitration cycle.

3. the method for claim 1, before this produces step, further comprising the steps of:

Determine whether this node expects to visit this control channel; And

To each of subsequently bus cycles:

If this node do not expect to visit this control channel, so,, this control channel position be set be the state of the control channel position that is received to the remaining time of arbitration cycle.

4. the process of claim 1 wherein that the step of the preamble that produces a coding may further comprise the steps:

Produce a random number;

This random number of encoding;

The field terminating symbol of encoding; And

The random number of additional this coding and the field terminating symbol of coding and produce the preamble of this coding.

5. the method for claim 4, the step that wherein produces a random number comprise producing to have 8 these steps of this random number of position continuously, and each be one of logical zero and " 1 ".

6. the method for claim 4, the step of the random number of wherein encoding comprises continuous this step of identical-status signal that the continuous position in this random number is encoded into varying number, wherein logical one is encoded into a single status signal, logical zero is encoded into two continuous identical-status signals, and the field terminating symbol is encoded into three continuous identical-status signals.

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