CN100593163C - Interface device used for connecting serial port or general serial bus structure - Google Patents
Interface device used for connecting serial port or general serial bus structure Download PDFInfo
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- CN100593163C CN100593163C CN200710191760A CN200710191760A CN100593163C CN 100593163 C CN100593163 C CN 100593163C CN 200710191760 A CN200710191760 A CN 200710191760A CN 200710191760 A CN200710191760 A CN 200710191760A CN 100593163 C CN100593163 C CN 100593163C
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Abstract
The invention discloses an interface device used to connect a serial port or a universal serial bus, which recognizes and connects the universal serial bus to the two-wire communication port devices of the serial port and universal serial bus interface. The invention is the device for the serial port and the universal serial bus to automatically recognize the two-wire communication port and combines the serial port or universal serial bus through judging and processing input signals, which not only connects with the serial port for communication, but also connects with the universal serial busfor communication, thereby increasing the flexibility of the two communication ports including the serial port and the universal serial bus.
Description
Technical field
The present invention relates to a kind of be used to connect serial ports or universal serial bus architecture interface device, this device also can be connected to two line communication port of serial ports, universal serial bus architecture interface for identification.
Background technology
Serial ports (asynchronous serial communication interface of full duplex or I2C bus) is used very extensive also very convenient in scm application system.
Universal serial bus structural (USB) is a kind of computer external interface standard, has plug and play, expands advantages such as convenient, has become an interface of computing machine indispensability.Also be widely used in scm application system, scm application system can be operated mass-memory unit (USB flash disk, portable hard drive etc.), digital camera, digital pickup camera, mouse, keyboard or the like.
The transmitting terminal of the asynchronous serial communication interface of full duplex only is used to send communication data, and receiving end only is used for the received communication data, and transmitting terminal and receiving end all are high level state when idle.SDA and SCL are bidirectional lines in the I2C bus, and when the I2C bus was idle, these two circuits also all were high level state.The D+/D-of USB USB (universal serial bus) can support synchronous transmission and two kinds of transmission modes of asynchronous transmission simultaneously, and D+/D-does not exist and is the situation of high level state simultaneously.Serial ports can not be connected on the USB USB (universal serial bus), and the USB USB (universal serial bus) can not be connected on the serial ports.
The present invention is serial ports/USB USB (universal serial bus) device of identification two line communication port automatically, compatible serial ports and USB USB (universal serial bus), USB both can be connected with serial ports to communicate also can be connected with the USB USB (universal serial bus) and communicated, thus the use dirigibility that has increased serial ports and these two kinds of communication port of USB USB (universal serial bus).
Summary of the invention
Technical matters: the purpose of this invention is to provide the two line communication port devices that a kind of identification also can be connected to universal serial bus structural serial ports, universal serial bus architecture interface.This device is used to solve USB and both can be connected with serial ports to communicate also can be connected with the USB USB (universal serial bus) and communicates, to increase dirigibility and the compatibility that these two kinds of communication port of serial ports and USB USB (universal serial bus) are used.
Technical scheme: the invention discloses a kind of be used to connect serial ports or usb bus interface arrangement, this device comprises the interface identification module, the serial ports transceiver module, the universal serial bus structural transceiver module, the first lead D-, the second lead D+, power lead LV, the end of source line LG connect respectively with serial bus architecture transceiver module port, wherein the first lead D-, the second lead D+, power lead LV, the other end of source line LG connect external communication ports respectively, P-channel field-effect transistor (PEFT) pipe drain electrode connecting resistance R1 negative terminal, the resistance R 1 positive termination second lead D+.
The interface identification module comprises the positive termination first lead D-of pull down resistor R2, pull down resistor R2 negative terminal connects N channel field-effect pipe drain electrode, the positive termination second lead D+ of pull down resistor R3, pull down resistor R3 negative terminal connects the drain electrode of the 2nd N channel field-effect pipe, first, two channel field-effect tube grids connect logical AND gate G4 output terminal, logical AND gate G4 input end one connects ternary follower control end, logical AND gate G4 input end two connects the P-channel field-effect transistor (PEFT) tube grid, the ternary follower output termination first lead D-, ternary follower input termination serial ports transceiver module transmitting terminal, the serial ports transceiver module receives the termination second lead D+, logical AND gate G5 input end one meets the first lead D-, logical AND gate G5 input end two meets the second lead D+, logical AND gate G5 output termination control logic module input end one, time block output termination control logic module input end two, system reset module output termination control logic module input end three, control logic module output terminal one connects ternary follower control end, control logic module output terminal two connects the P-channel field-effect transistor (PEFT) tube grid, P-channel field-effect transistor (PEFT) pipe drain electrode connecting resistance R1 negative terminal, the resistance R 1 positive termination second lead D+, logic inverter G6 output terminal is connected with serial bus architecture transceiver module Enable Pin, logic inverter G6 input termination control logic module output terminal two.
Above-mentioned control logic module is made up of logic inverter G3, the first d type flip flop G7, the second d type flip flop G8, the input end of logic inverter G3 is a control logic module input end one, the input end of the first d type flip flop G7 is a control logic module input end two, the input end of the second d type flip flop G8 is a control logic module input end three, the output terminal of the first d type flip flop G7 is that the output terminal of control logic module output terminal one, the second d type flip flop G8 is a control logic module output terminal two; Time block is made up of logic inverter G1, capacitor C 1, resistance R 4, and logic inverter G1 output terminal is the time block output terminal; The system reset module is made up of logic inverter G2, capacitor C 2, resistance R 5, and logic inverter G2 output terminal is a system reset module output terminal.Described each module components and parts utilize lead to connect.Pull down resistor R2, the R3 resistance is identical and resistance greater than twice external serial ports pull-up resistor resistance and twice driving resistor resistance.The product value time constant of capacitor C 1 and resistance R 4 is greater than the product value time constant of capacitor C 2 with resistance R 5.
Wherein time block, system reset module can realize with another kind of method, time block is made up of logic inverter G1, capacitor C 1, resistance R 4,3d flip-flop G9, the one or four digit counter G11, first clock, and 3d flip-flop G9 output terminal is the time block output terminal; The system reset module is made up of logic inverter G2, capacitor C 2, resistance R 5, four d flip-flop G10, the two or four digit counter G12, second clock, and four d flip-flop G10 output terminal is a system reset module output terminal.
The method of operating of this device comprises the steps: to start power reset, close universal serial bus structural bus transceiver module and serial ports transceiver module, after starting time block control delay time, judge the logical signal state on the first lead D-, the second lead D+, if the first lead D-, the second lead D+ go up logical signal state and are high level signal, open the serial ports transceiver module and connect, connect otherwise open the universal serial bus structural transceiver module.
Utilize single-chip microcomputer to realize the function of time block, system reset module:
The time block method of operating comprises the steps: to state a bit timing module output signal variable, the delay time variable of definition time block also states that this variable is no symbol sixteen bit variable, setting initial output signal is low level, time block delay time variable is provided with the delay time numerical quantities, and output signal was a high level when circulation of delay time numerical quantities was decremented to zero.
System reset module operation method comprises the steps: to state a system reset module output signal variable, the delay time variable of define system reseting module also states that this variable is no symbol sixteen bit variable, setting initial output signal is low level, system reset module delay time variable is provided with the delay time numerical quantities and less than the delay time numerical quantities of time block, output signal was a high level when circulation of delay time numerical quantities was decremented to zero.
The one NMOS and the 2nd NMOS are as switching tube, be used to enable or stop resistance R 2 and R3, PMOS is the USB switching tube, be used to enable or stop resistance R 1, when a NMOS and the 2nd NMOS are in opening, switch closure is communicated with to switch, PMOS is in cut-off state, switch opens disconnects to switch, signal on the reseting port of control logic module becomes high level and resets and finish, etc. in stable condition, low level of time block output is to the saltus step of high level, and the logical signal state on the output port of control logic module latching logic and door G5 is also exported the control signal corresponding combination.
When outside port inserts, the reseting port of control logic module is received a low level signal, the output port logical signal state of control logic module is a high level signal, the transmitting terminal of serial ports transceiver module is a high-impedance state, serial ports transceiver module and USB transceiver module are in " shut " mode", the one NMOS and the 2nd NMOS are in opening, PMOS is in cut-off state, time-delay a period of time, signal on the reseting port of control logic module becomes high level, the low level of a period of time time block output of delaying time again is to the saltus step of high level, and the logical signal state on the output port of control logic module latching logic and door G5 is also exported the control signal corresponding combination.
If interface is connected with serial ports, this moment first lead, second lead is that level is H/H, logical signal state on the logical AND gate G5 output port is a high level, and the output port that links to each other with ternary follower Enable Pin of control logic module is a low level, and ternary follower enables, serial ports transceiver transmitting terminal place in circuit D-, the output port that links to each other with the G6 input end of control logic module is a high level, and the USB transceiver module is closed, and this moment, circuit changed the serial ports transmission state over to.
If interface is connected with the USB USB (universal serial bus), this moment first lead, second lead is that level is H/L, or L/L, logical signal state on the logical AND gate G5 output port is a low level, the output port that links to each other with ternary follower Enable Pin of control logic module is a high level, ternary follower cuts out, serial ports transceiver transmitting terminal is high-impedance state, the output port that links to each other with the G6 input end of control logic module is a low level, the USB transceiver module enables, and this moment, circuit changed USB USB (universal serial bus) transmission state over to.
By the USB transceiver module, serial ports transceiver module and interface identification module are formed.The interface identification module is made up of four parts, is respectively logical AND gate G5, control logic module, time block and system reset module.The USB transceiver module, logical AND gate G5 is connected with two line communication port of this device with the serial ports transceiver module simultaneously.Logical AND gate G5, the output port of time block and system reset module is connected with control logic module.The logical signal state decision USB transceiver module of the output port of control logic module and the mode of operation of serial ports transceiver module, be respectively the USB transceiver module and close serial ports transceiver module " shut " mode", the USB transceiver module is opened serial ports transceiver module " shut " mode" and the USB transceiver module is closed serial ports transceiver module open mode.
Basic thought of the present invention is based on that there is not this logical signal state of H/H high level in D+/D-in the USB USB (universal serial bus) structure, so in case the logical signal state that the interface identification module detects on the two line communication port of this device is H/H, then can conclude has peculiar situation to take place, and utilizes logical signal state H/H to carry out a series of operation then.Operation steps is to start power reset, closes USB transceiver module and serial ports transceiver module, and the time-delay certain hour keeps this device reset initialization state, cancels reset signal; Wait to delay time after the regular hour, this time is controlled by time block, judges the logical signal state on the two line communication port of this device, if the D+/D-logical signal state is H/H, then enters and opens the serial ports transceiver module.If the D+/D-logic state is H/L, L/H or L/L low level then enter and open the USB transceiver module.
Serial ports/USB USB (universal serial bus) automatic identification equipment has only one two line communication port, being used for serial ports is that asynchronous serial communication interface, I2C bus or the USB USB (universal serial bus) of full duplex is connected, if two line communication port are unsettled, be defaulted as connection USB USB (universal serial bus).The serial ports transceiver module that two line communication port of this device are inner with this device simultaneously, a USB transceiver module is connected with an interface identification module.The interface identification module is by logical AND gate G5, control logic module, and time block and system reset module are formed.Logical AND gate G5 carries out the decision logic computing to the logical signal on the two line communication port of this device, accurately judging what connect on the two line communication port of this device is serial ports or USB USB (universal serial bus), and control logic module is enabled one of serial ports transceiver module and USB transceiver module according to the judged result of logical AND gate G5 and carried out corresponding data communication.
Beneficial effect: the present invention proposes a kind of be used to connect serial ports or universal serial bus architecture interface device, relate to the two line communication port devices that a kind of identification also can be connected to universal serial bus structural serial ports, universal serial bus architecture interface.By the judgment processing of level signal to input, thereby realizing that USB both can be connected with serial ports to communicate also can be connected with the USB USB (universal serial bus) communicates, and has strengthened the use dirigibility and the compatibility of serial ports and these two kinds of communication port of USB USB (universal serial bus).Can further promote USB like this and use, the equipment that different manufacturers is produced can use under the system of an opening widely.Simultaneously also for the manufacturer of system with the peripheral hardware developer provides enough spaces to create multi-functional product and exploitation vast market and needn't use outmoded interface to fear to lose compatibility.
Description of drawings
Fig. 1 is the total process flow diagram of the present invention.
Fig. 2 is an entire block diagram of the present invention.Wherein have: the first lead D-, the second lead D+, power lead LV, source line LG, interface identification module 1, serial ports transceiver module 2, USB transceiver module 3, external communication ports 4, control logic module 11, time block 12, system reset module 13, resistance R 1, resistance R 2, resistance R 3, ternary follower 14, a N channel field-effect pipe 15, the 2nd N channel field-effect pipe 16, P-channel field-effect transistor (PEFT) pipe 17, logical AND gate G4, logical AND gate G5, logic inverter G6.
Fig. 3 is a system reset module map of the present invention.Wherein have: logic inverter G2, capacitor C 2, resistance R 5.
Fig. 4 is time block figure of the present invention.Wherein have: logic inverter G1, capacitor C 1, resistance R 4.
Fig. 5 is control logic module figure of the present invention.Wherein have: logic inverter G3, logic inverter G13, logic inverter G14, logic inverter G15, the first d type flip flop G7, the second d type flip flop G8.
Fig. 6 is another time block of the present invention embodiment.Wherein have: logic inverter G1, capacitor C 1, resistance R 4,3d flip-flop G9, the one or four digit counter G11, first clock 18.
Fig. 7 is another system reset module of the present invention embodiment.Wherein have: logic inverter G2, capacitor C 2, resistance R 5, four d flip-flop G10, the two or four digit counter G12, second clock 19.
Embodiment
Be that specific embodiments of the invention further describe below:
Basic thought of the present invention is based on that there is not this logical signal state of H/H high level in D+/D-in the USB USB (universal serial bus) structure, so in case the logical signal state that the interface identification module detects on the two line communication port of this device is H/H, then can conclude has peculiar situation to take place, and utilizes logical signal state H/H to carry out a series of operation then.
The present invention is connected with USB transceiver module or serial ports transceiver module and communicates by letter through the judgment processing of interface identification module by external communication ports as shown in Figure 1.
This device comprises serial ports transceiver module 2 as shown in Figure 2, universal serial bus structural transceiver module 3, external communication ports 4, interface identification module 1, the first lead D-, the second lead D+, power lead LV, the end of source line LG connect respectively with serial bus architecture transceiver module 3 ports, the first lead D-, the second lead D+, power lead LV, the other end of source line LG connect external communication ports 4 respectively, serial ports transceiver module 2 receiving ends 22 meet the second lead D+.
Control logic module 11 is by logic inverter G3, logic inverter G13, logic inverter G14, logic inverter G15, the first d type flip flop G7, the second d type flip flop G8 forms, the data input pin of the first d type flip flop G7, the input end of logic inverter G3 is control logic module 11 input ends 1, the data input pin of the output termination second d type flip flop G8 of logic inverter G3, first, the input end of clock of 2-D trigger is control logic module 11 input ends 2 112, the input end of logic inverter G13 is control logic module 11 input ends 3 113, first, the RESET input of 2-D trigger connects the output terminal of logic inverter G13, the output terminal of logic inverter G15 is control logic module 11 output terminals 1, and the output terminal of logic inverter G14 is control logic module 11 output terminals 2 115.
The method of operating of said apparatus comprises the steps: to start power reset, close universal serial bus structural bus transceiver module 3 and serial ports transceiver module 2, after starting time block 12 control delay times, judge the logical signal state on the first lead D-, the second lead D+, if the first lead D-, the second lead D+ go up logical signal state and are high level signal, open serial ports transceiver module 2 and connect, connect otherwise open universal serial bus structural transceiver module 3.
The logical signal state decision USB transceiver module of the output port of control logic module and the mode of operation of serial ports transceiver module, be respectively the USB transceiver module and close serial ports transceiver module " shut " mode", the USB transceiver module is opened serial ports transceiver module " shut " mode" and the USB transceiver module is closed serial ports transceiver module open mode.
Logical AND gate G5 adopts the 74HC08 chip, and when the signal of IN0 and IN1 was high level simultaneously, DIN exported high level, when the signal of IN0 and IN1 makes up for other level, and the DIN output low level.The formation of time block and system reset module is the same, the CLK and the CLR of output are step signal, zero-time is a low level, to be maintained high level after a period of time constant always, G1 and G2 are that logic inverter adopts the 74HC04 chip, control logic module is formed employing 74HC74 chip by d type flip flop G7 and G8, G3 is that logic inverter adopts the 74HC04 chip, when～CLR signal is low level, Q0 and Q1 are output as high level, when～CLR signal is high level, the CLK signal by low level when high level changes, the D0 signal is latched on the Q0, and the D1 signal is latched on the Q1.The serial ports transceiver module is the asynchronous serial communication interface transceiver module of full duplex, and ternary follower 14 control ports are that low level is effective, and a NMOS and the 2nd NMOS are weak drop-down.The logical signal of the output port of logical AND gate G4 is controlled the duty of a NMOS and the 2nd NMOS.The duty PMOS that the logical signal of the output port 115 of control logic module 11 is used for controlling PMOS draws the mode of operation of control USB transceiver module on weak.
Embodiment 2
Fig. 7 system reset module 13 adopts the 74HC04 chip by logic inverter G2,0.1uF capacitor C 2 negativing ending groundings, the positive termination of 80K Ohmage R5+5V power supply, capacitor C 2 anodes, resistance R 5 negative terminals connect logic inverter G2 input end, four d flip-flop G10, the termination logic inverter G2 output terminal that resets of the two or four digit counter G12, four d flip-flop G10 adopts the 74HC74 chip, the two or four digit counter G12 adopts the 74HC161 chip, second clock 18 connects the input end of clock of the two or four digit counter G12, the output terminal B4 of the two or four digit counter G11 connects the input end of clock of four d flip-flop G10, second clock 19 frequencies are 32KHZ, and four d flip-flop G10 output terminal is system reset module 13 output terminals 131.
Pull down resistor R2, the R3 resistance is identical and resistance greater than twice external serial ports pull-up resistor resistance and twice driving resistor resistance, resistance R 2 and resistance R 3 are 1M ohm.Logical AND gate G5 adopts the 74HC08 chip, and when the signal of IN0 and IN1 was high level simultaneously, DIN exported high level, when the signal of IN0 and IN1 makes up for other level, and the DIN output low level.The formation of time block and system reset module is the same, the CLK and the CLR of output are step signal, zero-time is a low level, to be maintained high level after a period of time constant always, G1 and G2 are that logic inverter adopts the 74HC04 chip, control logic module is formed employing 74HC74 chip by d type flip flop G7 and G8, G3 is that logic inverter adopts the 74HC04 chip, when～CLR signal is low level, Q0 and Q1 are output as high level, when～CLR signal is high level, the CLK signal by low level when high level changes, the D0 signal is latched on the Q0, and the D1 signal is latched on the Q1.
Embodiment 3
Utilize single-chip microcomputer 8051, adopt KEILC compiler compiling C programmer to realize time block 12, system reset module 13 functions:
System reset module 13 methods of operating comprise the steps: to state a system reset module 13 output signal variablees, the delay time variable of define system reseting module 13 also states that this variable is no symbol sixteen bit variable, setting initial output signal is low level, it is 4000 that system reset module 13 delay time variablees are provided with the delay time numerical quantities, and output signal was a high level when circulation of delay time numerical quantities was decremented to zero.
The serial ports transceiver module is the asynchronous serial communication interface transceiver module of full duplex, and ternary follower 14 control ports are that low level is effective, and resistance R 2 and resistance R 3 are 1M Ω, and a NMOS and the 2nd NMOS are weak drop-down.The logical signal of the output port of logical AND gate G4 is controlled the duty of a NMOS and the 2nd NMOS.Resistance R 1 is 1.5K Ω, and the duty PMOS that the logical signal of the output port 115 of control logic module 11 is used for controlling PMOS draws the mode of operation of control USB transceiver module on weak.
The method of the automatic identification of this device serial ports/USB USB (universal serial bus) is as described below: the time marquis that this device is just powering on, the reseting port of control logic module 11 is received a low level signal, the output port 114 of control logic module 11 and the logical signal state of output port 115 all are H, the transmitting terminal 21 of serial ports transceiver module 2 is a high-impedance state, serial ports transceiver module 2 and USB transceiver module 3 are in the serial ports transceiver module and close USB transceiver module " shut " mode", the one NMOS and the 2nd NMOS are in the opening switch closure, and PMOS is in the cut-off state switch opens.After a period of time, signal on the reseting port of control logic module 11 becomes high level, after another period, low level of time block 12 outputs is to the saltus step of high level, and the logical signal state on control logic module 11 latching logics and the door G5 output port 157 is also exported the control signal corresponding combination.Two line communication port of this device are connected with serial ports or USB USB (universal serial bus), when if the logical signal state on the logical AND gate G5 output port 157 is the L low level, what represent to connect on the two line communication port of this device is the USB USB (universal serial bus), then the logical signal state of the output port 115 of control logic module 11 is L, the logical signal state of the output port 114 of control logic module 11 is H, the output of logic inverter G6 output high level allows signal effective, and serial ports transceiver module 2 and USB transceiver module 3 are in the serial ports transceiver module and close USB transceiver module open mode.When if the logical signal state on the logical AND gate G5 output port 157 is H, what represent to connect on the two line communication port of this device is the asynchronous serial communication interface of full duplex, then the logical signal state of the output port 115 of control logic module 11 is H, logical signal state on the output port 114 of control logic module 11 is L, the output of not gate G6 output low level allows invalidating signal, serial ports transceiver module 2 and USB transceiver module 3 are in the serial ports transceiver module and open USB transceiver module " shut " mode", PMOS is in cut-off state, and a NMOS and the 2nd NMOS are in cut-off state.Another kind of situation is in suspended state for two line communication port of this device, logical signal state on the logical AND gate G5 output port 157 is L, the logical signal state of the output port 115 of control logic module 11 is L, the logical signal state of the output port 115 of control logic module 11 is H, the output of logic inverter G6 output high level allows signal effective, serial ports transceiver module 2 and USB transceiver module 3 are in the serial ports transceiver module and close USB transceiver module open mode USB transceiver module 3 and work in the usb host transceiver mode, wait for and communicating with the USB device that is connected up, PMOS is in opening pattern at full speed, and a NMOS and the 2nd NMOS are in cut-off state.
Claims (8)
1. one kind is used to connect serial ports or universal serial bus structural bus interface devices, this device comprises serial ports transceiver module (2), universal serial bus structural transceiver module (3), external communication ports (4), it is characterized in that interface identification module (1), first lead (D-), second lead (D+), power lead (LV), one end of ground source line (LG) is connected respectively with serial bus architecture transceiver module (3) port, described first lead (D-), second lead (D+), power lead (LV), the other end of ground source line (LG) connects external communication ports (4) respectively, and serial ports transceiver module (2) receiving end (22) connects second lead (D+);
Described interface identification module (1) comprises positive termination first lead (D-) of pull down resistor one (R2), pull down resistor one (R2) negative terminal connects a N channel field-effect pipe (15) drain electrode, positive termination second lead (D+) of pull down resistor two (R3), pull down resistor two (R3) negative terminal connects the drain electrode of the 2nd N channel field-effect pipe (16), first, two N channel field-effect tube grids connect logical AND gate one (G4) output terminal (149), logical AND gate one (G4) input end one (148) connects ternary follower (14) control end (140), logical AND gate one (G4) input end two (147) connects P-channel field-effect transistor (PEFT) pipe (17) grid, ternary follower (14) output terminal (142) connects first lead (D-), ternary follower (14) input end (141) connects serial ports transceiver module (2) transmitting terminal (21), logical AND gate two (G5) input end one (158) connects first lead (D-), logical AND gate two (G5) input end two (159) connects second lead (D+), logical AND gate two (G5) output terminal (157) connects control logic module (11) input end one (111), time block (12) output terminal (121) connects control logic module (11) input end two (112), system reset module (13) output terminal (131) connects control logic module (11) input end three (113), control logic module (11) output terminal one (114) connects ternary follower (14) control end (140), control logic module (11) output terminal two (115) connects P-channel field-effect transistor (PEFT) pipe (17) grid, P-channel field-effect transistor (PEFT) pipe (17) drain electrode connecting resistance one (R1) negative terminal, positive termination second lead (D+) of resistance one (R1), logic inverter one (G6) output terminal (161) is connected with serial bus architecture transceiver module (3) Enable Pin (31), and logic inverter one (G6) input end (162) connects control logic module (11) output terminal two (115).
2. as claimed in claim 1ly be used to connect serial ports or universal serial bus structural bus interface devices, it is characterized in that control logic module (11) is by logic inverter two (G3), logic inverter three (G13), logic inverter four (G14), logic inverter five (G15), first d type flip flop (G7), second d type flip flop (G8) is formed, the data input pin of first d type flip flop (G7), the input end of logic inverter two (G3) is control logic module (a 11) input end one (111), the data input pin of output termination second d type flip flop (G8) of logic inverter two (G3), first, the input end of clock of 2-D trigger is control logic module (a 11) input end two (112), the input end of logic inverter three (G13) is control logic module (a 11) input end three (113), first, the RESET input of 2-D trigger connects the output terminal of logic inverter three (G13), the output terminal of logic inverter five (G15) is control logic module (a 11) output terminal one (114), and the output terminal of logic inverter four (G14) is control logic module (a 11) output terminal two (115); Time block (12) is made up of logic inverter six (G1), electric capacity one (C1), resistance two (R4), and logic inverter six (G1) output terminal is time block (a 12) output terminal (121); System reset module (13) is made up of logic inverter seven (G2), electric capacity two (C2), resistance three (R5), and logic inverter seven (G2) output terminal is system reset module (a 13) output terminal (131).
3. as claimed in claim 1ly be used to connect serial ports or universal serial bus structural bus interface devices, it is characterized in that time block (12) is made up of logic inverter six (G1), electric capacity one (C1), resistance two (R4), 3d flip-flop (G9), the one or four digit counter (G11), first clock (18), 3d flip-flop (G9) output terminal is time block (a 12) output terminal (121); System reset module (13) is made up of logic inverter seven (G2), electric capacity two (C2), resistance three (R5), four d flip-flop (G10), the two or four digit counter (G12), second clock (19), and four d flip-flop (G10) output terminal one (Q) is system reset module (13) output terminal (131).
4. as claimed in claim 1ly be used to connect serial ports or universal serial bus structural bus interface devices, it is characterized in that pull down resistor one (R2), pull down resistor two (R3) resistance is identical and resistance greater than the external serial ports pull-up resistor of twice resistance, pull down resistor one (R2), pull down resistor two (R3) resistance is identical and resistance greater than twice driving resistor resistance.
5. as claimed in claim 2ly be used to connect serial ports or universal serial bus structural bus interface devices, the product value time constant that it is characterized in that electric capacity one (C1) and resistance two (R4) is greater than the product value time constant of electric capacity two (C2) with resistance three (R5).
6. method of operating that is used to connect serial ports or universal serial bus structural bus interface devices as claimed in claim 1, it is characterized in that this method comprises the steps: start-up system reseting module (13), close universal serial bus structural bus transceiver module (3) and serial ports transceiver module (2), after starting time block (12) control delay time, judge first lead (D-), logical signal state on second lead (D+), if first lead (D-), second lead (D+) is gone up logical signal state and is high level signal, open serial ports transceiver module (2) and connect, connect otherwise open universal serial bus structural transceiver module (3).
7. the method for operating that is used to connect serial ports or universal serial bus structural bus interface devices as claimed in claim 6 is characterized in that this method comprises the steps:
State bit timing module (a 12) output signal variable, the delay time variable of definition time block (12) also states that this variable is no symbol sixteen bit variable, setting initial output signal is low level, time block (12) delay time variable is provided with the delay time numerical quantities, and output signal was a high level when circulation of delay time numerical quantities was decremented to zero.
8. the method for operating that is used to connect serial ports or universal serial bus structural bus interface devices as claimed in claim 6 is characterized in that this method comprises the steps:
State a system reset module (13) output signal variable, the delay time variable of define system reseting module (13) also states that this variable is no symbol sixteen bit variable, setting initial output signal is low level, system reset module (13) delay time variable is provided with the delay time numerical quantities and less than the delay time numerical quantities of time block (12), output signal was a high level when circulation of delay time numerical quantities was decremented to zero.
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| CN200710191760A CN100593163C (en) | 2007-12-18 | 2007-12-18 | Interface device used for connecting serial port or general serial bus structure |
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| CN200710191760A CN100593163C (en) | 2007-12-18 | 2007-12-18 | Interface device used for connecting serial port or general serial bus structure |
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| CN100593163C true CN100593163C (en) | 2010-03-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101404001B (en) * | 2008-11-10 | 2010-06-30 | 华为终端有限公司 | Serial port signal and USB signal compatible control circuit board and communication data cable |
| CN102521186B (en) * | 2011-11-22 | 2015-01-14 | 飞天诚信科技股份有限公司 | USB (Universal Serial Bus) key and method for communicating with terminal thereof |
| CN105930293B (en) * | 2016-06-15 | 2019-04-12 | 深圳拓邦股份有限公司 | Serial transceiver interface module and usb interface module common port circuit and working method |
| CN106844274B (en) * | 2016-12-26 | 2019-08-30 | 龙迅半导体（合肥）股份有限公司 | A kind of auxiliary circuit of I2C bus |
| CN110175144B (en) * | 2019-05-14 | 2024-01-19 | 惠州Tcl移动通信有限公司 | USB data transmission control method and related equipment |
| CN114070666B (en) * | 2021-11-10 | 2022-12-20 | 上海裕芯电子科技有限公司 | Bus communication interface circuit and communication method for enhancing bus communication effect |
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