CN100592203C

CN100592203C - Asymmetric high-pressure MOS component grid oxidizing layer protection method and uses thereof

Info

Publication number: CN100592203C
Application number: CN200610118022A
Authority: CN
Inventors: 崔崟; 郭兵; 金起凖; 程超; 梅奎
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2006-11-07
Filing date: 2006-11-07
Publication date: 2010-02-24
Anticipated expiration: 2026-11-07
Also published as: CN101178537A

Abstract

The invention relates to an HV MOS method for the gate oxide of an unsymmetrical device. The corrosion window of the source electrode contact hole of the unsymmetrical device in the SDOP mask is separated from the gate oxide with a certain distance; and then the gate oxide positioned above the contact hole is removed through two steps of dry corrosion and wet corrosion so as to keep the gate oxideentirely.

Description

Asymmetric high-voltage LDMOS device grid oxidizing layer protection method and application thereof

Technical field

The present invention relates to the manufacture method of asymmetric device in the integrated circuit, particularly keep the method for the gate oxide integrity of asymmetric high-voltage LDMOS device.

Background technology

HV MOS (high voltage most) device has critical role in integrated circuit (IC) design and in making.Particularly HV LDMOS (High voltage Laterally DiffusedMetal Oxide semiconductor high pressure LDMOS transistor) just is widely used in the chip for driving of TFT-LCD (Thin Film Transistor_liquid crystal Display, thin film transistor liquid crystal display screen).

And in order to realize higher operating voltage, these devices need adopt thicker gate oxide.For example in the processing procedure of the HVLDMOS of the 0.18 μ m that adopts at present, the thickness of the gate oxide of HVLDMOS has just reached

Thickness.

And in the processing procedure of HVMOS, conventional device has shallow trench isolation structure at source and drain areas (1,2), and still, in the metal-oxide-semiconductor of dissymmetrical structure, the structure of LDD has been adopted itself in source region 1, can reduce size of devices effectively.

But before the LDD ion injected, the gate oxide of source electrode 1 top that needs must be made the asymmetric device of LDD structure etched window and injects so that carry out the LDD ion.Carry out the SDOP etching if adopt self-registered technology, add isotropic performance of wet etching, make in the etching process and also etching away a part of gate oxide in the oxide layer of etching source region downwards to the next door, and because the gate oxide of HVMOS is thicker, downward like this etching is also more, thereby also many to the etching on next door.

And easy surface crystal to active area causes damage in the etching process owing to being dry-etched in, thereby still can adopt the step of a wet etching in etching process.

Such result makes the dissymmetrical structure that adopts prior art to produce can be etched away a part at the edge of the gate oxide below active area POLY, causes grid 3 to be difficult to bear high voltage, has influenced the performance of device.

Summary of the invention

In order to address the above problem, thereby the present invention proposes the method that the gate oxide etching of the asymmetric device of a kind of effective minimizing avoids device performance to descend.

The inventor recognizes if will make the LDD of asymmetric device source electrode and injects the etching window of usefulness to the direction skew certain distance away from gate oxide, make in the oxide layer of etching source region, etching to the next door can not arrive gate oxide, thereby effectively suppresses the problem that source end POLY below gate oxide is etched away.

Thus, the present invention proposes following method and solve the problem that above-mentioned gate oxide partly is etched.

Existing SDOP (Source Drain OPen, opening is leaked in the source) mask is done change, and it is separated by a distance that the etching window that makes the LDD of new SDOP mask in the source region of asymmetric device inject usefulness arrives gate oxide.

Compare in the etching window (see figure 1) that the source electrode LDD of asymmetric device injects usefulness with original SDOP mask like this, source electrode LDD at the quarter injection of the asymmetric device of new SDOP mask (see figure 2) has increased certain distance with the edge of etching window to gate oxide.

After etching process in, because the anisotropy of dry etching, to the etching on next door seldom, so adopt dry etching earlier, etch away the oxide layer of the etching window of most source electrode LDD injection usefulness, thereby, avoid the etching that adopts wet etching to come this part oxide layer strap of etching to the oxide layer by the window.

After dry etching, adopt wet etching to etch away the oxide layer that remaining asymmetric device source electrode LDD injects the etching window of usefulness again, with the source region crystal under the protection window.

In this process, the thickness that dry etching etches away is 80% of gross thickness, and wet etching etches away 20% of gross thickness.

Same as the prior art being not repeated of other processing steps of the present invention.

After adopting the present invention, can make asymmetric device can be when etching source LDD injects the oxide layer of etching window of usefulness to POLY below gate oxide damage, and the drain region of other symmetrical device and asymmetric device can not be affected.Thereby improved the integrality of gate oxide, improved the performance of device.

Description of drawings

Fig. 1 is the window vertical view that source electrode LDD injects the etching window of usefulness on the existing SDOP mask.

Fig. 2 is the window vertical view that source electrode LDD injects the etching window of usefulness on the SDOP mask of the present invention.

Fig. 3 is the gate oxide cut-open view that prior art is produced asymmetric device.

Fig. 4 is to use the gate oxide cut-open view of the asymmetric device of production of the present invention.

Wherein, the 1st, source electrode, the 2nd, drain electrode, the 3rd, grid, the 4th, the zone of etching oxidation layer.

Embodiment

In order to improve the understanding of the present invention, be described further below in conjunction with the drawings and specific embodiments.

In the high tension apparatus of existing 0.18 μ m was used, it was the asymmetric high-voltage LDMOS device of LDD structure that part of devices adopts source electrode 1, and the source electrode 1 of this part of devices does not have shallow isolating trough (STI) structure.

Now the high-voltage LDMOS technology of this dissymmetrical structure is done following improvement.

Adopt new SDOP mask, the etching window edge that the source electrode 1LDD of the asymmetric device of this SDOP mask injects usefulness is increased to 0.2 μ m far from the distance of gate oxide.See Fig. 3

In follow-up etching process, carry out dry etching earlier, adopt about 1.5 minutes fluorocarbon etch to fall the gate oxide of 800A.

Then carry out wet etching, the oxide layer that adopts about 2 minutes HF to etch away remaining 200A forms the etching window that LDD injects usefulness.

Other processing step is identical with the high pressure LDHVMOS processing step of the symmetrical structure of existing 0.18 μ m.

Contrast the gate oxide of existing asymmetric device, see Fig. 3, behind the use present embodiment, the gate oxide of the HVMOS of making is very complete, sees Fig. 4.

Certainly; the present invention can also have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof, those of ordinary skill in the art work as can make various corresponding changes according to the present invention, but these corresponding changes all should belong to the protection domain of claim of the present invention.

Claims

1. the lithographic method of the gate oxide of the asymmetric device of a HV MOS, the modification and the etching technics that contain the graph window of SDOP mask, it is characterized in that the source electrode LDD of asymmetric device in the mask of SDOP is injected the etching window of usefulness away from the gate oxide certain distance, so that in the oxide layer of etching source region, the etching to the next door can not arrive gate oxide.

2. the method for claim 1 is characterized in that the etching technics of oxide layer of the source electrode contact hole top of right title device is made of dry etching and two steps of wet etching.

3. the method for claim 1, it is characterized in that dry etching etch away asymmetric device source electrode contact hole top the oxide layer gross thickness 80%, wet etching etches away 20% of oxide layer gross thickness.

4. the method for claim 1 is characterized in that this method use is in 0.18 μ m high pressure dissymmetrical structure LDMOS device is made.

5. method as claimed in claim 4 is characterized in that in the mask of the SDOP of this device the source electrode LDD of dissymmetrical structure LDMOS device injects the etching window of usefulness apart from grid oxic horizon 0.2 μ m.

6. method as claimed in claim 4, the etching condition that it is characterized in that above-mentioned high pressure dissymmetrical structure LDMOS device source region contact hole oxide layer are to carry out dry etching with fluorocarbon earlier, then remove remaining oxide layer with HF.

7. method as claimed in claim 6, the etching time that it is characterized in that the source region contact hole oxide layer of this asymmetric device is dry etching 1.5 minutes, wet etching 2 minutes.

8. as any high pressure dissymmetrical structure LDMOS device that described method is made in the claim 4～7, it is characterized in that gate oxide is complete.