CN100590599C

CN100590599C - Write-operation process method, system and apparatus of FLASH

Info

Publication number: CN100590599C
Application number: CN200710195568A
Authority: CN
Inventors: 林建加
Original assignee: Fujian Star Net Communication Co Ltd
Current assignee: Beijing Zhigu Ruituo Technology Services Co Ltd
Priority date: 2007-12-06
Filing date: 2007-12-06
Publication date: 2010-02-17
Anticipated expiration: 2027-12-06
Also published as: CN101178678A

Abstract

The invention discloses a write operation processing method, system and device of FLASH, which comprises that: before write operation to FLASH, the data to be changed in FLASH is copied; after finishing the write operation to FLASH, intermitted requirement is made; after receiving the intermitted requirement, entering into the intermitted treatment, and validity judgment is made to the write operation according to the write operation record; when the write operation validity is confirmed, exiting from the intermitted treatment, and if the write operation is confirmed to be illegal, the changeddata is resumed according to the copied data. When the invention is in use, the changed data can be resumed when the write operation is confirmed to be illegal, which realizes that system can not bedamaged by wrong modification even in wrong write operation.

Description

The Write-operation process method of a kind of FLASH, system and equipment

Technical field

The present invention relates to data security, particularly the Write-operation process method of a kind of FLASH, system, FLASH write operation treating apparatus and CPU management system.

Background technology

The FLASH storer claims flash memory again, it is a kind of nonvolatile memory that can onlinely repeatedly wipe, being that data can not lost after the power down, is typical memory device in a kind of embedded system, and FLASH generally is used for the code and the data of storage system work in embedded system.

Parallel FLASH is a kind of of FLASH storer, is called NOR_FLASH again, owing to carry out on the parallel FLASH support code sheet, application program and start-up code can directly be moved on FLASH, so generally are used for the start-up code of storage system in the embedded system.

Parallel FLASH device generally comprises address signal line, data signal line and read-write control line, and the CPU processor reads or writes the FLASH content by above three kinds of signal wires.

Fig. 1 is the pin synoptic diagram of parallel FLASH, and as shown in the figure, the pin of parallel FLASH is represented respectively and is in the example:

RESET is the reseting pin of chip;

CE is the chip selection signal line of chip;

WE is the write line of chip;

OE is the control line of reading of chip;

VCC is the power supply input pin of chip;

VSS is the ground pin of chip;

BYTE is the working mode selection pin of chip, and chip operation was 16 mode of operations when BYTE connect high level, and chip operation is 8 mode of operations during BYTE ground connection;

The write-protect pin of WP/ACC chip, chip did not allow to be modified when WP connect low level;

The data signal line of DQ0-DQ7 chip operation under 8 bit patterns;

The data signal line of DQ8-DQ15 chip operation under 16 bit patterns;

A0, A1, A2 are the address wire of chip operation under 16 mode of operations to A20;

A-1, A0, A1 are the address wire of chip operation under 8 mode of operations to A20.

Wherein:

Address wire: be used for the signal wire of transport addresses information, as the A0 among Fig. 1, A1 etc.

Data line: be used for the signal wire of transmitting data information, as the DQ0-DQ7 among Fig. 1.

Control signal wire: be used for the signal wire of control information transmission, such as information such as read-write selections.

Fig. 2 is a FLASH connected mode structural representation in the read-write system, and as shown in the figure, management system 200 in the read-write system and FLASH201 link together by address wire, reading signal lines, write signal line, chip selection signal line.Wherein:

Management system 200 is finished the control of total system, comprises the read-write operation of initiation to FLASH201;

FLASH201 is used for normal code of storage system work and data, accepts the read write command that management system sends.

Write signal line: be used for when management system will be carried out write operation to FLASH, this signal wire pin being changed to low level.

Write-protect pin two 03 is directly connected to high level, allows the write operation behavior of management system, and high level generally is the voltage of 3.3V, and the write-protect pin is the WP pin among Fig. 1.

Management system 200 is by the duty of serial ports 204 output systems.

Traditional electronics read-write system is write the following several situations of the general existence of operation of FLASH:

1, starting and upgrading BOOT code (BIOS that is equivalent to PC);

2, upgrading master routine (being equivalent to WINDOWS operating system);

3, record trouble information (being equivalent to when using PC to make mistakes the daily record of PC misregistration);

4, information-setting by user (parameter of similar modification BIOS).

More than four kinds of operations are general only is used in certain condition, it is known when calling on these theory of operation, determine, but, because artificial or some other objective reason make can cause these operations by wrong calling, such as because system designer's carelessness, when some should not write FLASH, call and write the FLASH operation, that is to say that the deficiencies in the prior art are: write operation also exists the abnormal conditions of calling should not be invoked the time, and the system start-up code and the master routine that just might cause when these abnormal conditions take place are destroyed, and then will cause the system can't operate as normal.

Summary of the invention

The invention provides a kind of method, system, device and CPU management system that the write operation of FLASH is handled, in order to solve the problem of after abnormal conditions cause system start-up code and master routine destroyed, recovering.

The invention provides the Write-operation process method of a kind of FLASH, comprise the steps:

Before FLASH is carried out write operation, the data that will be rewritten among the FLASH are backed up;

After the FLASH write operation is finished, initiate interrupt request;

After receiving interrupt request, enter Interrupt Process, according to the write operation record described write operation is carried out legitimacy and judge;

When definite described write operation is legal, withdraw from Interrupt Process, when definite described write operation is illegal, the data that recovery is rewritten according to Backup Data.

The present invention also provides the write operation disposal system of a kind of FLASH, comprises management system, also comprises:

Backup module is used for before FLASH is carried out write operation the data that will be rewritten among the FLASH being backed up;

Request module is used for after the FLASH write operation is finished, and initiates interrupt request to judge module;

Judge module, link to each other with described request module, described management system, be used for after receiving interrupt request, entering Interrupt Process, write operation record according to management system carries out the legitimacy judgement to described write operation, when definite described write operation is legal, withdraw from Interrupt Process, when definite described write operation is illegal, triggers and recover module;

Recover module, link to each other, be used for the data of being rewritten according to the Backup Data recovery of described backup module with described judge module, described backup module.

The invention provides a kind of CPU management system, comprise management system, also comprise:

Judge module is used for entering Interrupt Process after receiving interrupt request, according to the write operation of management system record described write operation is carried out legitimacy and judge, when definite described write operation is legal, withdraw from Interrupt Process, when definite described write operation is illegal, triggers and recover module;

Beneficial effect of the present invention is as follows:

The present invention is when carrying out write operation to FLASH, at first the data that will be rewritten among the FLASH are backed up, making management system carry out legitimacy to write operation by interrupt request judges, when definite write operation is illegal, then can recover the data rewritten according to Backup Data, even thereby behind the write operation of feasible appearance mistake, can not cause systemic breakdown because of bug patch yet.

Description of drawings

Fig. 1 is the pin synoptic diagram of parallel FLASH described in the prior art;

Fig. 2 is a FLASH connected mode structural representation in the read-write system described in the prior art;

Fig. 3 is the synoptic diagram of Interrupt Process apparatus structure described in the prior art;

Fig. 4 is to the Write-operation process method implementing procedure synoptic diagram of FLASH described in the embodiment of the invention;

Fig. 5 is the write operation disposal system structural representation of FLASH described in the embodiment of the invention;

Fig. 6 is the treating apparatus of FLASH write operation described in an embodiment of the invention structural representation;

Fig. 7 is the structural representation of CPU management system described in the embodiment of the invention;

Fig. 8 is the disposal system of FLASH write operation described in the embodiment of the invention one structural representation;

Fig. 9 is the implementing procedure synoptic diagram of write operation disposal system described in the embodiment of the invention one.

Embodiment

Below in conjunction with accompanying drawing the specific embodiment of the present invention is described.

In the prior art, when FLASH is carried out write operation, when the abnormal conditions that write operation but has been called should not be invoked the time take place after, because the write-protect pin of FLASH directly connects high level, and FLASH is a kind of non intelligent device, therefore, no matter whether the write operation that management system is initiated is legal, as long as management system is initiated write operation, FLASH just allows to rewrite; In addition on the one hand, detect the testing circuit existence of writing the FLASH operation, also can't be found and recover even management system is initiated wrong write operation owing to be not used in.This has also just caused if wrong write operation, and will cause the content of FLASH inside destroyed, and then causes the system can't operate as normal.

Further, owing to can not detect mistake in the system, after making a mistake, the software coding personnel can't confirm also the end is where problem has appearred in code logic.

Based on above analysis, the present invention is in conjunction with the interrupt processing mechanism of CPU, the write operation of FLASH handled improved, and makes it be subjected to protecting more fully.Following elder generation briefly introduces interrupt mechanism.

Interrupt mechanism is the important technology that CPU handles outside accident.It can make CPU in operational process the interrupt request that external event sends be handled timely, when interrupt request is handled, the program that CPU interrupts carrying out is changeed get a haircut out the task of interrupt request of place to go, returns breakpoint after finishing dealing with again immediately, proceeds the original work of CPU.The source that the reason that causes interruption is sent interrupt request in other words is called interrupt source, according to the difference of interrupt source, can be interrupting being divided into hardware interrupts and software interruption two big classes, and hardware interrupts can be divided into external interrupt and internal interrupt two classes.

Fig. 3 is an Interrupt Process apparatus structure synoptic diagram, as shown in the figure, comprises CPU300 in the treating apparatus, interrupts producing circuit 301, state working storage 302, describes interrupting below in conjunction with Fig. 1.

The interrupt pin that external interrupt is generally processor is directly passed to CPU.Interrupt being the external interrupt source as INT0～4 of Fig. 3, in the normal course of operation of system, state working storage 302 is received as after the variation of INTO interrupt pin generation level, state working storage 302 triggers and interrupts producing the present software processes of circuit 301 generation interrupt notification CPU300 interruptions, then the Interrupt Process that enters INT0.

The interruption that internal interrupt is produced under certain situation by CPU inter-process module, internal interrupt priority generally is lower than external interrupt.UART as shown in Figure 1 and TIMER transmitting-receiving are interrupted, in the normal course of operation of system, state working storage 302 is received the data as sending over from UART, state working storage 302 triggers and interrupts producing circuit 301 generation interrupt notification CPU300, CPU300 interrupts present software processes, then the Interrupt Process that enters UART.

In conjunction with interrupt mechanism, the present invention detects judgment mechanism by adding in circuit, when FLASH is carried out write operation, initiates to interrupt, and notice CPU carries out Interrupt Process, and Interrupt Process is used to judge whether current write operation is legal.

Based on above-mentioned analysis, to how specifically to implement describe below.

Fig. 4 is the Write-operation process method implementing procedure synoptic diagram to FLASH, be clearer description the invention process, be considered as including management system among the CPU of handling interrupt, this management system can be carried out record to the legal operation of carrying out, then as shown in the figure, can comprise the steps: during processing

Step 401, the data that will be rewritten among the FLASH are backed up.

Step 402, FLASH is carried out write operation.

Step 403, FLASH write operation are finished.

In this step, know the FLASH write operation is finished, can know that write operation finishes with following mode, after finishing at write operation, management system is sent write operation and is finished instruction triggers and initiate interrupt request; Also can know, can also write down by the Disk Logs of write operation and know, know that it is that those skilled in the art are easy to know that write operation is finished by the write operation release that detects on the FLASH hardware.A kind of easy mode of knowing is provided in the present embodiment,, can have known that write operation finishes when sampling FLASH write signal and FLASH chip selection signal line when low.

Step 404, initiation interrupt request.

In this step, can after the FLASH write operation is finished, receive write operation and finish instruction back initiation interrupt request receiving the write operation instruction;

Or, though do not receive the write operation instruction, when sampling FLASH write signal and FLASH chip selection signal line, initiate interrupt request for low level;

Or, after receiving the write operation instruction, do not finish when instructing but in the setting-up time threshold value, receive write operation, also send interrupt request.

Step 405, receive interrupt request, enter Interrupt Process.

Step 406, write operation is carried out legitimacy judge, when definite write operation is legal, change step 407 over to, otherwise change step 408 over to, can carry out the legitimacy judgement according to the write operation record of management system in this step.

Step 407, withdraw from Interrupt Process.

Step 408, when definite write operation is illegal, recover the data rewritten according to Backup Data.

Step 409, location write operation mistake occurrence cause.

Step 410, error reason is exported.

From above-mentioned enforcement as can be seen, the present invention is when definite write operation is illegal, will recover according to backed up data when the write operation, thereby overcome in the prior art in case the deficiency that can't be found and recover behind the write operation of initiation mistake has improved the security to the write operation of FLASH.

Further, when handling, can also comprise the steps: in the enforcement

After receiving when FLASH carried out the instruction of write operation, closing write-protect, carry out write operation to FLASH;

The FLASH write operation is finished, received write operation and finish when instructing; Or, do not receiving write operation when instruction, when sampling FLASH write signal and FLASH chip selection signal line when being low level; Or, receive write operation instruction after, in the setting-up time threshold value, do not receive write operation when finishing instruction, open write-protect to FLASH.

In the enforcement; not only can whether finish the write-protect that determines whether opening to FLASH by detection write operation initiatively; can also open write-protect by the instruction triggers that the write operation that receives is finished to FLASH; what the instruction that this write operation is finished was concrete can be sent after write operation is finished by the CPU management system; can also be after entering Interrupt Process, judge write operation and send this instruction after illegal and instruct the write-protect of closing in order to open by illegal write operation.

FLASH is carried out write-protect specifically can realize opening write-protect by after FLASH write-protect pin is placed low level to FLASH.The write-protect purpose of opening FLASH is, opens the back and just can not carry out write operation to FLASH again.

Above-mentioned write-protect purpose mainly is the write-protect pin by control FLASH; reach and when working at ordinary times, do not allow illegal write operation; overcome because the write-protect pin of FLASH is in open mode at ordinary times always; the deficiency that the probability that causes system to be rewritten by mistake increases; thereby reduced the probability that FLASH is rewritten, alleviated the load of management system.

In the foregoing description, can at the situation that exists mainly contain: starting and upgrading BOOT code, upgrading master routine, record trouble information, information-setting by user, below the processing of these four kinds of situations in implementing is come that the present invention will be described, but easily know, by method of the present invention, that is: after detecting mistake, faulty operation is recovered, the visible soluble problem of the present invention is not limited in only in these four kinds of situations.Describe as follows to four kinds of situations below:

If find that in step 401 current write operation is that the code of BOOT is made amendment, then the judgement of the legitimacy in step 406 is and judges whether current task is the task of allowing upgrading BOOT, if be legal, then allow upgrading BOOT, withdraw from Interrupt Process; Otherwise be illegal, recover the code that is modified in the execution in step 408;

If in the write operation in step 401, whether the address of current operation FLASH is to make amendment at the storage space of master routine, if, then the judgement of the legitimacy in step 406 is and judges whether the current task of calling write operation is to appoint the task of allowing to revise master routine, if be legal, then do not handle, withdraw from Interrupt Process; Otherwise be illegal, recover the code that is modified in the execution in step 408;

Equally, failure message record, user's configuration also can detect by similar method.

Further, when finding the write operation mistake, in step 409, can produce the debugging code that external interrupt signal triggers management system, be used for the software logic that the helper applications personnel locate errors and avoid follow-up faulty operation, lower the hidden danger that the FLASH of system is rewritten by system.

The present invention also provides write operation disposal system, FLASH write operation treating apparatus and the CPU management system of a kind of FLASH, below in conjunction with accompanying drawing its embodiment is described.

Fig. 5 is the write operation disposal system structural representation of FLASH; as shown in the figure; native system is used for that FLASH201 is carried out write operation to be handled; comprise management system 200, backup module 501, request module 502, judge module 503 in the system, recover module 504, locating module 505, output module 506, write-protect module 507, describe with the example that is embodied as of native system below FLASH201.

Backup module 501 links to each other with FLASH201, is used for when FLASH is carried out write operation the data that will be rewritten among the FLASH201 being backed up;

Request module 502 links to each other with judge module 503, FLASH201, is used for after the FLASH201 write operation is finished, and initiates interrupt request to judge module 503;

Judge module 503 links to each other with management system 200, be used for after receiving interrupt request, entering Interrupt Process, write operation record according to management system carries out the legitimacy judgement to described write operation, when definite described write operation is legal, withdraw from Interrupt Process, when definite described write operation is illegal, triggers and recover module 504;

Recover module 504 and link to each other, be used for the data of being rewritten according to the Backup Data recovery of backup module 501 with judge module 503, backup module 501.

In request module 502, can comprise detecting unit and request unit, wherein:

Detecting unit is finished the FLASH write operation, receives after write operation finishes instruction; Or, do not receiving write operation when instruction, when sampling FLASH write signal and FLASH chip selection signal line when being low level; Or, receive write operation instruction after, in the setting-up time threshold value, do not receive write operation when finishing instruction, the trigger request unit;

Request unit is initiated interrupt request to judge module after detected unit triggers.

From above-mentioned enforcement as can be seen, when judge module determines that write operation is illegal, will trigger and recover module and recover according to backup module backed up data when the write operation, thereby overcome in the prior art in case the deficiency that can't be found and recover behind the write operation of initiation mistake has improved the security to the write operation of FLASH.

Can further include the locating module 505 that links to each other with judge module 503 in the system, be used for when definite described write operation is illegal, locating described write operation mistake occurrence cause according to the judged result of judge module.

Can further include output module 506 in the system and link to each other, be used for the write operation occurrence cause output that locating module is oriented with locating module 505.Concrete can export by the serial ports 204 on the residing CPU management system of management system.

As can be seen, produce external interrupt signal by system after, the debugging code of triggered location module can be used for the software logic that the helper applications personnel locate errors and avoid follow-up faulty operation, lowers the hidden danger that the FLASH of system is rewritten.

Further can also comprise the write-protect module 507 that links to each other with FLASH201 in the system, be used for FLASH being carried out write-protect according to write operation instruction to FLASH.

Concrete, can comprise in the write-protect module:

Write operation command reception unit, be used for receive FLASH carried out the instruction of write operation after, trigger the set unit;

The set unit is used for closing the write-protect to FLASH after by described write operation command reception unit triggers, and the FLASH write operation is finished, and receives write operation when finishing instruction; Or, do not receiving write operation when instruction, when sampling FLASH write signal and FLASH chip selection signal line when being low level; Or, receive write operation instruction after, in the setting-up time threshold value, do not receive write operation when finishing instruction, open write-protect to FLASH.

The set unit can link to each other with the write-protect pin of FLASH201, when the write-protect of closing FLASH the write-protect pin is placed low level, when the write-protect of opening FLASH the write-protect pin is placed high level.

As can be seen; write-protect pin by write-protect module controls FLASH; reached and when working at ordinary times, do not allowed illegal write operation; overcome because the write-protect pin of FLASH is in open mode at ordinary times always; the deficiency that the probability that causes system to be rewritten by mistake increases; thereby reduced the probability that FLASH is rewritten, alleviated the load of management system.

Fig. 6 is a FLASH write operation treating apparatus structural representation, as shown in the figure, comprises request module 502, write-protect module 507 in the device, wherein:

Request module 502 is used for after the FLASH write operation is finished, and initiates described write operation is carried out the interrupt request that legitimacy is judged.

Request module can comprise in the device:

Detecting unit 5021 is used for the FLASH write operation is finished, and receives after write operation finishes instruction; Or, do not receiving write operation when instruction, when sampling FLASH write signal and FLASH chip selection signal line when being low level; Or, receive write operation instruction after, in the setting-up time threshold value, do not receive write operation when finishing instruction, the trigger request unit;

Request unit 5022 is used for being triggered the back by described detecting unit to management system initiation interrupt request; Described interrupt request is used to trigger management system described write operation is carried out the legitimacy judgement.

Can further include write-protect module 507 in the device, be used for FLASH being carried out write-protect according to write operation state to FLASH.

Can comprise in the write-protect module:

Write operation command reception unit 5072 is used for triggering the set unit when receiving the instruction that FLASH is carried out write operation and enter the write operation state;

Set unit 5071 is used for closing the write-protect to FLASH after by described write operation command reception unit triggers, and the FLASH write operation is finished, and receives write operation when finishing instruction; Or, do not receiving write operation when instruction, when sampling FLASH write signal and FLASH chip selection signal line when being low level; Or, receive write operation instruction after, in the setting-up time threshold value, do not receive write operation when finishing instruction, open write-protect to FLASH.

The set unit can link to each other with the write-protect pin of FLASH, when FLASH is carried out write-protect the write-protect pin is placed low level, places high level to realize write-protect the write-protect pin when opening write-protect.

Fig. 7 is a CPU management system structural representation, as shown in the figure, can comprise in the system: backup module 501, management system 200, judge module 503, recovery module 504, wherein:

Backup module 501 is used for before FLASH is carried out write operation the data that will be rewritten among the FLASH being backed up;

Judge module 503 enters Interrupt Process after receiving interrupt request, write operation record according to management system 200 carries out the legitimacy judgement to described write operation, when definite described write operation is legal, withdraws from Interrupt Process, when definite described write operation is illegal, triggers and recover module 504;

Recover module 504, link to each other, be used for the data of being rewritten according to the Backup Data recovery of described backup module with described judge module 503, described backup module 501.

Can further include locating module 505 in the CPU management system, be used for when definite described write operation is illegal, locating described write operation mistake occurrence cause according to the judged result of judge module 503.

The CPU management system can further include output module 506, is used for the described write operation mistake occurrence cause output that locating module 505 is oriented.

With embodiment one the specific embodiment of the present invention is described again below.

Embodiment one

Will be in this example with CPLD (Complex Programmable Logic Device, CPLD) enforcement describes, CPLD is a kind of programmable logic device (PLD), it can be after manufacturing is finished defines its logic function by the user according to oneself needs, generally is used to realize some simple user customized logics in electronic system.Obviously; use CPLD just can realize the function of above-mentioned request module, write-protect module; simultaneously; also used the CPU management system that comprises management system in the previous embodiment in the enforcement; because the CPU management system is an operation system of software; realizing the function of backup module, receiver module, judge module, locating module, output module, recovery module in this CPU management system, also is easy to know for a person skilled in the art.It may be noted that simultaneously, can in CPU management system or CPLD or other entities, realize different functional modules as required during enforcement, be not limited in the embodiment in this example, such as, backup module, recover module and not only can on the CPU management system, realize, also can possess on the entity of data storage function, reading and writing data function and realize with other.Utilizing existing CPLD to implement then can implement as follows when of the present invention:

Fig. 8 is the FLASH write operation disposal system structural representation of embodiment one, and as shown in the figure, system is made up of CPLD801, FLASH201, CPU management system 800 and the serial ports 204 that links to each other with the CPU management system, wherein:

CPU management system 800 sends read write command by bus and is used to control CPLD801;

CPU management system 800 sends read write command to FLASH201 by reading signal lines, write signal line, data line, address wire etc.;

CPLD801 is used to notify CPU management system 800 handling interrupt requests timely, i.e. write operation of Fa Shenging by INT (the external interrupt signal line of management system);

CPLD801 is by the write-protect pin two 03 of a pin 802 control FLASH201; under working condition at ordinary times; the level output low level of this pin; do not allow FLASH to finish write operation; only receive write operation instruction triggers that the CPU management system sends and close and just send high level write-protected the time, this time, FLASH just can accept the write operation of management system.

Fig. 9 is the implementing procedure synoptic diagram of write operation disposal system among the embodiment one, and then as shown in the figure, the write operation flow process of above-mentioned write operation disposal system can be as follows:

Step 901, CPU management system notice CPLD open the write-protect pin and allow write operation.

Concrete, in this step by the write-protect module on the CPLD being sent the write operation instruction, thereby make the write-protect module close write-protect to FLASH so that carry out write operation.

The FLASH content that step 902, the backup of CPU management system are rewritten is to the internal memory of system.

In concrete the enforcement, be not limited in and back up to internal memory, know that easily all data storage mediums can realize.

Step 903, CPU management system are initiated write operation, and FLASH accepts write operation.

Step 904, CPU management system wait write operation are finished.

Step 905, CPU management system notice CPLD close the write-protect pin and forbid illegal write operation.

In step 904,905, not only can after write operation is finished, send the write-protect module that write operation finishes among the instruction notification CPLD and close by the CPU management system, can also behind unusual write operation, close by the CPLD active detecting.

In the enforcement; wrong write operation instruction may appear sending; also thereby do not have the correctly corresponding with it write operation described in the step 905 to finish instruction to make FLASH enter write-protect; in the case; the write-protect module can make FLASH enter the write-protect state behind unusual write operation by active detecting; after also can judging this write operation and be illegal operation, send write operation again and finish instruction and make FLASH enter the write-protect state by interrupt request.

Step 906, CPLD close the write-protect pin and forbid illegal write operation.

In the above-mentioned steps 904,905,906, be not limited in step 904 the CPU management system after waiting for that write operation is finished, send a kind of embodiment that write operation is finished instruction to CPLD, though also can be that CPLD does not receive write operation instruction, when sampling FLASH write signal and FLASH chip selection signal line when being low level; Or; receive the write operation instruction; but not receiving write operation in the setting-up time threshold value finishes when instructing; CPLD also initiatively closes the write-protect pin; its reason is that write operation might not be initiated by the write operation instruction by the CPU management system, and write operation might carry out under the unwitting situation of CPU management system; for better FLASH being carried out write-protect, CPLD also can close the write-protect pin not receiving when write operation is finished instruction.

Step 907, CPLD produce look-at-me (INT) notice CPU management system write operation and finish.

The sending look-at-me and can be of this step: CPLD receives the write operation instruction, and after the FLASH write operation was finished, CPLD received write operation and finishes the instruction back and initiate interrupt request;

Or, do not receive write operation when instruction at CPLD, when CPLD sample the FLASH write signal with FLASH chip selection signal line initiation interrupt request during for low level;

Or, after CPLD receives the write operation instruction, not finishing when instructing but in the setting-up time threshold value, receive write operation, CPLD sends interrupt request.

The external interrupt of step 908, CPU management system response INT enters interrupt handling routine.

Step 909, CPU management system confirm whether present write operation is legal, if legal then change step 910 over to, otherwise would change step 911 over to.

Step 910, withdraw from Interrupt Process.

Step 911, CPU management system are located the possible mistake of current write operation.

The FLASH content that step 912, the recovery of CPU management system are rewritten.

Step 913, CPU management system are exported information by serial ports, the software code of prompting user's modification management system.

Be used to detect the behavior of incorrect rewriting FLASH in the present embodiment by interpolation CPLD in circuit.Whether be the write operation that be allowed to management system if all write operation being checked affirmation after each write operation is finished.If finding the wrong FLASH that writes operates, the CPU management system is responsible for recovering the FLASH content of being rewritten, thereby the FLASH that avoids old design system is owing to being caused systemic breakdown by CPU management system bug patch, and by the modification of mistake, the master routine of system is destroyed such as the system start-up code.

Pass through in the enforcement when the CPU management system is initiated write operation, to produce the debugging code that external interrupt signal triggers the CPU management system by CPLD, just the software logic that can the helper applications personnel locates errors has lowered the hidden danger that system FLASH is rewritten to avoid follow-up faulty operation.

Also when working at ordinary times, do not allow illegal write operation simultaneously, further reduced the probability that FLASH is rewritten, alleviate the load of management system by controlling the write-protect pin of FLASH, reaching.

By the foregoing description as can be known, by detecting write operation, and occurring carrying out error handling processing behind the wrong write operation among the present invention, improving the efficient that the peopleware finds the error-logic of software code FLASH.Further can reach the operation that allows and forbid writing FLASH, lower the probability that FLASH is write by mistake by the high-low level of control WP pin.And after the operation of writing FLASH that detects each CPU management system initiation, notice CPU management system confirms whether current write operation is legal, and will recover by the FLASH content of wrong rewriting, and the system that makes can recover when the write operation mistake occurring.

Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.

Claims

1, the Write-operation process method of a kind of FLASH is characterized in that, comprises the steps:

After the FLASH write operation is finished, initiate interrupt request;

2, the method for claim 1 is characterized in that, when definite described write operation is illegal, further comprises the steps:

Locate the illegal occurrence cause of described write operation.

3, method as claimed in claim 2 is characterized in that, orient the illegal occurrence cause of described write operation after, further comprise the steps:

With the illegal occurrence cause output of described write operation.

4, the method for claim 1 is characterized in that, and is described after the FLASH write operation is finished, and initiates interrupt request and is specially:

The FLASH write operation is finished, received write operation and finish instruction back initiation interrupt request;

Or, when not receiving the write operation instruction, when sampling FLASH write signal and FLASH chip selection signal line, initiate interrupt request for low level;

Or, receive write operation instruction after, in the setting-up time threshold value, do not receive and send interrupt request when write operation is finished instruction.

5, as the arbitrary described method of claim 1 to 4, it is characterized in that, further comprise the steps:

Receiving when FLASH carried out the instruction of write operation, close write-protect to FLASH, carry out write operation;

6, the write operation disposal system of a kind of FLASH comprises management system, it is characterized in that, also comprises:

7, system as claimed in claim 6 is characterized in that, the described request module comprises:

Detecting unit is used for the FLASH write operation is finished, and receives after write operation finishes instruction; Or, do not receiving write operation when instruction, when sampling FLASH write signal and FLASH chip selection signal line when being low level; Or, receive write operation instruction after, in the setting-up time threshold value, do not receive write operation when finishing instruction, the trigger request unit;

Request unit is used for being triggered the back by described detecting unit to described judge module initiation interrupt request.

8, system as claimed in claim 6 is characterized in that, further comprises locating module, links to each other with described judge module, is used for locating the illegal occurrence cause of described write operation according to the judged result of described judge module when definite described write operation is illegal.

9, system as claimed in claim 8 is characterized in that, further comprises output module, links to each other with described locating module, is used for the illegal occurrence cause output of described write operation that described locating module is oriented.

10, as the arbitrary described system of claim 6 to 9, it is characterized in that, further comprise the write-protect module, be used for FLASH being carried out write-protect according to write operation instruction to FLASH.

11, system as claimed in claim 10 is characterized in that, described write-protect module comprises:

12, a kind of CPU management system comprises management system, it is characterized in that, also comprises:

13, system as claimed in claim 12 is characterized in that, further comprises locating module, is used for locating the illegal occurrence cause of described write operation according to the judged result of described judge module when definite described write operation is illegal.