CN100583653C - An encoding method, decoding method and decoder of LDPC cascade connection code - Google Patents

Abstract

The invention discloses a design scheme of LDPC cascaded code, which is an LDPC-SPC product code which takes LDPC code as horizontal code and SPC code as vertical code, and each bit of an SPC code word is acquired by the even parity check of the bits in corresponding positions of n LDPC code words. The scheme can solve the flat bed of error codes of the LDPC code and has higher flexibility and greater encoding gain than the cascaded methods of BCH code. The invention simultaneously provides an encoding method of the LDPC-SPC product code and two decoding methods (a hard decision method and a soft decision iteration method), and provides corresponding decoders. The LDPC-SPC product code provided by the invention can acquire greater encoding gain with very small redundancy cost and is a signal channel encoding scheme which is applicable to delay-insensitive businesses.

Description

A kind of coding method of LDPC cascaded code, interpretation method and decoder thereof

Technical field

The present invention relates to a kind of channel coding technology, especially a kind of structure of LDPC cascaded code and interpretation method belong to areas of information technology.

Background technology

Channel coding technology is as the basic fundamental that guarantees the communication system reliable transmission, obtaining develop rapidly over past ten years, with Turbo code, LDPC sign indicating number (low density parity check code) is that the chnnel coding that large quantities of performances of representative can the approximation theory limit is found and obtains further investigation in succession, wherein the LDPC sign indicating number has especially obtained concern in recent years, this yard is because have error-correcting performance that approaches shannon limit and the simple decoding algorithm that is suitable for parallel computation, so adopted, as DVB-S2, WiMAX etc. by many communication standards.This shows that the LDPC sign indicating number will become a kind of main flow chnnel coding in the communication system in following one period considerable time.

By nearly shannon limit sign indicating number such as Turbo code, LDPC sign indicating number discovered that different with all in the past chnnel codings, the ber curve of nearly shannon limit sign indicating number can be divided into waterfall (waterfall) district and flat bed (floor) is distinguished two zones.In the waterfall district, the bit error rate of nearly shannon limit sign indicating number descends fast along with the increase of Normalized Signal/Noise Ratio, and the bit error rate curve looks at this moment almost perpendicular to the x axle.At leveling zone, the bit error rate of nearly shannon limit sign indicating number increases the speed that descends with Normalized Signal/Noise Ratio and obviously slows down with respect to the waterfall district, even might no longer descend, the bit error rate curve looks the platform that is parallel to the x axle just as at this moment, error code flat bed (Error Floor) hence obtains one's name.

Mainly caused differently by its little weight code word with the error code flat bed of Turbo code, (AdditiveWhite Gaussian Noise, AWGN) under the channel, the error code flat bed of LDPC sign indicating number mainly is to catch collection (trappingset) decision by it at additive white Gaussian noise.When the error code flat bed of LDPC sign indicating number occurred, iterative decoding algorithm converged to a probability on " approximate code word " (the near code word) close with correct code word and also increases.Should " approximate code word " can satisfy most check equations constraint.Therefore, the error code flat bed phenomenon of LDPC sign indicating number has following two characteristics, the one, longer at the code length of LDPC sign indicating number, when for example reaching thousands of bit length, its error code flat bed is mainly by " approximate code word " decision, because they can not satisfy all verification relations, so wrong code word can detect by decoded device; The 2nd, because " approximate code word " is very close with correct code word, the error bits numbers in each wrong code word can be not a lot.

For example: length is 8064 bits, the LDPC sign indicating number of 1/2 code check, and its error code curve is as shown in Figure 1.This LDPC sign indicating number begins to occur the error code flat bed when Normalized Signal/Noise Ratio equals 1.5dB, for its error code flat bed is analyzed, added up the LDPC sign indicating number code word of 200 mistakes separately when Normalized Signal/Noise Ratio is respectively 1.5dB and 1.6dB.

Statistics shows that under two Normalized Signal/Noise Ratios, 200 wrong code words that count on separately all can not satisfy the verification relation of H matrix, therefore can both be detected by ldpc decoder, meet characteristics one above-mentioned.Secondly, as seen from Figure 2, under two signal to noise ratios, separately in Tong Ji 200 wrong code words, although the statistics of the code word number that error bits numbers surpasses 10 bits during 1.5dB during slightly more than 1.6dB, but under two signal to noise ratios, a code word has situation about making a mistake above 10 bits all to be no more than 10%, and maximum error bits numbers also only is 25 bits.Error bits numbers is far smaller than code length 8064 bits, and this statistics has well met second characteristic about LDPC sign indicating number error code flat bed above-mentioned.What is interesting is, can also find, reach maximum iteration time at decoder from Fig. 2, during decoding failure, the wrong LDPC code word that suitable ratio arranged is only wrong 1 bit.It is because the check equations that error bit participates in has comprised near the bit of the soft information of two or more confidence levels 0 usually that this phenomenon takes place.In the iterative process each time of sum-product algorithm, the soft information of the confidence level of the bit that these confidence levels are very low will constantly be overturn up and down 0, makes ldpc decoder can't converge to correct code word all the time.

When the error code flat bed appears in the LDPC sign indicating number, occur in same position in order to analyze the error bit whether a plurality of wrong code words are arranged, position to error bit is added up separately when Normalized Signal/Noise Ratio is respectively 1.5dB and 1.6dB, as can see from Figure 3, under two Normalized Signal/Noise Ratios, once mistake has all only taken place in the bit position that the overwhelming majority makes a mistake, and the bit position that twice and twice above mistake takes place only accounts for 20% of all error bit positions.If every n LDPC code word once added up, in this n LDPC code word, taken place twice or twice above wrong bit position so, ratio is just littler.For example make n=100, if in per 100 LDPC sign indicating number code words, mistake two or more code words, so in these wrong code words, taken place twice or twice above wrong bit position less than 1% of all error bit positions.That is to say in 100 LDPC code words seldom have same bit position to occur twice or twice above mistake.

Error code flat bed phenomenon requires the realization of the very high communication system of error performance to bring puzzlement to many.Therefore be an important research direction of field of channel coding in recent years for the research of LDPC sign indicating number error code flat bed always.At present, the method that overcomes LDPC sign indicating number error code flat bed mainly contains three kinds, a kind of is the method for algebraically, mainly the LDPC sign indicating number that has a very big minimum distance by structure reaches the purpose that reduces the error code flat bed, this shortcoming is to have the LDPC sign indicating number of bigger minimum distance, and often performance is not ideal enough, and the parameter that can construct is also discontinuous; Second method then is to adopt the ACE criterion in the construction process of LDPC sign indicating number, has lower decoding threshold though this method can be constructed, and its effect that reduces the error code thresholding is more limited; The third method is carried out cascade with LDPC sign indicating number and BCH code exactly, and this also is the most frequently used method.This method is outer sign indicating number with BCH, and LDPC is an ISN, and information code word to be encoded is introduced into the Bose-Chaudhuri-Hocquenghem Code device, generates the Bose-Chaudhuri-Hocquenghem Code code word, enters the LDPC encoder afterwards again and generates final coding output code word.Decoding is the inverse process of coding, and the code word that receives is introduced into the LDPC decoder, decodes the BCH code word, sends into the BCH decoder and decodes, and exports final decoded result.

A large amount of simulation results show, the LDPC-BCH cascaded code can be effectively be reduced to 10 with the error code flat bed of LDPC sign indicating number ^-11Below, can satisfy the demand of most systems.But this method has two main shortcomings, the one, and redundant cost is higher, because BCH code does not have simple Soft decision decoding algorithm, can only adopt the hard decision algorithm usually, and the coding gain loss is very big; The 2nd, actual communication systems often has many different code checks, and this just requires BCH code for the LDPC sign indicating number of different code checks provides different code lengths and different error correcting capabilities, has increased the difficulty of code cascading scheme design and the complexity of coding/decoding system.

Summary of the invention

At the above-mentioned present situation of LDPC sign indicating number, in order better to reduce the error code flat bed of LDPC sign indicating number, improve the error performance of LDPC sign indicating number, the present invention proposes a kind of new better LDPC code cascading scheme, and provided its coding and decoding scheme.Concrete encoding scheme is as follows:

1. initialization: message bit stream framing;

2. every n information frame is done mould 2 Hes at the bit of relevant position, wherein, n is a positive integer, can select according to actual needs.Promptly n+1 redundant frame is $c_{n+1}^j=\underset{k=1}{\overset{n}{\mathrm{\&Sigma;}}}{c}_{\mathrm{<figure-callout\; id="2"\; label="k\; j\; mod"\; filenames="C2008100560490023H2.png,C2008100560490024H1.png"\; state="\{\{state\}\}">k</figure-callout>}}^j\mathrm{mod}2,j=\mathrm{1,2},\&CenterDot;\&CenterDot;\&CenterDot;,N,$ Wherein N is an information frame length, is positive integer;

3. this n+1 information frame is passed through the LDPC code coder successively, obtain n+1 LDPC sign indicating number code word, wherein n+1 LDPC sign indicating number code word is redundant code word, in the present invention this redundant code word called after single-parity check (single parity check, SPC) sign indicating number, because the LDPC sign indicating number is a kind of linear block codes, so each bit of SPC sign indicating number code word is equivalent to obtain by n the bit even parity check of LDPC sign indicating number code word in the relevant position, is c if make j bit of SPC code word _SPC ^j, j bit of i code word is in n LDPC code word

Then have:

$c_{\mathrm{SPC}}^j+c_{\mathrm{LDP}{C}_1}^j+c_{{\mathrm{LDPC}}_2}^j+c_{\mathrm{LDP}{C}_3}^j+\&CenterDot;\&CenterDot;\&CenterDot;c_{{\mathrm{LDPC}}_{\mathrm{<figure-callout\; id="2"\; label="n\; j\; mod"\; filenames="C2008100560490023H2.png,C2008100560490024H1.png"\; state="\{\{state\}\}">n</figure-callout>}}}^j\mathrm{mod}2=0$

Code word pattern behind the coding as shown in Figure 4, as can be seen from the figure the LDPC code cascading scheme that proposes of the present invention is to be horizontal codes with the LDPC sign indicating number, the SPC sign indicating number is the LDPC-SPC product code scheme of vertical codes.As can be seen, SPC sign indicating number code word also is the LDPC sign indicating number code word that meets same H matrix constraint from cataloged procedure.If the code check of LDPC sign indicating number is R, the LDPC-SPC product code code check that obtains so is nR/ (n+1), and wherein n is a positive integer.

N can get 1 any one positive integer in just infinite in theory.But because the coding of LDPC-SPC product code is to add a SPC redundant code word on the basis of LDPC sign indicating number again, its Normalized Signal/Noise Ratio that brings loss is When the n value hour, the coding redundancy that brings is bigger, the snr loss is bigger, is unfavorable for improving the LDPC error performance; But when the n value is very big, though the coding redundancy that brings can ignore, also corresponding the increasing of number of the wrong code word that may occur in n LDPC code word, this makes the interpretation method complexity increase.The present invention draws by a large amount of simulation results, and the numerical value that n gets between 50 to 400 will be a reasonably selection, and the coding redundancy of this moment also can be ignored, and the complexity of interpretation method is also little.Certainly, also can increase or reduce the value of n according to actual needs.

Can know that by the analysis in the background technology when the error code flat bed of LDPC sign indicating number occurred, nearly all wrong code word all can be detected.Utilize this error detection characteristic of LDPC sign indicating number, the present invention provides two kinds of interpretation methods of LDPC-SPC product code: hard decision method and soft-decision alternative manner.

The Hard decision decoding method of LDPC-SPC product code comprises the steps:

1. initialization: every n LDPC sign indicating number code word and 1 SPC sign indicating number code word are deciphered by ldpc code decoder successively, even i LDPC code word

Enter ldpc code decoder and decipher, wherein i from 1 to n+1 the circulation, $C_{{\mathrm{LDPC}}_{n+1}}=C_{\mathrm{SPC}},$ Obtain the hard decision result of n+1 LDPC sign indicating number decoding;

According to ldpc code decoder can error detection characteristic, can count the multiple error pattern in n+1 the LDPC sign indicating number, specifically handle as follows:

If a) do not have the codeword decoding failure in n+1 LDPC sign indicating number code word, decoding finishes;

B) if surpass 1 codeword decoding failure in n+1 LDPC sign indicating number code word, decoding finishes;

C) if having only a codeword decoding failure in n+1 LDPC sign indicating number code word, can be divided into two kinds of situations again:

If i. Cuo Wu code word is the SPC sign indicating number, because the SPC sign indicating number is the redundancy check code word, thus can directly delete, n correct LDPC sign indicating number before the output, decoding finishes;

If ii. Cuo Wu code word is in preceding n the LDPC sign indicating number one, then enter step 3.

3. according to the even parity check relation of SPC code word, recover correct code word, concrete treatment step is as follows:

The LDPC code word of 3-1 deletion error;

3-2 carries out mould 2 Hes by bit with remaining n correct LDPC code word on column direction, the gained result is the correct code word that recovers;

Correct code word after 3-3 output recovers.

Wherein, the proof of step 3-2 is as follows:

Because $c_{\mathrm{SPC}}^j+c_{\mathrm{LDP}{C}_1}^j+c_{{\mathrm{LDPC}}_2}^j+c_{\mathrm{LDP}{C}_3}^j+\&CenterDot;\&CenterDot;\&CenterDot;+c_{\mathrm{LDP}{C}_{\mathrm{<figure-callout\; id="2"\; label="n\; j\; mod"\; filenames="C2008100560490023H2.png,C2008100560490024H1.png"\; state="\{\{state\}\}">n</figure-callout>}}}^j\mathrm{mod}2=0,$ J bit of wrong code word then $c_{\mathrm{Error}}^j=c_{\mathrm{SPC}}^j+c_{\mathrm{LDP}{C}_1}^j+c_{\mathrm{LDP}{C}_2}^j+c_{\mathrm{LDP}{C}_3}^j+\&CenterDot;\&CenterDot;\&CenterDot;+c_{\mathrm{Error}-1}^j+c_{\mathrm{Error}+1}^j+\&CenterDot;\&CenterDot;\&CenterDot;+c_{\mathrm{LDP}{C}_{\mathrm{<figure-callout\; id="2"\; label="n\; j\; mod"\; filenames="C2008100560490023H2.png,C2008100560490024H1.png"\; state="\{\{state\}\}">n</figure-callout>}}}^j\mathrm{mod}2,$ Promptly $c_{\mathrm{Error}}^j=\underset{\begin{array}{c}k=1\\ k\&NotEqual;\mathrm{Error}\end{array}}{\overset{n=1}{\mathrm{\&Sigma;}}}{c}_{\mathrm{LDP}{C}_k}^{\mathrm{<figure-callout\; id="2"\; label="j\; mod"\; filenames="C2008100560490023H2.png,C2008100560490024H1.png"\; state="\{\{state\}\}">j</figure-callout>}}\mathrm{mod}2.$ Must demonstrate,prove.

Be not difficult to find that LDPC-SPC product code Hard decision decoding method can only be corrected the situation that a wrong code word only appears in every n+1 LDPC code word, so its decoding performance is relevant with the error code word rate of LDPC sign indicating number by above-mentioned steps, can estimate to obtain by calculating.If the error probability of each LDPC sign indicating number code word is P before the cascade, after the cascade, have only wrong and code word of mistake only in n LDPC sign indicating number code word, and the SPC code word is when correct, the hard decision method just can be corrected a mistake, and this conditional probability is P ₁=nP (1-P) ⁿ, so the error code word rate P '=P-P of LDPC sign indicating number after the cascade ₁/ n=P-P (1-P) ⁿIf with (1-P) ⁿLaunch, just can obtain $P^{\&prime;}=P-P(1-\mathrm{nP}+C_n^2{\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="C2008100560490023H2.png,C2008100560490024H1.png"\; state="\{\{state\}\}">P</figure-callout>}}^2+\&CenterDot;\&CenterDot;\&CenterDot;).$ As n during much smaller than 1/P, the LDPC sign indicating number error code word rate P ' ≈ nP after the cascaded code decoding ²Because when the error code flat bed takes place, the error code word rate of LDPC sign indicating number and bit error rate are very little with the amplitude that Normalized Signal/Noise Ratio changes, and therefore can think that proportionally nP dwindles as the error code word rate P ' of the LDPC sign indicating number after the fixing later cascade of the n error code word rate P before the cascade.Because the performance of hard decision method is not subjected to the influence of the error bit number of each wrong code word, thus can think approx the bit error rate of product coding also be only carry out the LDPC coding bit error rate p proportionally nP dwindle.Utilize above-mentioned method of estimation can estimate simulation result more accurately, thereby save a large amount of simulation times.

The hard decision method is a kind of interpretation method with utmost point low complex degree, and the LDPC sign indicating number that can help the error code flat bed to occur reduces the error code flat bed.But when the wrong code word that occurs in n LDPC code word and 1 the SPC sign indicating number code word more than 2 or 2, the hard decision method can't be corrected it, this has also just limited its further improvement to the LDPC code performance, soft-decision interative encode method given below can be corrected above-mentioned error code pattern, thereby improves the error performance of LDPC sign indicating number to a greater extent.

According in the background technology to the analysis result of error code flat bed as can be known, when LDPC sign indicating number error code flat bed occurs, when occurring the wrong code word more than 2 or 2 in n LDPC code word and 1 the SPC sign indicating number code word, most error bit does not occur in same position, therefore wrong patterns as shown in Figure 5 can take place with very big probability, promptly in each relation of verification longitudinally of cascaded code, most check equations have only comprised an error bit.Though in theory, just can recover error bit by remaining correct bit and since ldpc code decoder can't the misjudgment code word in the position of correct bit, so the present invention provides a kind of soft-decision interative encode method.Utilize this method, each bit offers bit in other LDPC sign indicating number code word with the soft information of the confidence level of self as external information in the longitudinal check equation, and the external information that obtains offered ldpc code decoder under own, converge to correct code word smoothly to help decoder.

The concrete steps of the soft-decision interative encode method of LDPC-SPC product code are as follows:

1. initialization: every n LDPC sign indicating number code word and 1 SPC sign indicating number code word are deciphered by ldpc code decoder successively, obtained the hard decision result of n+1 LDPC sign indicating number decoding and the confidence information L of each bit _i ^j, L wherein _i ^jThe confidence information of showing j bit of i code word, i is from 1 to n+1, and j is from 1 to N, and N is the code length of LDPC sign indicating number, $L_{\mathrm{LDP}{C}_{n+1}}^j=L_{\mathrm{SPC}}^j,$ And establishing the Soft decision decoding maximum iteration time is T;

According to ldpc code decoder can error detection characteristic, can count the multiple error pattern in n+1 the LDPC sign indicating number, specifically handle as follows:

If a) do not have the codeword decoding failure in n+1 LDPC sign indicating number code word, decoding finishes;

B) if having only a codeword decoding failure in n+1 LDPC sign indicating number code word, can be divided into two kinds of situations again:

If i. Cuo Wu code word is the SPC sign indicating number, because the SPC sign indicating number is the redundancy check code word, thus can directly delete, n correct LDPC sign indicating number before the output, decoding finishes;

If ii. Cuo Wu code word is in preceding n the LDPC sign indicating number one, then carry out the method similar with Hard decision decoding:

The first, the LDPC code word of deletion error;

The second, remaining n correct LDPC code word carried out mould 2 Hes by bit on column direction, the gained result is the correct code word that recovers;

The 3rd, the correct code word after output recovers, decoding finishes;

C) if having the code word more than 2 or 2 to make a mistake in n+1 LDPC sign indicating number code word, then vertically decipher;

If i. reached Soft decision decoding maximum iteration time T, then decoding finishes.

If ii. do not reach Soft decision decoding maximum iteration time T, then forward step 3 to.

3. according to vertical even parity check relation, the external information of each bit of mistake in computation code word respectively: $e_{i_k}^j=2\mathrm{ar\; c}\tanh \left(\underset{t=1,t\&NotEqual;i_k}{\overset{n+1}{\mathrm{\&Pi;}}}\tanh \left(\frac{L_t^j}{2}\right)\right),$ i _kRepresent k wrong code word in n+1 the code word, k is a positive integer, and j represents k j bit in the wrong code word;

4. upgrade the confidence level of each bit of wrong code word $L_{i_k}^j=L_{i_k}^j+e_{i_k}^j,$ I wherein _kRepresent k wrong code word in n+1 the code word, k is a positive integer, and j represents k j bit in the wrong code word;

5. will upgrade the wrong code word of confidence level and send into ldpc code decoder successively, decipher, return step 2 then.

The soft-decision interative encode method flow chart of LDPC-SPC product code as shown in Figure 6.

Step 3 is core procedures of the soft-decision interative encode method of LDPC-SPC product code.Wherein, by longitudinal check relation, the computing formula of the external information of each bit of mistake code word $e_i^j=2\mathrm{ar\; c}\tanh \left(\underset{t=1,t\&NotEqual;i}{\overset{n+1}{\mathrm{\&Pi;}}}\tanh \left(\frac{L_t^j}{2}\right)\right)$ Proof as follows:

If n+1 the LDPC sign indicating number code word that comprises SPC sign indicating number code word be through after the ldpc code decoder, the confidence level of j bit in i LDPC code word is L _i ^j, the soft information of confidence level that order participates in n+1 bit of j the relation of verification longitudinally is respectively K ₁ ^j, L ₂ ^j..., L _N+1 ^j, wherein $L_i^j=\log \frac{p(c_i^j=0)}{p(c_i^j=1)},$ $p(c_i^j=0)$ J the probability that bit equals 0 representing i LDPC sign indicating number code word, $p(c_i^j=1)$ Represent the probability that this bit equals 1,1≤i≤n+1.

Because $c_{\mathrm{SPC}}^j+c_{\mathrm{LDP}{C}_1}^j+c_{{\mathrm{LDPC}}_2}^j+c_{\mathrm{LDP}{C}_3}^j+\&CenterDot;\&CenterDot;\&CenterDot;+c_{\mathrm{LDP}{C}_{\mathrm{<figure-callout\; id="2"\; label="n\; j\; mod"\; filenames="C2008100560490023H2.png,C2008100560490024H1.png"\; state="\{\{state\}\}">n</figure-callout>}}}^j\mathrm{mod}2=0,$ Make S=0 represent this even parity check relation, then the soft information of i bit in j the verification relation of decoding output is:

${\mathrm{Ls}}_i^j=\log \frac{p(c_i^j=0|S=0)}{p(c_i^j=1|S=0)}$

Wherein,

$p(c_i^j=0|S=0)=\frac{p(S=0|c_i^j=0)}{p(S=0)}\&CenterDot;p(c_i^j=0)$

$p(c_i^j=1|S=0)=\frac{p(S=0|c_i^j=1)}{p(S=0)}\&CenterDot;p(c_i^j=1)$

Therefore ${\mathrm{Ls}}_i^j=\log \frac{p(S=0|c_i^j=0)\&CenterDot;p(c_i^j=0)}{p(S=0|c_i^j=1)\&CenterDot;p(c_i^j=1)}=\log \frac{p(S=0|c_i^j=0)}{p(S=0|c_i^j=1)}+L_i^j;$

Again $p(S=0|c_i^j=0)=p(S^{\&prime;}=0),$ $p(S=0|c_i^j=1)=p(S^{\&prime;}=1)$ Wherein the verification of S ' expression all the other n bit except that i bit and, can get by above-mentioned abbreviation:

${\mathrm{Ls}}_i^j=\log \frac{p(S^{\&prime;}=0)}{p(S^{\&prime;}=1)}+L_i^j$

Will $c_i^j=0$ Be mapped as $u_i^j=1,$ $c_i^j=1$ Be mapped as $u_i^j=-1,$ Then

$p(S^{\&prime;}=0)=p(\underset{\begin{array}{c}k=1\\ k\&NotEqual;i\end{array}}{\overset{n+1}{\mathrm{\&Pi;}}}{u}_k^j=1),$ $p(S^{\&prime;}=1)=p(\underset{\begin{array}{c}k=1\\ k\&NotEqual;i\end{array}}{\overset{n+1}{\mathrm{\&Pi;}}}{u}_k^j=-1)$

Because all bits come from different LDPC sign indicating numbers, each bit is relatively independent, therefore has:

$p(\underset{\begin{array}{c}k=1\\ k\&NotEqual;i\end{array}}{\overset{n+1}{\mathrm{\&Pi;}}}{u}_k^j=1)=1+\underset{\begin{array}{c}k=1\\ k\&NotEqual;i\end{array}}{\overset{n+1}{\mathrm{\&Pi;}}}(p(u_k^j=1)-p(u_k^j=-1))$

$p(\underset{\begin{array}{c}k=1\\ k\&NotEqual;i\end{array}}{\overset{n+1}{\mathrm{\&Pi;}}}{u}_k^j=-1)=1-\underset{\begin{array}{c}k=1\\ k\&NotEqual;i\end{array}}{\overset{n+1}{\mathrm{\&Pi;}}}(p(u_k^j=1)-p(u_k^j=-1))$

Then ${\mathrm{Ls}}_i^j=\log \frac{p(S^{\&prime;}=0)}{p(S^{\&prime;}=1)}+L_i^j=\mathrm{<figure-callout\; id="1"\; label="log"\; filenames="C2008100560490024H1.png,C2008100560490025H1.png"\; state="\{\{state\}\}">log</figure-callout>}\frac{1+\underset{\begin{array}{c}k=1\\ k\&NotEqual;i\end{array}}{\overset{n+1}{\mathrm{\&Pi;}}}(p(u_k^j=1)-p(u_k^j=-1))}{1-\underset{\begin{array}{c}k=1\\ k\&NotEqual;i\end{array}}{\overset{n+1}{\mathrm{\&Pi;}}}(p(u_k^j=1)-p(u_k^j=-1))}+L_i^j$

So have ${\mathrm{Ls}}_i^j=2\mathrm{ar\; c}\tanh \left(\underset{t=1,t\&NotEqual;i}{\overset{n+1}{\mathrm{\&Pi;}}}\tanh \left(\frac{L_t^j}{2}\right)\right)+L_i^j,$ Promptly for each bit, the external information that the longitudinal check of SPC sign indicating number relation provides is $2\mathrm{ar\; c}\tanh \left(\underset{t=1,t\&NotEqual;i}{\overset{n+1}{\mathrm{\&Pi;}}}\tanh \left(\frac{L_t^j}{2}\right)\right),$ Formula must be demonstrate,proved.

The present invention gives improving one's methods of soft-decision interative encode method.The main purpose of interative encode method is exactly to make each bit constantly obtain the soft information of confidence level that can help it to adjudicate from the outside by iteration.In the soft-decision alternative manner that provides above, the bit of each LDPC sign indicating number code word all passes through the relation of SPC verification longitudinally, has obtained new external information from remaining LDPC sign indicating number code word, and then helps ldpc code decoder to converge to correct code word.Because in n+1 the LDPC sign indicating number code word, not all code word is decoding failure all.By the error detecing capability of LDPC sign indicating number, can know which code word has successfully converged to correct code word in n+1 the code word.Utilize this information that knows, can improve the soft-decision interative encode method.

The main thought of improving interpretation method is, utilize the error detecing capability of ldpc code decoder, the confidence level that is judged as each bit of successfully decoded LDPC sign indicating number code word is brought up to maximum,, accelerate the convergence of iterative decoding to improve the confidence level that each bit of wrong code word can access.If promptly i code word meets the check equations constraint, make the confidence level L of i j bit in the LDPC code word _i ^jSize be $\left|L_i^j\right|=\&infin;,$ Symbol is $\mathrm{sgn}\left(L_i^j\right)=\mathrm{sgn}\left(L_i^j\right),$ J=1 wherein, 2 ..., N, N are the code lengths of LDPC sign indicating number;

Be not difficult to find that LDPC-SPC sign indicating number soft-decision alternative manner is equivalent in the sum-product algorithm decoding that hockets of level and vertical direction.Therefore similar with sum-product algorithm, the verification of longitudinal direction concerns the external information computing formula $2\mathrm{arctanh}\left(\underset{t=1,t\&NotEqual;i}{\overset{n+1}{\mathrm{\&Pi;}}}\tanh \left(\frac{L_t^j}{2}\right)\right)$ Can carry out similarly simplifying with sum-product algorithm.The present invention has adopted offset-min-sum algorithm (the Chen Jinghu of better performances; R.M.Tanner; C.Jones, " Improved min-sum decoding algorithms for irregular LDPC codes; " InProc.ISIT ' 05.Massachusetts:MIT Press, pp.449-453,2005) method for simplifying of the vertical method of conduct, wherein the offset value is chosen as 0.2 according to a large amount of simulation results and in conjunction with experience, then the external information of longitudinal check relation Size be $\left|e_{i_k}^j\right|=\max (\underset{\begin{array}{c}t=1\\ t\&NotEqual;i\end{array}}{\overset{n+1}{\min }}\left(\right|L_t^j\left|\right)-\mathrm{0.2,0}),$ Symbol is $\mathrm{sgn}=\left(e_{i_k}^j\right)=\underset{t=1,t\&NotEqual;i}{\overset{n+1}{\mathrm{\&Pi;}}}\mathrm{sgn}\left(L_t^j\right),$ J=1 wherein, 2 ..., N, N are the code lengths of LDPC sign indicating number, i _kRepresent k wrong code word in n+1 the code word, L _i ^jIt is the confidence level of j bit in i the LDPC code word;

Because the absolute value of the bit confidence coefficient of each correct code word all is changed to infinity, therefore when calculating vertical soft information, the order of magnitude that only needs the bit confidence coefficient of relevant position in the comparison error code word, correct code word then only participate in the symbolic operation of the soft information of confidence level of relevant position bit.Than foregoing soft-decision alternative manner, improved soft-decision interative encode method complexity greatly reduces.Soft-decision interative encode method after the improvement is that the 3rd processing method that goes on foot is different with foregoing soft-decision alternative manner, and other steps are the same, and the concrete processing method of the step 3 in the method is as follows:

1) if. i code word meets the constraint of LDPC code check equation, then the confidence level L of j bit in i LDPC code word _i ^jSize be $L_i^j=\&infin;,$ Symbol is $\mathrm{sgn}\left(L_i^j\right)=\mathrm{sgn}\left(L_i^j\right),$ J=1 wherein, 2 ..., N, N are the code lengths of LDPC sign indicating number;

2). according to the longitudinal check relation, the external information of each bit of difference mistake in computation code word

Its size is $\left|e_{i_k}^j\right|=\max (\underset{\begin{array}{c}t=1\\ t\&NotEqual;i\end{array}}{\overset{n+1}{\min }}\left(\right|L_t^j\left|\right)-\mathrm{0.2,0}),$ Symbol is $\mathrm{sgn}\left(e_{i_k}^j\right)=\underset{t=1,t\&NotEqual;i}{\overset{n+1}{\mathrm{\&Pi;}}}\mathrm{sgn}\left(L_t^j\right),$ J=1 wherein, 2 ..., N, N are the code lengths of LDPC sign indicating number, i _kRepresent k wrong code word in n+1 the code word, L _i ^jIt is the confidence level of j bit in i the LDPC code word.

Another object of the present invention is to provide the decoder of the LDPC-SPC product code that adapts with said method.According to the coding structure of LDPC-SPC product code and in conjunction with said method, the present invention has provided Hard decision decoding device and soft-decision iterative decoder, be applicable to the Hard decision decoding method and the soft-decision interative encode method of LDPC-SPC product code respectively, introduced respectively below:

Hard decision decoding device structural representation as shown in Figure 7.The Hard decision decoding device comprises: LDPC sign indicating number decoding module, first memory module, mistake code word statistical module and hard decision recover four parts of module.Wherein, LDPC sign indicating number decoding module is used to realize the decoding of LDPC code word, and the hard decision information of output LDPC sign indicating number information bit is promptly deciphered successively to every n+1 LDPC sign indicating number code word, n+1 LDPC sign indicating number code word wherein is SPC sign indicating number code word, exports the hard decision information of n+1 LDPC sign indicating number information bit; First memory module is used to store the hard decision information of LDPC sign indicating number information bit, generally uses two-port RAM, and big I is fixed according to actual needs; Mistake code word statistical module is according to the wrong code word in n+1 LDPC sign indicating number of hard decision Information Statistics, usually form by a counter, initial value is 0, and by the flow direction of its decision LDPC codeword information position, the concrete flow direction as shown in Figure 7 is not the SPC sign indicating number if having only a codeword decoding failure and this code word in n+1 LDPC sign indicating number code word, then enters hard decision recovery module, otherwise the output information bit, decoding finishes; Hard decision recovers the LDPC code word of module deletion error, then remaining n correct LDPC code word is carried out mould 2 Hes by bit on column direction, recovers correct code word, the correct information bit after output recovers, and decoding finishes.

Hard decision recovers modular structure can be as shown in Figure 8, and it mainly is divided into modulo 2 adder module and two parts of second memory module.Wherein, modulo 2 adder is realized two not mould 2 He of the binary number of tape symbol position, and the information bit step-by-step that is used to calculate n LDPC code word except wrong code word is mould 2 Hes longitudinally, and export the individual correct information bit of this n simultaneously; Second memory module is a dual port RAM, and size is the size of LDPC codeword information bit, is used to store the interim result of modulo 2 adder, promptly with next frame do mould 2 and addend, and export final accumulation result, the correct information bit that promptly recovers.

Soft-decision iterative decoder structural representation as shown in Figure 9.The soft-decision iterative decoder comprises: LDPC sign indicating number decoding module, first memory module, mistake code word statistical module, SPC sign indicating number soft decoding module and hard decision recover five parts of module.Wherein, LDPC sign indicating number decoding module is used to realize the decoding of LDPC code word, the soft information and the hard decision information of the LDPC sign indicating number information bit of output, promptly every n+1 LDPC sign indicating number code word deciphered successively, n+1 LDPC sign indicating number code word wherein is SPC sign indicating number code word, export the soft information and the hard decision information of n+1 LDPC sign indicating number information bit, described soft information is the confidence level L of each bit _i ^j, wherein i is from 1 to n+1, and j is from 1 to N, and N is the code length of LDPC sign indicating number.First memory module is used to store the soft information and the hard decision information of LDPC sign indicating number information bit, generally uses dual port RAM, and big I is fixed according to actual needs.Wrong code word in n+1 LDPC sign indicating number of mistake code word statistical module counts, usually form by a counter, initial value is 0, and by the flow direction of its decision LDPC codeword information position, the concrete flow direction as shown in Figure 9, if having only a codeword decoding failure and this code word in n+1 the LDPC sign indicating number code word is not the SPC sign indicating number, then enters hard decision and recover module; If surpass a codeword decoding failure in n+1 the LDPC sign indicating number code word, then enter SPC sign indicating number soft decoding module; If do not have code word mistake or SPC sign indicating number decoding failure only, then export correct information bit.SPC sign indicating number soft decoding module, the external information that is used for the mistake in computation code word, using above-mentioned soft-decision interative encode method or its improves one's methods and deciphers, keep its soft information to occurring wrong code word in n+1 the LDPC sign indicating number, and correct code word only keeps its hard decision information, be sign bit, distinguish the external information of each bit of mistake in computation code word then $e_{i_k}^j=2\mathrm{arctanh}\left(\underset{t=1,t\&NotEqual;i_k}{\overset{n+1}{\mathrm{\&Pi;}}}\tanh \left(\frac{L_t^j}{2}\right)\right),$ I wherein _kRepresent k wrong code word in n+1 the code word, k is a positive integer, and j represents k j bit in the wrong code word, and the external information that obtains is deciphered once more as the prior information of LDPC sign indicating number decoding module, promptly upgrades the confidence level of wrong each bit of code word $L_{i_k}^j=L_{i_k}^j+e_{i_k}^j,$ Import LDPC sign indicating number decoding module again and carry out iterative decoding, until reaching maximum iteration time or all codeword detection are correct.Hard decision recovers module, in n LDPC sign indicating number, there is and only have a code word to make a mistake, and when should the mistake code word not being the SPC sign indicating number, recover this wrong code word with the method that is similar to Hard decision decoding, it is the LDPC code word of deletion error, then remaining n correct LDPC code word carried out mould 2 Hes by bit on column direction, the gained result is the correct code word that recovers, the correct information bit after output recovers.The concrete workflow of this decoder is:

Receiving terminal is at first deciphered successively to n+1 LDPC sign indicating number, if find not have the code word mistake, and then all bit-order outputs; If finding has and only have a code word to make a mistake, then n+1 LDPC sign indicating number is stored, and recovers wrong code word by hard decision; If finding the code word more than 2 or 2 makes a mistake, in n+1 LDPC sign indicating number the soft information that wrong code word keeps the output of LDPC sign indicating number decoding module appears so, correct code word only keeps hard decision information, it is sign bit, decipher by SPC sign indicating number soft decoding module, the external information that obtains is deciphered once more as the prior information of LDPC sign indicating number decoding module, until reaching maximum iteration time or all codeword detection are correct.

Identical with the Hard decision decoding device, hard decision in the soft-decision iterative decoder recovers module and mainly is made up of modulo 2 adder module and second memory module two parts, wherein modulo 2 adder module information bit step-by-step mould 2 Hes longitudinally that are used to calculate n LDPC code word except wrong code word are exported this n correct information bit simultaneously; Second memory module is used to store the interim result of modulo 2 adder, promptly with next frame do mould 2 and addend, and export final accumulation result, the correct information bit that promptly recovers.

Technique effect of the present invention is the following aspects:

First, LDPC-SPC product code design has been proposed, this scheme can overcome the error code flat bed of LDPC sign indicating number, and higher flexibility and bigger coding gain are arranged than BCH code Cascading Methods, this mainly is because BCH code need provide different code lengths and different error correcting capabilities for the LDPC sign indicating number of different code checks, increased the difficulty of code cascading scheme design and the complexity of coding/decoding system, and the LDPC-SPC product code need not be considered this problem; The coding redundancy that the while BCH code need be paid is bigger, and the coding redundancy of LDPC-SPC product code has only after being equivalent to the Normalized Signal/Noise Ratio loss $101g\left(\frac{n}{n+1}\right)\mathrm{dB},$ When n got higher value, coding redundancy can be ignored.

The second, provided the Hard decision decoding method of LDPC-SPC cascaded code, this is a kind of interpretation method with utmost point low complex degree, the LDPC sign indicating number that can help the error code flat bed to occur reduces the error code flat bed.

The 3rd, hard decision method to the LDPC-SPC cascaded code is analyzed, and provided the bit error rate estimation method of hard decision method, estimated result and simulation result more as shown in figure 10, as can be seen from the figure this estimation can meet simulation result accurately, thereby saves a large amount of simulation times.

The 4th, provided a kind of soft-decision interative encode method of LDPC-SPC cascaded code, and it is simplified, simulation result as shown in figure 13, as can be seen from Figure 13 under this soft-decision decoding method, compare with hard decision, the LDPC-SPC cascaded code can obtain more significantly coding gain, effectively reduces LDPC sign indicating number error code flat bed more.

So the LDPC-SPC product code that the present invention proposes can be obtained bigger coding gain with very little redundant cost, is a kind of channel coding schemes that is applicable to insensitive business of delaying time.

Description of drawings

Fig. 1 is the characteristic curve of error code of (8064,4032) LDPC sign indicating number;

Fig. 2 is (8064,4032) LDPC sign indicating number error code flat bed is respectively 200 wrong code words of being added up under 1.5dB (I) and the 1.6dB (II) at Normalized Signal/Noise Ratio an error bits numbers distribution map;

To be (8064,4032) LDPC sign indicating number be respectively error bit position statistical chart under 1.5dB and the 1.6dB at Normalized Signal/Noise Ratio to Fig. 3;

Fig. 4 is the code word pattern of LDPC-SPC product code of the present invention;

Fig. 5 is that the error bit position of LDPC-SPC product code of the present invention concerns schematic diagram;

Fig. 6 is the soft-decision interative encode method flow chart of LDPC-SPC product code of the present invention;

Fig. 7 is the structural representation of Hard decision decoding device of the present invention;

Fig. 8 is the structured flowchart that hard decision recovers module in the Hard decision decoding device of the embodiment of the invention 2;

Fig. 9 is the structural representation of soft-decision iterative decoder of the present invention;

The comparison diagram of the LDPC-SPC sign indicating number Hard decision decoding method error rate and estimated result when Figure 10 is n=100;

Figure 11 is a LDPC-SPC product code coding flow chart in the embodiment of the invention 1;

Figure 12 is the errored bit performance simulation of LDPC-SPC sign indicating number Hard decision decoding method figure as a result during n=200 in the embodiment of the invention 1;

Figure 13 is LDPC-SPC sign indicating number soft-decision interative encode method and LDPC-BCH sign indicating number errored bit property comparison simulation result figure during n=200 in the embodiment of the invention 1.

Embodiment

Below by embodiment, further specify the present invention in conjunction with the accompanying drawings, but the scope that does not limit the present invention in any way.Embodiment 1: construct the LDPC-SPC product code, and it is deciphered

The following specifically describes the method for the present invention of utilizing, is 8064 bits with length, and code check is that 1/2 LDPC sign indicating number has been constructed the LDPC-SPC product code, and to its process of deciphering, interpretation method comprises Hard decision decoding method and soft-decision interative encode method:

Present embodiment is got n=200, and promptly per 200 LDPC sign indicating numbers insert the SPC code word of a redundancy.

Encode flow chart as shown in figure 11, and concrete steps are as follows:

1. initialization: message bit stream framing, frame length are 4032 bits;

With 200 information frames successively by the SPC code coder, the SPC code coder with each information frame in the relevant position

Bit do mould 2 Hes, after n=200 information frame, export the result, i.e. information bit in the SPC sign indicating number, $c_{\mathrm{SPC}}^j=\underset{k=1}{\overset{n}{\mathrm{\&Sigma;}}}{c}_{\mathrm{LD}{\mathrm{PC}}_{\mathrm{<figure-callout\; id="2"\; label="k\; j\; mod"\; filenames="C2008100560490023H2.png,C2008100560490024H1.png"\; state="\{\{state\}\}">k</figure-callout>}}}^j\mathrm{mod}2,$ Wherein j from 1 to 4032;

3. 200 information frames and 1 SPC information frame are passed through the LDPC code coder successively, obtain n+1=201 LDPC sign indicating number code word, wherein n+1 LDPC sign indicating number code word is redundant SPC sign indicating number code word;

4. the code word behind the output encoder in order.

Decipher at receiving terminal, adopt Hard decision decoding as receiving terminal, the step of this method is as follows:

1. initialization: 200 LDPC sign indicating number code words and 1 SPC sign indicating number code word are deciphered by LDPC sign indicating number decoding module successively, even i LDPC code word

Enter LDPC sign indicating number decoding module and decipher, wherein i from 1 to 201, $C_{{\mathrm{LDPC}}_{201}}=C_{\mathrm{SPC}},$ Obtain the hard decision result of 201 LDPC sign indicating number decodings;

According to LDPC sign indicating number decoding module can error detection characteristic, can count the multiple error pattern in 201 LDPC sign indicating numbers, concrete treatment step is as follows:

If a) do not have the codeword decoding failure in 201 LDPC sign indicating number code words, decoding finishes;

B) if surpass 1 codeword decoding failure in 201 LDPC sign indicating number code words, decoding finishes;

C) if having only a codeword decoding failure in 201 LDPC sign indicating number code words, can be divided into two kinds of situations again:

If i. Cuo Wu code word is the SPC sign indicating number, because the SPC sign indicating number is the redundancy check code word, thus can directly delete, n correct LDPC sign indicating number before the output, decoding finishes;

If ii. Cuo Wu code word is the LDPC sign indicating number, then enter step 3.

3. according to the even parity check relation of SPC code word, recover correct code word, concrete treatment step is as follows:

The LDPC code word of 3-1 deletion error;

3-2 carries out mould 2 Hes by bit with remaining 200 correct LDPC code words on column direction, the gained result is the correct code word that recovers;

Correct code word after 3-3 output recovers.

If receiving terminal adopts the soft-decision iterative decoding, its flow chart adopts the improved soft-decision interative encode method described in the summary of the invention as shown in Figure 8 in the present embodiment, gets soft-decision greatest iteration decoding number of times T=5, and concrete steps are as follows:

1. initialization: 200 LDPC sign indicating number code words and 1 SPC sign indicating number code word are deciphered by LDPC sign indicating number decoding module successively, obtained the confidence information L of j bit of i code word _i ^j, wherein i from 1 to 201,

$L_{{\mathrm{LDPC}}_{201}}^j=L_{\mathrm{SPC}}^j;$

According to LDPC sign indicating number decoding module can error detection characteristic, the mistake of statistics code word:

If a) do not have the codeword decoding failure in 201 LDPC sign indicating number code words, decoding finishes, and exports correct LDPC sign indicating number;

B) if having only a codeword decoding failure in 201 LDPC sign indicating number code words, can be divided into two kinds of situations again:

If i. Cuo Wu code word is the SPC sign indicating number, because the SPC sign indicating number is the redundancy check code word,, export preceding 200 correct LDPC sign indicating numbers so can directly delete, decoding finishes;

If ii. Cuo Wu code word is the LDPC sign indicating number, then carry out the method similar with Hard decision decoding:

The first, the LDPC code word of deletion error;

The second, remaining 200 correct LDPC code words are carried out mould 2 Hes by bit on column direction, the gained result is the correct code word that recovers;

The 3rd, the correct code word after output recovers, decoding finishes;

C) if having the code word more than 2 or 2 to make a mistake in 201 LDPC sign indicating number code words, then vertically decipher;

If i. reached the Soft decision decoding maximum iteration time, promptly t＞T=5 then deciphers and finishes;

If ii. do not reach the Soft decision decoding maximum iteration time, promptly t≤T=5 then forwards step 3 to;

3. vertically decoding:, make the confidence level L of i each bit of LDPC code word if i code word meets the check equations constraint _i ^jSize be $\left|L_i^j\right|=\&infin;,$ Symbol is $\mathrm{sgn}\left(L_i^j\right)=\mathrm{sgn}\left(L_i^j\right),$ J=1 wherein, 2 ..., 4032.

4. concern according to longitudinal check, respectively the external information of each bit of mistake in computation code word

Its size is $\left|e_{i_k}^j\right|=\max (\underset{\begin{array}{c}t=1\\ t\&NotEqual;i\end{array}}{\overset{n+1}{\min }}\left(\right|L_t^j\left|\right)-\mathrm{0.2,0}),$ Symbol is $\mathrm{sgn}=\left(e_{i_k}^j\right)=\underset{t=1,t\&NotEqual;i}{\overset{n+1}{\mathrm{\&Pi;}}}\mathrm{sgn}\left(L_t^j\right),$ J=1 wherein, 2 ..., 4032, i _kRepresent k wrong code word in 201 code words, L _i ^jIt is the confidence level of j bit in i the LDPC code word;

5. upgrade the bit confidence coefficient of wrong code word $L_{i_k}^j=L_{i_k}^j+e_{i_k}^j,$ J=1 wherein, 2 ..., 4032, i _kRepresent 201 code words

In k wrong code word, k is a positive integer;

6. will upgrade confidence level wrong code word afterwards and send into ldpc code decoder successively, decipher, return step 2 then.

Present embodiment has carried out the error performance emulation of LDPC-SPC cascaded code under the BIAWGN channel to the LDPC-SPC product code of above-mentioned structure, wherein in order to accelerate simulation velocity, the interpretation method of LDPC sign indicating number has adopted and has been suitable for hard-wired offset-min-sum algorithm (Chen Jinghu; R.M.Tanner; C.Jones, " Improved min-sum decodingalgorithms for irregular LDPC codes; " In Proc.ISIT ' 05.Massachusetts:MIT Press, pp.449-453,2005), wherein the offset value is chosen as 0.2, and maximum iteration time is chosen as 37 times to adapt to the actual parameter of ldpc code decoder.When the LDPC of mistake sign indicating number number of codewords surpassed 50, emulation stopped.

Present embodiment has also been selected the GF (2 of error correcting capability t=10 ¹²) on BCH code carry out the emulation of errored bit property comparison.GF (2 ¹²) on minimal polynomial as follows.If the error correcting capability of BCH code is t, the product of t minimal polynomial before the generator polynomial of this BCH code just equals so.For example during t=2, the generator polynomial of BCH code is g (x)=g1 (x) g2 (x).Wherein, the selection of error correcting capability t=10 is based on the analysis of front to LDPC sign indicating number error code flat bed characteristics, draw when the error code flat bed occurring, error bit is counted major part all below 10 bits in the LDPC mistake code word, and the situation that surpasses 10 bits generally is no more than 10%.

Minimal polynomial

g ₁(x)＝1+x+x ⁴+x ⁶+x ¹²

g ₂(x)＝1+x+x ³+x ⁴+x ⁶+x ¹⁰+x ¹²

g ₃(x)＝1+x ²+x ³+x ⁶+x ¹²

g ₄(x)＝1+x+x ³+x ⁵+x ⁶+x ¹⁰+x ¹²

g ₅(x)＝1+x ²+x ⁴+x ⁵+x ⁶+x ⁷+x ⁸+x ⁹+x ¹²

g ₆(x)＝1+x+x ²+x ⁵+x ⁷+x ⁸+x ⁹+x ¹¹+x ¹²

g ₇(x)＝1+x+x ³+x ⁶+x ⁸+x ¹⁰+x ¹²

g ₈(x)＝1+x+x ²+x ³+x ⁴+x ⁵+x ⁹+x ¹⁰+x ¹²

g ₉(x)＝1+x+x ³+x ⁴+x ⁶+x ⁸+x ¹⁰+x ¹¹+x ¹²

g ₁₀(x)＝1+x+x ²+x ⁵+x ¹⁰+x ¹¹+x ¹²

Adopt simulation result that the Hard decision decoding method obtains as shown in figure 12, as can be seen from the figure the present embodiment LDPC-SPC product code of constructing adopts the Hard decision decoding method can reduce the error code flat bed of LDPC sign indicating number.

The simulation result that employing soft-decision interative encode method obtains as shown in figure 13, from the curve of Figure 13 as can be seen the present embodiment LDPC-SPC product code of constructing adopt the soft-decision alternative manner except the error code flat bed that can overcome the LDPC sign indicating number, can also obtain very significantly coding gain.When the error rate was 10-7, product code was compared the performance advantage that the LDPC sign indicating number has been obtained about 0.3dB, and was better than more than the LDPC-BCH cascaded code 0.4dB.

Embodiment 2: decoder

Present embodiment only provides the implementation of the Hard decision decoding device of the LDPC-SPC product code that embodiment 1 constructed.The realization block diagram of Hard decision decoding device as shown in Figure 7, it can be divided into LDPC decoding module, first memory module, mistake code word statistical module and hard decision recovers four parts of module.

Wherein, LDPC sign indicating number decoding module is used to realize the decoding of LDPC code word, do not do in the present embodiment and give unnecessary details, just be used to obtain the soft information and the hard decision information of LDPC sign indicating number information bit, the Hard decision decoding method only needs the hard decision information of LDPC sign indicating number information bit in the present embodiment; First memory module needs 201 two-port RAMs that size is 4032bits, is used to store the hard decision information of LDPC sign indicating number information bit; Mistake code word statistical module is made up of a counter, and initial value is 0, and maximum is 201, and determines the flow direction of LDPC codeword information position by its:

1. if do not have the codeword decoding failure in 201 LDPC sign indicating number code words, decoding finishes, and exports correct information bit;

2. if having the codeword decoding more than 2 or 2 to fail in 201 LDPC sign indicating number code words, decoding finishes;

3. if having only a codeword decoding failure in 201 LDPC sign indicating number code words, can be divided into two kinds of situations again:

If i. Cuo Wu code word is the SPC sign indicating number, because the SPC sign indicating number is the redundancy check code word, thus can directly delete, n correct LDPC sign indicating number before the output, decoding finishes;

If ii. Cuo Wu code word is the LDPC sign indicating number, then enters hard decision and recover module.

Hard decision recovers the modular structure block diagram as shown in Figure 8, and it mainly is divided into modulo 2 adder module and two parts of second memory module.Wherein, it be 4032bits step-by-step mould 2 and adder that modulo 2 adder needs size, is used to calculate 200 information bit step-by-steps mould 2 Hes longitudinally except wrong code word, and exports this 200 correct information bits simultaneously; It is the two-port RAM of 4032bits that second memory module needs size, is used to store the interim result of modulo 2 adder, promptly with next frame do mould 2 and addend, and after n=200, export final accumulation result, the correct information bit that promptly recovers.

Although disclose specific embodiments of the invention and accompanying drawing for the purpose of illustration, its purpose is to help to understand content of the present invention and implement according to this, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various replacements, variation and modification all are possible.Therefore, the present invention should not be limited to most preferred embodiment and the disclosed content of accompanying drawing.

Claims (10)

1. the coding method of a LDPC cascaded code may further comprise the steps:

1) makes the message bit stream framing;

2) every n information frame is done mould 2 Hes at the bit of relevant position, wherein n is a positive integer, obtains n+1 redundant frame, for $c_{n+1}^j=\underset{k=1}{\overset{n}{\mathrm{\&Sigma;}}}{c}_k^j\mathrm{mod}2,j=\mathrm{1,2},\&CenterDot;\&CenterDot;\&CenterDot;,N,$ Wherein N is an information frame length, is positive integer;

3) this n+1 information frame is obtained n+1 LDPC sign indicating number code word through LDPC sign indicating number coding successively, wherein n+1 LDPC sign indicating number code word is redundant code word, and with this redundant code word called after SPC sign indicating number, then resulting LDPC cascaded code is the LDPC-SPC product code, has:

$c_{\mathrm{SPC}}^j+c_{{\mathrm{LDPC}}_1}^j+c_{{\mathrm{LDPC}}_2}^j+c_{{\mathrm{LDPC}}_3}^j+\&CenterDot;\&CenterDot;\&CenterDot;+c_{{\mathrm{LDPC}}_n}^j\mathrm{mod}2=0$

C wherein _SPC ^jBe j bit of SPC code word,

J bit of n LDPC code word before being respectively.

2. coding method according to claim 1 is characterized in that: the value of described n is 50 to 400.

3. the interpretation method of the LDPC-SPC product code described in the claim 1 comprises the steps:

1) every n+1 LDPC sign indicating number code word carried out successively the decoding of LDPC sign indicating number, n+1 LDPC sign indicating number code word wherein is SPC sign indicating number code word, obtains the hard decision result of n+1 LDPC sign indicating number decoding;

2) count n+1 the error pattern in the LDPC sign indicating number, handle according to following situation a)～c):

If a) do not have the codeword decoding failure in n+1 LDPC sign indicating number code word, decoding finishes;

B) if surpass 1 codeword decoding failure in n+1 LDPC sign indicating number code word, decoding finishes;

C) if having only a codeword decoding failure in n+1 LDPC sign indicating number code word, then again in two kinds of situation:

If i. Cuo Wu code word is the SPC sign indicating number, directly delete this code word, n correct LDPC sign indicating number before the output, decoding finishes;

If ii. Cuo Wu code word is in preceding n the LDPC sign indicating number one, then enter step 3);

3) the LDPC code word of deletion error is carried out mould 2 Hes by bit with remaining n correct LDPC code word on column direction, the gained result is the correct code word that recovers, the correct code word after output recovers, and decoding finishes.

4. the interpretation method of the LDPC-SPC product code described in the claim 1 comprises the steps:

1) every n+1 LDPC sign indicating number code word carried out successively the decoding of LDPC sign indicating number, n+1 LDPC sign indicating number code word wherein is SPC sign indicating number code word, obtains the hard decision result of n+1 LDPC sign indicating number decoding and the confidence information L of each bit _i ^j,

Wherein i is from 1 to n+1, and j is from 1 to N, and N is the code length of LDPC sign indicating number, $L_{{\mathrm{LDPC}}_{n+1}}^j=L_{\mathrm{SPC}}^j;$ And set the maximum iteration time T of decoding;

2) count n+1 the error pattern in the LDPC sign indicating number, handle according to following situation a)～c):

If a) do not have the codeword decoding failure in n+1 LDPC sign indicating number code word, decoding finishes;

B) if having only a codeword decoding failure in n+1 LDPC sign indicating number code word, then again in two kinds of situation:

If i. Cuo Wu code word is the SPC sign indicating number, directly delete this code word, n correct LDPC sign indicating number before the output, decoding finishes;

If ii. Cuo Wu code word is in preceding n the LDPC sign indicating number one, then delete this mistake code word, then remaining n correct LDPC code word carried out mould 2 Hes by bit on column direction, the gained result is the correct code word that recovers, correct code word after output recovers, decoding finishes;

C) if having the code word more than 2 or 2 to make a mistake in n+1 LDPC sign indicating number code word, then change step 3) over to and carry out iteration and vertically decipher, decoding finishes when iterations reaches T;

3) external information of each bit of difference mistake in computation code word $e_{i_k}^j=2\mathrm{arctanh}\left(\underset{t=1,t\&NotEqual;i_k}{\overset{n+1}{\mathrm{\&Pi;}}}\tanh \left(\frac{L_t^j}{2}\right)\right),$ I wherein _kRepresent k wrong code word in n+1 the code word, k is a positive integer, and j represents k j bit in the wrong code word;

4) confidence level of wrong each bit of code word of renewal $L_{i_k}^j=L_{i_k}^j+e_{i_k}^j;$

5) the wrong code word that will upgrade confidence level is carried out the decoding of LDPC sign indicating number successively, returns step 2 then).

5. interpretation method according to claim 4 is characterized in that: the confidence level L that makes successfully decoded code word in the described step 3) _i ^jSize be $\left|L_i^j\right|=\&infin;,$ Symbol is $\mathrm{sgn}\left(L_i^j\right)=\mathrm{sgn}\left(L_i^j\right),$ J=1 wherein, 2 ..., N, the external information of then wrong each bit of code word

Size be $\left|e_{i_k}^j\right|=\max (\underset{t\&NotEqual;i}{\overset{n+1}{\underset{t=1}{\min }}}\left(\right|L_t^j\left|\right)-\mathrm{0.2,0}),$ Symbol is $\mathrm{sgn}\left(e_{i_k}^j\right)=\underset{t=1,t\&NotEqual;i}{\overset{n+1}{\mathrm{\&Pi;}}}\mathrm{sgn}\left(L_t^j\right),$ J=1 wherein, 2 ..., N.

6. a decoder is used for the LDPC-SPC product code described in the claim 1 is deciphered, and comprises that LDPC sign indicating number decoding module, first memory module, mistake code word statistical module and hard decision recover four parts of module, wherein:

LDPC sign indicating number decoding module is deciphered successively to every n+1 LDPC sign indicating number code word, and n+1 LDPC sign indicating number code word wherein is SPC sign indicating number code word, exports the hard decision information of n+1 LDPC sign indicating number information bit;

First memory module is used to store hard decision information;

Mistake code word statistical module is according to the wrong code word in n+1 LDPC sign indicating number of hard decision Information Statistics, and the flow direction of decision LDPC codeword information position: if having only a codeword decoding to fail in n+1 LDPC sign indicating number code word and this code word is not the SPC sign indicating number, then enter hard decision and recover module, otherwise the output information bit;

Hard decision recovers the LDPC code word of module deletion error, then remaining n correct LDPC code word is carried out mould 2 Hes by bit on column direction, and the gained result is the correct code word that recovers, the correct information bit after output recovers.

7. decoder according to claim 6 is characterized in that: described first memory module is a two-port RAM; Described wrong code word statistical module is that an initial value is 0 counter.

8. decoder according to claim 6, it is characterized in that: described hard decision recovers module and mainly is made up of modulo 2 adder module and second memory module two parts, wherein modulo 2 adder module information bit step-by-step mould 2 Hes longitudinally that are used to calculate n LDPC code word except wrong code word are exported this n correct information bit simultaneously; Second memory module is used to store the interim result of modulo 2 adder, promptly with next frame do mould 2 and addend, and export final accumulation result, the correct information bit that promptly recovers.

9. a decoder is used for the LDPC-SPC product code described in the claim 1 is deciphered, and comprises that LDPC sign indicating number decoding module, first memory module, mistake code word statistical module, SPC sign indicating number soft decoding module and hard decision recover five parts of module, wherein:

LDPC sign indicating number decoding module is deciphered successively to every n+1 LDPC sign indicating number code word, and n+1 LDPC sign indicating number code word wherein is SPC sign indicating number code word, exports the soft information and the hard decision information of n+1 LDPC sign indicating number information bit, and described soft information is the confidence level L of each bit _i ^j, wherein i is from 1 to n+1, and j is from 1 to N, and N is the code length of LDPC sign indicating number;

First memory module is used to store the soft information and the hard decision information of LDPC sign indicating number information bit;

Wrong code word in n+1 LDPC sign indicating number of mistake code word statistical module counts, and the flow direction of decision LDPC codeword information position: if having only a codeword decoding failure and this code word in n+1 LDPC sign indicating number code word is not the SPC sign indicating number, then enters hard decision recovery module; If surpass a codeword decoding failure in n+1 the LDPC sign indicating number code word, then enter SPC sign indicating number soft decoding module; If do not have code word mistake or SPC sign indicating number decoding failure only, then export correct information bit;

Hard decision recovers the LDPC code word of module deletion error, then remaining n correct LDPC code word is carried out mould 2 Hes by bit on column direction, and the gained result is the correct code word that recovers, the correct information bit after output recovers;

SPC sign indicating number soft decoding module keeps its soft information to occurring wrong code word in n+1 the LDPC sign indicating number, and correct code word only keeps its hard decision information, i.e. sign bit; Distinguish the external information of each bit of mistake in computation code word then $e_{i_k}^j=2\mathrm{ar\; c}\tanh \left(\underset{t=1,t\&NotEqual;i_k}{\overset{n+1}{\mathrm{\&Pi;}}}\tanh \left(\frac{L_t^j}{2}\right)\right),$ I wherein _kRepresent k wrong code word in n+1 the code word, k is a positive integer, and j represents k j bit in the wrong code word; The external information that obtains is deciphered once more as the prior information of LDPC sign indicating number decoding module, promptly upgrades the confidence level of wrong each bit of code word $L_{i_k}^j=L_{i_k}^j+e_{i_k}^j,$ Import LDPC sign indicating number decoding module again and carry out iterative decoding, until reaching maximum iteration time or all codeword detection are correct.

10. decoder according to claim 9, it is characterized in that: described hard decision recovers module and mainly is made up of modulo 2 adder module and second memory module two parts, wherein modulo 2 adder module information bit step-by-step mould 2 Hes longitudinally that are used to calculate n LDPC code word except wrong code word are exported this n correct information bit simultaneously; Second memory module is used to store the interim result of modulo 2 adder, promptly with next frame do mould 2 and addend, and export final accumulation result, the correct information bit that promptly recovers.

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