CN100581096C - Method and device for generating data stabilization effective index signal - Google Patents
Method and device for generating data stabilization effective index signal Download PDFInfo
- Publication number
- CN100581096C CN100581096C CN200710187313A CN200710187313A CN100581096C CN 100581096 C CN100581096 C CN 100581096C CN 200710187313 A CN200710187313 A CN 200710187313A CN 200710187313 A CN200710187313 A CN 200710187313A CN 100581096 C CN100581096 C CN 100581096C
- Authority
- CN
- China
- Prior art keywords
- signal
- data
- cycle
- clock signal
- index signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention discloses a method and a device to produce a stable and effective indication signal of data. The invention comprises the steps that: an indication signal of change edge is obtained after change edge detection is conducted by a first clock signal to receiving data, the cycle of the first clock signal is equal to one Nth of the minimum pulse width of the receiving data; wherein, N is a natural number greater than or equal to four; the cycle of the first clock signal is circularly counted based on a circulation cycle of N, and the count value is adjusted according to the indication signal of the change edge, thus a stable and effective indication signal of data corresponding to the stable stage of the receiving data is produced in line with the count value; the stable and effective indication signal of data is applied to various fields of data processing as an enable signal of subsequent conditioning circuit. The invention has the advantages that the stability of the subsequent conditioning circuit is greatly improved because the subsequent conditioning circuit works while the stable and effective indication signal of data is effective by judging whether the receiving data is stable according to the stable and effective indication signal of data.
Description
Technical field
The present invention relates to digital processing field, relate in particular to the method and the device that produce the data stabilization effective index signal.
Background technology
Phase-locked loop is used in receiver in communication, and its effect is to handle for the signal that receives, and from wherein extracting the phase information of certain clock.
In computer realm, USB comes transmission signals and power supply by a quadded cable, as shown in Figure 1.Wherein D+ and D-are the holding wires of a pair of differential mode, are used for transmission signals, and VBus and GND then provide the power supply of 5V, are used for to some power devices.USB provides two kinds of data transmission rates: the fast mode of a kind of 12Mb of being, another kind is the low-speed mode of 1.5Mb, these two kinds of patterns can be present in the USB system simultaneously, when D+, D-are used for carrying out transfer of data, data are carried out the difference non-return-to-zero coding, after clock is modulated, together be transferred to the communication opposite end with differential data, and guarantee that by the bit completion method clock can step-out, simultaneously, the packet header of each packet is a synchronization field, and the recipient can recover with the road clock by synchronization field.
In receiving data, it is phase-locked to use digital phase-locked loop that the data that receive are carried out, and therefrom recovers clock, by clock recovered the data that receive is carried out the digital circuit Synchronization Design.
Owing to be transferred to the process of receiving terminal from transmitting terminal at D+, D-differential data, exist send the receiving terminal frequency jitter, send receiving terminal drive the shake that shake, Multistage U SB extended line introduce, the influences such as shake that Multistage U SBHUB introduces, between the differential data bit width that receiving terminal is received and D+, the D-shake is arranged, the bit width maximum possible reaches ± 20ns at full speed, may reach ± 12ns between D+, the D-at full speed.
So, according to the Data Transmission Feature of USB, design digital phase-locked loop completely in receiving data, circuit will be very complicated; Simultaneously, clock by digital phase-locked loop generates as the clock of subsequent decoding circuit, may cause the front and rear part clock zone of subsequent conditioning circuit inconsistent, can give the checking and the realization of field programmable gate array, and the application-specific IC design back is made troubles.
Summary of the invention
Embodiment of the invention technical problem to be solved provides method and the device that produces the data stabilization effective index signal, produces the data stabilization effective index signal from the data that receive, realizes easy reliably, cost is low.
For solving the problems of the technologies described above, the embodiment of the invention provides a kind of method that produces the data stabilization effective index signal, comprises the steps:
Change along detecting receiving data according to first clock signal, obtain changing along index signal, the cycle of described first clock signal equals the 1/N of described reception data minimum pulse width, and N is the natural number more than or equal to 4;
The cycle of described first clock signal is carried out the cycle count that cycle period is N, and adjust count value along index signal according to described variation, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of described first clock signal is consistent, and k is a natural number;
Produce the data stabilization effective index signal according to described count value, described data stabilization effective index signal is corresponding to the stabilization sub stage of described reception data, describedly produces the data stabilization effective index signal according to described count value and comprises:
When the value of counting is when being the cycle count median of N the described cycle, postpone the useful signal of the cycle generation second clock signal of one first clock signal;
Effective when described second clock signal, and described variation is along index signal when invalid, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
A kind of device that produces the data stabilization effective index signal also is provided, comprises:
Variation is used for changing along detecting receiving data according to first clock signal along detecting unit, obtains changing along index signal, and the cycle of described first clock signal equals the 1/N of described reception data minimum pulse width, and N is the natural number more than or equal to 4;
Counting unit is used for the cycle of described first clock signal is carried out the cycle count that cycle period is N;
Adjustment unit, be used for adjusting along index signal the count value of described counting unit according to described variation, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of described first clock signal is consistent, and k is a natural number;
Data stabilization signal generation unit is used for producing the data stabilization effective index signal according to the count value of described counting unit, and described data stabilization effective index signal is corresponding to the stabilization sub stage of described reception data; Described data stabilization signal generation unit comprises:
The clock subelement is used for when the value of described counting unit counting is median, and the cycle that postpones one first clock signal produces the useful signal of second clock signal;
The first indication subelement is used for when described second clock signal effectively, and described variation is along index signal when invalid, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
Compared with prior art, the embodiment of the invention has the following advantages:
According to changing along index signal, the data stabilization effective index signal of generation can be applied to the field of various data processing.Can be used as the work enable signal of subsequent conditioning circuit, subsequent conditioning circuit judges according to this data stabilization effective index signal whether receive data stablizes, thereby work when the data stabilization effective index signal is effective, improved the stability of subsequent conditioning circuit operation, and subsequent conditioning circuit can also be continued to use first clock signal, make the front and rear part clock zone unanimity of subsequent conditioning circuit, improved the reasonability of timing topology; The data stabilization effective index signal that obtains directly can also be used as the clock of subsequent conditioning circuit, adopt the scheme of the embodiment of the invention, the phase-locked loop circuit that can substitute prior art produces the method for clock, recover being modulated to the clock that receives in the data, design easy, dependable performance, cost is low.
Description of drawings
Fig. 1 is the construction of cable schematic diagram of transmission USB in the prior art;
Fig. 2 is the schematic flow sheet that the present invention produces the method embodiment one of data stabilization effective index signal;
Fig. 3 is the flow chart that the present invention produces the method embodiment two of data stabilization effective index signal;
Fig. 4 is that the present invention produces the signal waveform schematic diagram among the method embodiment six of data stabilization effective index signal;
Fig. 5 is that the present invention produces the signal waveform schematic diagram among the method embodiment seven of data stabilization effective index signal;
Fig. 6 is that the present invention produces the signal waveform schematic diagram among the method embodiment eight of data stabilization effective index signal;
Fig. 7 is the structural representation that the present invention produces the device embodiment of data stabilization effective index signal.
Embodiment
For above-mentioned purpose, the feature and advantage that make the embodiment of the invention can become apparent more, the embodiment of the invention is described in further detail below in conjunction with the drawings and specific embodiments.
Embodiment one, and referring to Fig. 2, a kind of method that produces the data stabilization effective index signal comprises the steps:
201, change along detecting receiving data according to first clock signal, obtain changing along index signal, the cycle of first clock signal equals to receive the 1/N of data minimum pulse width, and N is the natural number more than or equal to 4;
202, the cycle of first clock signal is carried out the cycle count that cycle period is N, and according to changing along index signal adjustment count value, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of first clock signal is consistent, and k is a natural number;
203, according to count value, produce the data stabilization effective index signal, the data stabilization effective index signal is corresponding to the stabilization sub stage that receives data.
Adopt the labile state that changes along index signal recorder data; Cycle to first clock signal counts, the state of recorder data; According to count value, will receive the labile state removal of data again, thereby obtain data stabilization effective index signal corresponding to the stabilization sub stage that receives data.
According to changing along index signal, the data stabilization effective index signal of generation can be applied to the field of various data processing.Can be used as the work enable signal of subsequent conditioning circuit, subsequent conditioning circuit judges according to this data stabilization effective index signal whether receive data stablizes, thereby work when the data stabilization effective index signal is effective, improved the stability of subsequent conditioning circuit operation, and subsequent conditioning circuit can also be continued to use first clock signal, make the front and rear part clock zone unanimity of subsequent conditioning circuit, improved the reasonability of timing topology; The data stabilization effective index signal that obtains directly can also be used as the clock of subsequent conditioning circuit, adopt the scheme of present embodiment, the phase-locked loop circuit that can substitute prior art produces the method for clock, recover being modulated to the clock that receives in the data, design easy, dependable performance, cost is low.
Embodiment two, produce the method for data stabilization effective index signal, in the present embodiment, change along detecting receiving data with first clock signal, and the step that obtains changing along index signal can comprise:
Carry out obtaining synchrodata synchronously to receiving data with first clock signal;
In cycle with one first clock signal of synchrodata delay, obtain delayed data;
Whether equate with delayed data according to synchrodata, obtain changing along index signal.
Referring to Fig. 3, produce the method for data stabilization effective index signal, can comprise the steps:
301, carry out obtaining synchrodata synchronously to receiving data with first clock signal;
302, synchrodata is postponed the cycle of one first clock signal, obtain delayed data;
303, whether equate with delayed data according to synchrodata, obtain changing along index signal.
304, the cycle of first clock signal is carried out the cycle count that cycle period is N, and according to changing along index signal adjustment count value, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of first clock signal is consistent, and k is a natural number;
305,, produce the data stabilization effective index signal according to count value.
Change along detecting receiving data, obtain changing and have multiplely along the method for index signal, for example detect the saltus step situation of the voltage that receives data, when voltage jump takes place, judge to receive data and the variation edge occurred this moment; Perhaps adopt in the present embodiment, when the reception data before reception data after postponing and the delay were unequal, judgement changed effective along index signal, and the realization variation is along the principle of detection.
Variation is used for the labile state of recorder data along index signal, in actual applications because when receiving data generation saltus step, may be in a period of time less stables all, therefore, a plurality of variations can be set along index signal.In the present embodiment, can be provided with 2: first variation changes along index signal change along index signal change_pre and second.
When synchrodata and delayed data are unequal, produce first useful signal that changes along index signal change_pre; Otherwise obtain first invalid signals that changes along index signal change_pre;
First changes the cycle that postpones one first clock signal along index signal change_pre, obtains second and changes along index signal change.
Embodiment three, produce the method for data stabilization effective index signal, in the present embodiment, the cycle of first clock signal carried out the cycle count that cycle period is N, and can comprise according to changing the step of adjusting count value along index signal:
When resetting, begin counting from initial value;
When variation is invalid along index signal,, continue counting according to first clock cycle;
When changing along index signal when effective, adjust the value of next counting, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of first clock signal is consistent, k is a natural number.
The purpose that the cycle of first clock signal is counted is the state for the recorder data.When variation was invalid along index signal, expression received data and the edge do not occur changing, continued this moment to count.When variation was effective along index signal, expression received data and the variation edge occurred; If change along index signal and comprise that first variation changes along index signal along index signal and second, the variation of indication effectively is first variation along index signal and changes effective along index signal along index signal and/or second, in expression this moment or a period of time, receive data and the variation edge occurred.Owing to occur to change along being to receive data unsure state to have occurred, therefore the value by next one counting jumps to preset value this unsure state is noted.
The initial value of counting can set up on their own, for example, can count from zero, 0,1,2,,, N-1, perhaps counting from the beginning, 1,2,,, N, perhaps begin counting from N-1, N-1, N-2,,, 0 or the like.
Embodiment four, produce the method for data stabilization effective index signal, comprise the steps:
Carry out obtaining synchrodata synchronously to receiving data with first clock signal;
In cycle with one first clock signal of synchrodata delay, obtain delayed data;
Whether equate with delayed data according to synchrodata, obtain changing along index signal.
The second clock signal can also further be set, and the recorder data are stable status comparatively, and the data stabilization effective index signal is adjusted.
When the cycle of counting down to is the median of cycle count of N, the cycle that postpones one first clock signal produces the useful signal of second clock signal, the sequential counting if counting is started from scratch, perhaps begin sountdown from N-1, when then N is even number, median is N/2, and when N was odd number, median was (N-1)/2 or (N+1)/2.
Effective when the second clock signal, and change along index signal when invalid, the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
The cycle of first clock signal equals to receive the 1/N of data minimum pulse width, ordinary circumstance according to data variation, in the cycle of N first clock signal, counting is the moment of median, corresponding reception data are comparatively stable, therefore, in the present embodiment, by the second clock signal, with these comparatively stable status note, when the second clock signal is effective, be to receive comparatively stable status of data, the second clock signal is effective, and change along index signal also effectively the time, be to receive data should be in comparatively stable status, sudden change but occurred, cause the no longer stable situation of data that receives, therefore, effective when the second clock signal, and change along index signal when invalid, the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
Embodiment five, produce the method for data stabilization effective index signal, in the present embodiment, the stable signal of adjusting is set, the labile state of recorder data, this stable signal of adjusting produces according to changing along index signal and second clock signal, when the second clock signal effective, and change along index signal when effective, the cycle that postpones one first clock signal produces the stable useful signal of adjusting signal.Adopt the stable signal record reception data of adjusting to be in comparatively stable status, sudden change has but appearred, cause to receive the no longer stable situation of data, avoid the state of this sudden change, the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
Embodiment six, in the present embodiment, the method that produces the data stabilization effective index signal is applied in the usb bus, receive data and be the data of 12Mbps at full speed, subsequent conditioning circuit is the signaling interface engine circuit, and reception data minimum pulse width equals 6 times of cycle of first clock signal, adopt 3 bit counter that the first clock signal clk is carried out 0 to 5 counting, in the present embodiment, only adopt 1 variation along index signal, promptly first changes along index signal.
Referring to Fig. 4, comprise the steps:
Carry out obtaining synchrodata data synchronously to receiving data;
Synchrodata data is postponed the cycle of one first clock signal clk, obtain delayed data data_dly;
When synchrodata data and delayed data data_dly are unequal, produce first useful signal that changes along index signal change_pre, otherwise produce first invalid signals that changes along index signal change_pre;
Cycle to the first clock signal clk counts, and when resetting, counts from zero; When first variation is invalid along index signal change_pre, continue counting; When first variation was effective along index signal change_pre, the value of adjusting next counting was N/2, is 3, referring to the waveform of the data_cnt among Fig. 4;
When counting down to 3, the cycle that postpones one first clock signal clk produces the useful signal of second clock signal bit_dv_pre.
Bit_dv_pre is effective when the second clock signal, and first change along index signal change_pre when invalid, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
To produce the data stabilization effective index signal is applied in the usb bus, first clock signal can be used for clock as the signaling interface engine circuit, the data stabilization effective index signal is as the index signal of signaling interface engine circuit, and the signaling interface engine circuit is worked when the data stabilization effective index signal is effective.
In actual applications, can be according to the concrete condition that receives data, the minimum pulse width of reception data and the conditions such as multiple in the cycle of first clock signal are provided with a plurality of variations along index signal; Can also the second clock signal be set adjust according to the stable case that receives data with the stable data signal stabilization effective index signal of adjusting.
Embodiment seven, in the present embodiment, the method that produces the data stabilization effective index signal is applied in the usb bus, receiving data is the data of low speed 1.5Mbps, and subsequent conditioning circuit is the signaling interface engine circuit, receives 5 times of cycle that the data minimum pulse width equals first clock signal, adopt 3 bit counter the first clock signal clk to be carried out 0 to 4 counting, in the present embodiment, adopt 2 variations along index signal, i.e. first variation changes along index signal along index signal and second.
Referring to Fig. 5, comprise the steps:
Carry out obtaining synchrodata data synchronously to receiving data;
Synchrodata data is postponed the cycle of one first clock signal clk, obtain delayed data data_dly;
When synchrodata data and delayed data data_dly are unequal, produce first useful signal that changes along index signal change_pre, otherwise produce first invalid signals that changes along index signal change_pre;
First variation is postponed the cycle of one first clock signal clk along index signal change_pre, obtain second and change along index signal change.
Cycle to the first clock signal clk counts:
1, during system reset, timer is resetted, otherwise operation below carrying out;
2, when second variation is invalid along index signal change, continues counting, otherwise operate below carrying out;
3, when second variation was effective along index signal change, adjusting next count value was 3.
Referring to Fig. 5, in the present embodiment, the value of counting is to be that the value of the cycle count median correspondence of N is 2 or 3 in the cycle, can get when counting down to 3, and the cycle that postpones one first clock signal clk produces the useful signal of second clock signal bit_dv_pre.Also can get and count down at 2 o'clock, the cycle that postpones one first clock signal clk produces the useful signal of second clock signal bit_dv_pre, and the data stabilization effective index signal that finally obtains also corresponds to the stable state that receives data.
Bit_dv_pre is effective when the second clock signal, and first change along index signal change_pre and second and change along index signal change when all invalid, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
In Fig. 5, the useful signal that first useful signal corresponding first of second clock signal bit_dv_pre changes along index signal change_pre, this moment is for receiving the situation that data are undergone mutation, the stable signal bit_dv_add that adjusts is set writes down the situation of this sudden change, it is effective promptly to work as the second clock signal, and change along index signal when effective, the cycle that postpones one first clock signal produces the stable useful signal of adjusting signal bit_dv_add.
When stable adjustment signal was effective, the cycle that postpones one first clock signal produced the useful signal of data stabilization effective index signal.
Embodiment eight, in the present embodiment, the method that produces the data stabilization effective index signal is applied in the usb bus, receiving data is the data of low speed 1.5Mbps or full speed 12Mbps, subsequent conditioning circuit is the signaling interface engine circuit, receive 4 times of cycle that the data minimum pulse width equals first clock signal, adopt 2 bit counter the first clock signal clk to be carried out 0 to 3 counting, in the present embodiment, adopt 2 variations along index signal, i.e. first variation changes along index signal along index signal and second.
Referring to Fig. 6, comprise the steps:
Carry out obtaining synchrodata data synchronously to receiving data;
Synchrodata data is postponed the cycle of one first clock signal clk, obtain delayed data data_dly;
When synchrodata data and delayed data data_dly are unequal, produce first useful signal that changes along index signal change_pre, otherwise produce first invalid signals that changes along index signal change_pre;
First variation is postponed the cycle of one first clock signal clk along index signal change_pre, obtain second and change along index signal change.
Cycle to the first clock signal clk counts:
1, during system reset, timer is resetted, otherwise operation below carrying out;
2, when second variation is invalid along index signal change, continues counting, otherwise operate below carrying out;
3, when second variation was effective along index signal change, adjusting next count value was 1.
In the present embodiment, the value of counting is to be that the value of the cycle count median correspondence of N is 2 in the cycle, and therefore, when counting down to 2, the cycle that postpones one first clock signal clk produces the useful signal of second clock signal bit_dv_pre.
Bit_dv_pre is effective when the second clock signal, and first change along index signal change_pre and second and change along index signal change when all invalid, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
In Fig. 6, first and second of second clock signal bit_dv_pre, four, six, seven, eight useful signals that useful signal corresponding first changes along index signal change_pre, this moment is for receiving the situation that data are undergone mutation, the stable signal bit_dv_add that adjusts is set writes down the situation of this sudden change, it is effective promptly to work as the second clock signal, and change along index signal when effective, the cycle that postpones one first clock signal produces the stable useful signal of adjusting signal bit_dv_add.
When stable adjustment signal bit_dv_add was effective, the cycle that postpones one first clock signal produced the useful signal of data stabilization effective index signal.
Embodiment, a kind of device that produces the data stabilization effective index signal referring to Fig. 7, comprising:
Variation is used for changing along detecting receiving data according to first clock signal along detecting unit 701, obtains changing along index signal, and the cycle of first clock signal equals to receive the 1/N of data minimum pulse width, and N is the natural number more than or equal to 4;
Counting unit 702 is used for the cycle of first clock signal is carried out the cycle count that cycle period is N;
Data stabilization signal generation unit 704 is used for producing the data stabilization effective index signal according to the count value of counting unit, and the data stabilization effective index signal is corresponding to the stabilization sub stage that receives data.
Wherein, variation can comprise along detecting unit:
Subelement is used for carrying out obtaining synchrodata synchronously to receiving data with first clock signal synchronously;
Postpone subelement, be used for synchrodata is postponed the cycle of one first clock signal, obtain delayed data;
Whether judgment sub-unit is used for equating with delayed data according to synchrodata, obtains changing along index signal.
Judgment sub-unit can comprise:
The XOR unit is used for when synchrodata and delayed data are unequal, produces first useful signal that changes along index signal;
First delay cell is used for the cycle of first variation along one first clock signal of index signal delay obtained second and change along index signal.
Adjustment unit can comprise:
Detection sub-unit is used to detect reset signal and variation along index signal;
Control sub unit when being used to detect reset signal, makes counting unit begin counting from initial value; When detecting variation along the useful signal of index signal, adjust the value of the next one counting of counting unit, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of first clock signal is consistent, and k is a natural number.
Data stabilization signal generation unit can comprise:
The clock subelement is used for when the value of counting unit counting is median, and the cycle that postpones one first clock signal produces the useful signal of second clock signal;
The first indication subelement is used for when the second clock signal effectively, and changes along index signal when invalid, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
Data stabilization signal generation unit can also comprise:
The stabistor unit is used for when the second clock signal effectively, and changes along index signal when effective, and the cycle that postpones one first clock signal produces the stable useful signal of adjusting signal;
The second indication subelement is used for when stable adjustment signal is effective, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential hardware platform, can certainly all implement, but the former is better execution mode under a lot of situation by hardware.Based on such understanding, all or part of can the embodying that technical scheme of the present invention contributes to background technology with the form of software product, this computer software product can be stored in the storage medium, as ROM/RAM, magnetic disc, CD etc., comprise that some instructions are with so that a computer equipment (can be a personal computer, server, the perhaps network equipment etc.) carry out the described method of some part of each embodiment of the present invention or embodiment.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1, a kind of method that produces the data stabilization effective index signal is characterized in that, comprises the steps:
Change along detecting receiving data according to first clock signal, obtain changing along index signal, the cycle of described first clock signal equals the 1/N of described reception data minimum pulse width, and N is the natural number more than or equal to 4;
The cycle of described first clock signal is carried out the cycle count that cycle period is N, and adjust count value along index signal according to described variation, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of described first clock signal is consistent, and k is a natural number;
Produce the data stabilization effective index signal according to described count value, described data stabilization effective index signal is corresponding to the stabilization sub stage of described reception data, describedly produces the data stabilization effective index signal according to described count value and comprises:
When the value of counting is when being the cycle count median of N the described cycle, postpone the useful signal of the cycle generation second clock signal of one first clock signal;
Effective when described second clock signal, and described variation is along index signal when invalid, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
2, method according to claim 1 is characterized in that, describedly changes along detecting receiving data according to first clock signal, and the step that obtains changing along index signal comprises:
Carry out obtaining synchrodata synchronously to receiving data with described first clock signal;
In cycle with described first clock signal of described synchrodata delay, obtain delayed data;
Whether equate with described delayed data according to described synchrodata, obtain changing along index signal.
3, method according to claim 2 is characterized in that, describedly whether equates that with described delayed data the step that obtains changing along index signal comprises according to described synchrodata:
Described variation comprises that along index signal first variation changes along index signal along index signal and second;
When described synchrodata and described delayed data are unequal, produce first useful signal that changes along index signal;
Described first changes the cycle that postpones described first clock signal along index signal, obtains described second and changes along index signal.
According to one of them described method of claim 1 to 3, it is characterized in that 4, the described cycle to first clock signal is carried out the cycle count that cycle period is N, and the step of adjusting count value along index signal according to described variation comprises:
When resetting, begin counting from initial value;
When described variation is invalid along index signal,, continue counting according to described first clock cycle; When described variation is effective along index signal, adjust the value of next counting, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of described first clock signal is consistent, k is a natural number.
5, method according to claim 1 is characterized in that, the step of described generation data stabilization effective index signal also comprises:
Effective when described second clock signal, and described variation is along index signal when effective, and the cycle that postpones one first clock signal produces the stable useful signal of adjusting signal;
When described stable adjustment signal was effective, the cycle that postpones one first clock signal produced the useful signal of data stabilization effective index signal.
6, a kind of device that produces the data stabilization effective index signal is characterized in that, comprising:
Variation is used for changing along detecting receiving data according to first clock signal along detecting unit, obtains changing along index signal, and the cycle of described first clock signal equals the 1/N of described reception data minimum pulse width, and N is the natural number more than or equal to 4;
Counting unit is used for the cycle of described first clock signal is carried out the cycle count that cycle period is N;
Adjustment unit, be used for adjusting along index signal the count value of described counting unit according to described variation, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of described first clock signal is consistent, and k is a natural number;
Data stabilization signal generation unit is used for producing the data stabilization effective index signal according to the count value of described counting unit, and described data stabilization effective index signal is corresponding to the stabilization sub stage of described reception data; Described data stabilization signal generation unit comprises:
The clock subelement is used for when the value of described counting unit counting is median, and the cycle that postpones one first clock signal produces the useful signal of second clock signal;
The first indication subelement is used for when described second clock signal effectively, and described variation is along index signal when invalid, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
7, device according to claim 6 is characterized in that, described variation comprises along detecting unit:
Subelement is used for carrying out obtaining synchrodata synchronously to receiving data with described first clock signal synchronously;
Postpone subelement, be used for described synchrodata is postponed the cycle of described first clock signal, obtain delayed data;
Whether judgment sub-unit is used for equating with described delayed data according to described synchrodata, obtains changing along index signal.
8, device according to claim 7 is characterized in that, described judgment sub-unit comprises:
The XOR unit is used for when described synchrodata and described delayed data are unequal, produces first useful signal that changes along index signal;
First delay cell is used for the cycle of described first variation along described first clock signal of index signal delay obtained described second and change along index signal.
9, device according to claim 6 is characterized in that, described adjustment unit comprises:
Detection sub-unit is used to detect reset signal and variation along index signal;
Control sub unit when being used to detect reset signal, makes described counting unit begin counting from initial value; When detecting variation along the useful signal of index signal, adjust the value of the next one counting of described counting unit, making the width that receives is that the cycle count value of top n first clock signal of k * N data pulse correspondence doubly in the cycle of described first clock signal is consistent, and k is a natural number.
10, device according to claim 6 is characterized in that, described data stabilization signal generation unit also comprises:
The stabistor unit is used for when described second clock signal effectively, and described variation is along index signal when effective, and the cycle that postpones one first clock signal produces the stable useful signal of adjusting signal;
The second indication subelement is used for when described stable adjustment signal is effective, and the cycle that postpones one first clock signal produces the useful signal of data stabilization effective index signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710187313A CN100581096C (en) | 2007-11-19 | 2007-11-19 | Method and device for generating data stabilization effective index signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710187313A CN100581096C (en) | 2007-11-19 | 2007-11-19 | Method and device for generating data stabilization effective index signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101183926A CN101183926A (en) | 2008-05-21 |
| CN100581096C true CN100581096C (en) | 2010-01-13 |
Family
ID=39449025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710187313A Expired - Fee Related CN100581096C (en) | 2007-11-19 | 2007-11-19 | Method and device for generating data stabilization effective index signal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100581096C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106412527A (en) * | 2016-11-28 | 2017-02-15 | 深圳市载德光电技术开发有限公司 | Hot backup realization method and system with seamless switching of high definition audio and video |
| CN108241405B (en) * | 2016-12-26 | 2020-11-06 | 深圳比亚迪微电子有限公司 | On-chip clock circuit and method for generating on-chip clock signal |
| CN108347599B (en) * | 2018-01-26 | 2019-07-30 | 郑州云海信息技术有限公司 | A kind of vision signal Effective judgement method and system based on FPGA |
-
2007
- 2007-11-19 CN CN200710187313A patent/CN100581096C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101183926A (en) | 2008-05-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8064535B2 (en) | Three phase and polarity encoded serial interface | |
| CN103036670B (en) | A kind of clock recovery circuitry and parallel output circuit | |
| CN104954096B (en) | A kind of high-speed synchronous serial communication data transmission method of one master and multiple slaves | |
| US7729427B2 (en) | Pseudo-synchronous one wire bidirectional bus interface | |
| CN101432762B (en) | Signal transmission method, transmission/reception device, and communication system | |
| US8023602B2 (en) | Serial data communication apparatus and methods of using a single line | |
| CN101540158B (en) | Apparatus and method for transmitting and receiving data bit | |
| US9621332B2 (en) | Clock and data recovery for pulse based multi-wire link | |
| CN102340316A (en) | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer | |
| CN102819282B (en) | A kind of clock recovery circuit device and corresponding method | |
| CN108694148B (en) | Method and apparatus for Universal Serial Bus (USB) communication | |
| US11403251B2 (en) | Single-wire transmission method, chip and communication system | |
| CN100581096C (en) | Method and device for generating data stabilization effective index signal | |
| CN101257464B (en) | Circuit and method for differential signaling receiver | |
| CN105591645B (en) | A kind of multistage serial-parallel conversion circuit | |
| US20080195792A1 (en) | Universal Serial Bus Transmitter | |
| CN101964657B (en) | Low power consumption USB circuit | |
| WO2012038546A1 (en) | Multi-lane data transmission de-skew | |
| CN108614795A (en) | A kind of Digital Implementation method of USB data transmission | |
| CN201804327U (en) | Universal serial interface circuit | |
| WO2002103534A1 (en) | Multiphase encoded protocol and synchronization of buses | |
| KR102518285B1 (en) | PCIe INTERFACE AND INTERFACE SYSTEM | |
| CN111221760A (en) | Communication control method and device of I2C bus and storage medium | |
| CN107122325A (en) | Data transmission system and method based on novel universal universal serial bus | |
| CN220820664U (en) | I2C slave device detection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170927 Address after: Suining County, Jiangsu province 221200 Zhu Lou Cun, Xuzhou City Sui town No. 34 Patentee after: Liu Xiaochao Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: Huawei Technologies Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100113 Termination date: 20171119 |