CN100573933C - A kind of semiconductor chip - Google Patents
A kind of semiconductor chip Download PDFInfo
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- CN100573933C CN100573933C CNB2004100279552A CN200410027955A CN100573933C CN 100573933 C CN100573933 C CN 100573933C CN B2004100279552 A CNB2004100279552 A CN B2004100279552A CN 200410027955 A CN200410027955 A CN 200410027955A CN 100573933 C CN100573933 C CN 100573933C
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Abstract
A kind of semiconductor chip comprises territory, N polar region, territory, P polar region, and the electronics-hole-recombination zone between territory, N polar region and the territory, P polar region, it is characterized in that, each electrode is provided with two or more can be for the electrode area of lead-in wire.This semiconductor chip can be used for the preparation of high power LED chip and other semiconductor device, promptly be not limited to application, also can be used as high-power chip on the IC, laser diode (LD), ultraviolet detector, various other transistor devices etc. in the LED field.Owing to be provided with a plurality of electrode area, therefore overcome in the past because the improper problem that causes chip performance to descend or scrap of lead-in wire has improved the uniformity of chip reliability and operating current, and therefore improved luminous efficiency.
Description
Technical field
The present invention relates to semiconductor device, be specifically related to semiconductor large chip structure, more particularly, relate to a kind of semiconductor chip for preparing large-power light-emitting diodes, this chip has the N contact conductor position and the P contact conductor position of two or more quantity, and electrode is arranged to the luminous efficiency that can provide higher.
Background technology
Along with being " third generation " development of semiconductor of representative with gallium nitride and compound thereof, with gallium nitride and compound thereof be the blue green light of base and white light LEDs in Application for Field such as photoelectric display more and more widely, LED is more and more in various Application for Field such as white-light illuminating, traffic lights demonstration, the demonstration of three primary colors full color, IC.Along with the development of technology, there have been blue green light LED and white light LEDs to be used to show purposes and partial illumination purposes.But objectively need the more led chip of high brightness, to satisfy the requirement that illumination and others are used.The applicant in 2003 the application Chinese invention patent " a kind of semiconductor chip for preparing large-power light-emitting diodes " (number of patent application 03126942.7) and utility model " a kind of semiconductor chip for preparing large-power light-emitting diodes " (number of patent application 03247547.0) in, proposed such semiconductor chip structure for preparing large-power light-emitting diodes, these two patents by reference and incorporated herein.
The problem that prior art exists is, because at present particularly the price of short-wave band LED large chip is higher for the price of large chip, therefore be damaged in follow-up encapsulation process as fruit chip, if particularly the chip electrode position is damaged, so this damage will be unacceptable.Yet in the present at home encapsulation manufacturer, the overwhelming majority adopts the pattern of manual encapsulation.Facts have proved, in operations such as a crystalline substance, bonding wire, be easy to cause the damage at chip electrode position, as scuffing, not prison welding, burn out electrode etc., this can cause every performance index of chip to descend, and can cause chip rejection when serious, and this is unacceptable for manufacturer.In addition, because the volume of large chip is bigger, the current density when being easy to cause chip operation is inhomogeneous, thereby causes the electric current distribution in electronics-hole-recombination zone inhomogeneous, makes the luminous efficiency of entire chip be difficult to improve.
Therefore, in order to address the above problem, objectively need so a kind of chip, its P electrode area, each in the N electrode area all have two or more numbers, like this, if in encapsulation process, cause electrode area to damage, can use other redundant electrode area, and be unlikely to cause scrapping of chip.Simultaneously, the working current density that can also guarantee entire chip that is provided with of kind electrode is more evenly distributed, thereby improves luminosity, improves luminous efficiency.
Summary of the invention
The technical problem to be solved in the present invention is the semiconductor chip how a kind of new construction is provided, and each electrode all can provide two or more electrode area, and can improve the uniformity of chip operation electric current distribution.Wherein, the size of large-sized chip can be designed to about about 24 mils or about 40 mils, make that resultant LED is more powerful, but that the large chip size also can be made into is greater or lesser.Simultaneously, the electrode design of chip becomes to guarantee to also have other respective electrode position available when N electrode area or P electrode area are damaged; The layout of electrode can also make that electric current distribution is more even simultaneously, thereby improves luminous efficiency.
The above-mentioned technical problem of the present invention solves like this, construct a kind of semiconductor chip for preparing large-power light-emitting diodes, comprise territory, N polar region, territory, P polar region, and the electronics-hole-recombination zone between territory, N polar region and the territory, P polar region, it is characterized in that, be provided with many between territory, N polar region and territory, P polar region and run through or partly go deep into electronics-cavitation area be used to dispel the heat and the opening of bright dipping.Simultaneously, N electrode and P electrode are arranged to comprise two or more electrode area separately, and the layout of each electrode can be so that the working current density of chip distributes more even.
In according to semiconductor chip provided by the invention, comprise N electrode, P electrode, territory, N polar region, territory, P polar region, and the electronics-hole-recombination zone between territory, N polar region and the territory, P polar region, it is characterized in that, described N electrode is provided with two or more N electrode area, and described P electrode is provided with two or more P electrode area.
In according to chip provided by the invention, described N electrode (104) is arranged on the edge in territory, N polar region (101), the N electrode area (104A) of described N electrode (104) and (104B) be separately positioned on the two ends at described edge, described N electrode area (104A) and (104B) be the part of described N electrode (104).
In according to chip provided by the invention, circular, fan-shaped or arc of being shaped as of described N electrode area (104A), (104B) etc.
In according to chip provided by the invention, described P electrode (105) is arranged on another edge that with described N electrode area (104A) and (104B) limit of living in parallels on the territory, described P polar region (103), the described P electrode area (105A) of wherein said P electrode (105) and (105B) be separately positioned on the two ends at this edge.
In according to chip provided by the invention, described P electrode area (105A) and (105B) be shaped as circular, fan-shaped or arc etc.
In according to chip provided by the invention, also comprise substrate (100), territory, described N polar region (101), territory, P polar region (103) is in the same side of described substrate (100), wherein, territory, N polar region (101) is near substrate (100), territory, P polar region (103) is away from substrate (100), on territory, described N polar region (101), be provided with N electrode (104), be provided with P electrode (105) on territory, described P polar region (103), described opening is to open in territory, N polar region (101) and pass or partly be deep into electronics-cavitation area (102) and extend to territory, P polar region (103) or open in territory, P polar region (103) and pass or partly be deep into electronics-cavitation area (102) and extend to the opening (106) in territory, N polar region (101).
In according to chip provided by the invention, described substrate (100) is the material that is suitable for growing gallium nitride and compound thereof.
In according to chip provided by the invention, described substrate (100) adopts gallium nitride single crystal, monocrystalline silicon, sapphire (a kind of in α-Al2O3) monocrystalline, silicon dioxide monocrystalline, carborundum (SiC) monocrystalline, form described N electrode (104) in territory, N polar region (101) by photoetching, evaporation, ion sputtering method, equally, go up making described P electrode (105) in territory, P polar region (103) by photoetching, evaporation, ion sputtering method.
In according to chip provided by the invention, described substrate (100) adopts sapphire single-crystal, the manufacturing materials of described N electrode (104) and described P electrode (105) is gold, nickel, silver, copper or its alloy, and described electronics-hole-recombination zone (102) are the structures of single heterojunction, double heterojunction, single quantum well or Multiple Quantum Well.
In according to chip provided by the invention, described electronics-hole-recombination zone (202) are located between territory, N polar region (201), the territory, P polar region (203), are provided with N electrode (204) on territory, N polar region (201), are provided with P electrode (205) on territory, P polar region (203).
In according to chip provided by the invention, N electrode (204) is arranged in territory, whole N polar region (201), or P electrode (205) is arranged in territory, whole P polar region (203).
In according to chip provided by the invention, the manufacturing materials of described N electrode (104) and described P electrode (105) is gold, nickel, silver, copper or its alloy, and described electronics-hole-recombination zone (102) are the structures of single heterojunction, double heterojunction, single quantum well or Multiple Quantum Well.
Implement semiconductor chip provided by the invention, can be used for the preparation of high power LED chip and other semiconductor device, promptly be not limited to application, also can be used as high-power chip on the IC, laser diode (LD), ultraviolet detector, various other transistor devices etc. in the LED field.Because each electrode is provided with two or more electrode area respectively, therefore the semiconductor device of producing is more reliable, and operating current distributes more even, and luminosity and luminous efficiency are higher.In addition, because opening can be set, therefore can effectively overcome because the problem that heating is big, light emission rate is low and radiating effect is not good that chip size brings greatly, thereby make the performance of the semiconductor device of producing (for example LED) more stable, and also help further to improve luminosity and power.
Description of drawings
By hereinafter to the detailed introduction of embodiment and with reference to the accompanying drawings, the present invention may be better understood.For the sake of clarity, in each is provided with the figure of embodiment of opening, only shown an opening, but those skilled in the art will appreciate that one or above opening can be set as required.In the accompanying drawings:
Fig. 1 and Fig. 2 are respectively perspective view and the top views according to an embodiment of semiconductor chip of the present invention, have wherein schematically shown the chip unitary construction, comprise coplanar electrode, electrode area and opening, wherein include substrate in this large chip structure;
Fig. 3 and Fig. 4 are respectively according to the perspective view of another embodiment of semiconductor chip of the present invention and top view, have wherein schematically shown to comprise coplanar electrode, electrode area by the chip unitary construction, have wherein removed substrate in this large chip structure;
Fig. 5 and Fig. 6 are respectively according to the perspective view of another embodiment of semiconductor chip of the present invention and top view, have wherein schematically shown to comprise antarafacial electrode, electrode area by the chip unitary construction, have wherein removed substrate in this large chip structure;
Fig. 7 and Fig. 8 are respectively according to the perspective view of another embodiment of semiconductor chip of the present invention and top view, have schematically shown the chip unitary construction, comprise coplanar electrode, electrode area.Wherein include substrate in this large chip structure, but opening is not set.
Embodiment
Before further introducing the present invention, should be appreciated that owing to can make amendment, so the present invention is not limited to following specific embodiment specific embodiment.Should also be understood that because scope of the present invention only is defined by the following claims, therefore the term that is adopted just is used to introduce these specific embodiments, rather than restrictive.Except as otherwise noted, otherwise all used here technology and scientific words and those of ordinary skill in the art the same meaning generally understood.In addition, unless have to be noted that explanation is clearly arranged in the context in addition, included the implication of plural form interior such as " one ", " this " and " this " etc. otherwise reach the singulative that uses in the claims in this article.
According to semiconductor chip of the present invention, term " electrode part " refers to and specially is made into the position that is suitable for lead-in wire (bonding wire) in this electrode, and for example N electrode 104 comprises N electrode area 104A and 104B in Fig. 1.
According to semiconductor chip of the present invention, can be roughly rectangle, square, rhombus or other any suitable shape, the distribution from electrode is made can have coplanar electrode and antarafacial electrode.Wherein, when adopting the coplanar electrode, near substrate be territory, N polar region, be territory, P polar region away from the part of substrate, between territory, N polar region and territory, P polar region, be provided with electronics-hole-recombination zone, the N electrode is arranged on the territory, N polar region, the P electrode is arranged on the territory, P polar region.On N electrode and P electrode, be provided with two or more electrode area separately,, can make the operating current of chip distribute more even simultaneously to guarantee the reliability of lead-in wire (bonding wire).In addition, can also be provided with one or more opening that is opened on large chip surface (being territory, P polar region) on large chip, described opening passes electronics-hole-recombination zone and extends to territory, N polar region.On the other hand, adopt the antarafacial electrode, one side at large chip is provided with the N utmost point, and opposite one side is provided with the P utmost point, between the N utmost point and the P utmost point, be provided with electronics-hole-recombination zone,, on territory, N polar region and territory, P polar region, be provided with two or more electrode area separately, to guarantee the reliability of lead-in wire (bonding wire), can make the operating current of chip distribute more even simultaneously.On large chip, can be provided with one or more opening, this opening can be opened in territory, P polar region and pass or partly be deep into electronics-cavitation area and extend to territory, N polar region, and perhaps this opening can be opened in territory, N polar region and pass electronics-cavitation area and extend to territory, P polar region.Above-mentioned opening can be to be suitable for dispelling the heat and/or the Any shape or the size of bright dipping.Certainly, as required, also any opening can be set.
It needs to be noted that the large chip of indication can also be used for other purposes and for example make all kinds of IC power devices, ultraviolet detector, laser diode or the like herein except can being used as light-emitting diode (LED) purposes.
Introduce the present invention below with reference to the accompanying drawings, in these accompanying drawings, similarly parts are represented by similar label.
Embodiment one
Fig. 1 and Fig. 2 are respectively perspective view and the top views according to an embodiment of semiconductor chip of the present invention, have wherein schematically shown the chip unitary construction, comprise coplanar electrode, electrode area and opening, wherein include substrate in this large chip structure;
This chip comprises substrate 100, territory, N polar region 101, electronics-hole-recombination zone 102, territory, P polar region 103.On territory, N polar region 101, be provided with N electrode 104, on territory, P polar region 103, be provided with P electrode 105.Wherein, substrate 100 can be any suitable material that is suitable for growing gallium nitride and compound thereof, for example gallium nitride single crystal, monocrystalline silicon, sapphire (α-Al
2O
3) monocrystalline, silicon dioxide monocrystalline, carborundum (SiC) monocrystalline or the like, wherein sapphire single-crystal is preferred backing material.Can on territory, N polar region 101, make N electrode 104, for example photoetching, evaporation, ion sputtering or the like by any suitable method.N electrode 104 can be located at any position on the territory, N polar region 101, but preferably be arranged on the edge in territory, N polar region 101, wherein two of N electrode 104 N electrode area 104A and 104B are separately positioned on the two ends at this edge, N electrode area 104A and 104B are the parts of N electrode 104, its shape is preferably the Any shape that is suitable for going between, for example circular, semicircle, fan-shaped, arc or the like.。Certainly, the N electrode also can be to be suitable for equally distributed any other shape of current density, for example may extend into the optional position in the territory, N polar region 101.Equally, also can on territory, P polar region 103, make P electrode 105 by any suitable method such as photoetching, evaporation, ion sputtering etc.P electrode 105 can be located at any position on the territory, P polar region 103, but preferably be arranged on on the territory, P polar region 103 and another edge that N electrode area 104A and 104B limit of living in parallel, wherein two of P electrode 105 P electrode area 105A and 105B are separately positioned on the two ends at this edge, P electrode area 105A and 105B are the parts of P electrode 105, its shape is preferably the Any shape that is suitable for going between, for example circular, semicircle, fan-shaped or the like.The N electrode.Certainly, the P electrode also can be to be suitable for equally distributed any other shape of current density, perhaps extends to the whole zone in territory, P polar region.The material of making N electrode and P electrode can be gold, nickel, silver, copper etc., perhaps their alloy.
Should be pointed out that each electrode has only shown two electrode area in this embodiment, but each electrode also can be provided with plural electrode area as required.
Be provided with electronics-hole-recombination zone 102 between territory, N polar region 101 and territory, P polar region 103, being compounded in this zone of electronics and hole takes place.Electronics-hole-recombination zone 102 can be the structure of single heterojunction, double heterojunction, single quantum well or Multiple Quantum Well, but the structure of preferred Multiple Quantum Well.
Be provided with one or more openings 106 on territory, P polar region 103, these openings 106 open wide on territory, P polar region 103, and pass electronics-hole-recombination zone 102 and extend to territory, N polar region 101.But opening 106 does not run through territory, (perhaps preferably not running through) N polar region 101 and extends to substrate 100, the electric current distribution in territory, N polar region, back 101 of may causing switching on because territory 101, N polar region is separated by opening 106 for this is inhomogeneous, thereby may cause luminosity inhomogeneous.Opening can be to be suitable for dispelling the heat and/or any other shape and the size of bright dipping.Can form opening 106 by any suitable method, include but not limited to photoetching process, plasma etching, chemical etching, mechanical etching or the like.
Described opening 106 is not limited to the shape shown in the present embodiment, and can be to be convenient to dispel the heat and/or the Any shape and the structure of bright dipping, for example its section shape be triangle open mouth, one or more step-like opening, arc opening (, trapezoid-shaped openings and rectangular aperture or the like, also can be made into point-like, recess shape, polyline shaped, curve-like, helical form or the like, these openings can extend or not extend to the edge of large chip, but these openings preferably extend to the degree of depth that runs through electronics-hole-recombination zone, so that heat radiation and/or bright dipping greatly.The shape of these openings and be arranged on the inventor in 2003 the application Chinese invention patent " a kind of semiconductor chip for preparing large-power light-emitting diodes " (patent No. ZL03126942.7) in detailed introduction is arranged, this patent of invention is incorporated herein by reference.
Embodiment two
Fig. 3 and Fig. 4 are respectively according to the perspective view of another embodiment of semiconductor chip of the present invention and top view, have wherein schematically shown to comprise coplanar electrode, electrode area by the chip unitary construction, have wherein removed substrate in this large chip structure; Wherein the large chip structure comprises territory, N polar region 201, electronics-hole-recombination zone 202, territory, P polar region 203.On territory, N polar region 201, be provided with N electrode 204, be provided with P electrode 205 in territory, P polar region 203.Wherein N electrode 204 is provided with N electrode area 204A and 204B, and P electrode 205 is provided with P electrode area 205A and 205B.
Being provided with of the setting of the large chip structure of this embodiment and the large chip structure among the embodiment one is similar.But one of structure difference of the semiconductor chip among this embodiment and the above embodiment one is do not have substrate among this embodiment, facilitates large chip like this and dispels the heat better and/or bright dipping.Can remove substrate by any suitable mode, comprise chemical reduction, mechanical lapping attenuate or the like.
Embodiment three
Fig. 5 and Fig. 6 are respectively according to the perspective view of another embodiment of semiconductor chip of the present invention and top view, have wherein schematically shown to comprise coplanar electrode, electrode area by the chip unitary construction, have wherein removed substrate in this large chip structure; Wherein the large chip structure comprises territory, N polar region 301, electronics-hole-recombination zone 302, territory, P polar region 303.On territory, N polar region 301, be provided with N electrode 304, be provided with P electrode 305 in territory, P polar region 303.Wherein N electrode 304 is provided with N electrode area 304A and 304B, and P electrode 305 is provided with P electrode area 305A and 305B.
Being provided with of the setting of the large chip structure of this embodiment of N electrode and the large chip structure among the embodiment two is similar.But the electrode of this large chip structure is set to the antarafacial electrode, and promptly N electrode and P electrode are arranged on the opposite two sides.
In addition, because the particularity of this large chip structure, perhaps the convenience of realizing for technology can be arranged to other suitable shape with N electrode 304 and/or P electrode 305, for example N electrode 304 is arranged in territory, whole N polar region 301, perhaps P electrode 305 is arranged in territory, whole P polar region 303.
One or more openings 306 in territory, P polar region 303 can be opened on territory, P polar region 303, and pass electronics-hole-recombination zone 302 and extend to territory, N polar region 301.Perhaps, also these openings 306 can be arranged to be opened on territory, N polar region 301, and pass electronics-hole-recombination zone 302 and extend to territory, P polar region 303 from territory, N polar region 301.
Embodiment four
Fig. 7 and Fig. 8 are respectively according to the perspective view of another embodiment of semiconductor chip of the present invention and top view, have schematically shown the chip unitary construction, comprise coplanar electrode, electrode area.Wherein include substrate in this large chip structure, but opening is not set.
Wherein the large chip structure comprises territory, N polar region 401, electronics-hole-recombination zone 402, territory, P polar region 403.On territory, N polar region 401, be provided with N electrode 404, be provided with P electrode 405 in territory, P polar region 403.Wherein N electrode 404 is provided with N electrode area 404A and 404B, and P electrode 405 is provided with P electrode area 405A and 405B.
Being provided with of large chip structure among the setting of the large chip structure of this embodiment and the embodiment one is identical.Its difference is that this large chip structure is not provided with opening.
By above introduction the present invention having been carried out a ratio more comprehensively introduces.But it should be noted, though the present invention is suitable for use as the chip of light-emitting diode (LED), but the invention is not restricted to application, but can be as the high-power chip on the IC, laser diode (LD), ultraviolet detector, various other transistor devices etc. in the LED field.
It is therefore to be understood that the present invention except above these embodiment that carry out specific introduction, also can have practicing of other.Therefore, the embodiment that the present invention introduced should be regarded as illustrative and nonrestrictive, under the prerequisite that does not break away from the scope of the invention disclosed herein, also can adopt other setting, structure and application according to large chip of the present invention.Scope of the present invention is only limited by claims.
Claims (11)
1, a kind of semiconductor chip, comprise N electrode (104), P electrode (105), territory, N polar region (101), territory, P polar region (103), and the electronics-hole-recombination zone between territory, N polar region (101) and the territory, P polar region (103), described N electrode (104) has two or more N electrode area, and described P electrode (105) has two or more P electrode area (105A, 105B); It is characterized in that,
Described N electrode (104) is arranged on the whole piece edge in territory, N polar region (101), the N electrode area of described N electrode (104) (104A, 104B) is separately positioned on the two ends at a described whole piece edge, and described N electrode area (104A, 104B) is the part of described N electrode (104); And territory, whole P polar region is arranged to the P electrode; Perhaps,
Described P electrode (105) is arranged on on the territory, described P polar region (103) and another whole piece edge that described N electrode area (104A, 104B) limit of living in parallels, and the described P electrode area (105A, 105B) of wherein said P electrode (105) is separately positioned on the two ends at this whole piece edge; And territory, whole described N polar region is arranged to the N electrode;
Described chip also comprises substrate (100), territory, described N polar region (101), territory, P polar region (103) are in the same side of described substrate (100), wherein, territory, N polar region (101) is near substrate (100), territory, P polar region (103) is away from substrate (100), and is provided with and opens in territory, N polar region (101) and pass or partly be deep into electronics-cavitation area (102) and extend to territory, P polar region (103) or open in territory, P polar region (103) and pass or partly be deep into electronics-cavitation area (102) and extend to the opening (106) in territory, N polar region (101).
2, according to the described semiconductor chip of claim 1, it is characterized in that, the described N electrode area (104A, 104B) of described N electrode be shaped as circle.
According to the described semiconductor chip of claim 1, it is characterized in that 3, being shaped as of described N electrode area (104A, 104B) is fan-shaped.
4, according to the described semiconductor chip of claim 1, it is characterized in that, described N electrode area (104A, 104B) be shaped as arc.
5, according to the described semiconductor chip of claim 1, it is characterized in that, described P electrode area (105A, 105B) be shaped as circle.
According to the described semiconductor chip of claim 1, it is characterized in that 6, being shaped as of described P electrode area (105A, 105B) is fan-shaped.
7, according to the described semiconductor chip of claim 1, it is characterized in that, described P electrode area (105A, 105B) be shaped as arc.
According to the described semiconductor chip of claim 1, it is characterized in that 8, described substrate (100) is the material that is suitable for growing gallium nitride and compound thereof.
9, described according to Claim 8 semiconductor chip is characterized in that, described substrate (100) adopts gallium nitride single crystal, monocrystalline silicon, sapphire (α-Al
2O
3) a kind of in the monocrystalline, silicon dioxide monocrystalline, carborundum (SiC) monocrystalline, form described N electrode (104) in territory, N polar region (101) by photoetching, evaporation, ion sputtering method, equally, go up making described P electrode (105) in territory, P polar region (103) by photoetching, evaporation, ion sputtering method.
10, according to the described semiconductor chip of claim 1, it is characterized in that, described substrate (100) adopts sapphire single-crystal, the manufacturing materials of described N electrode (104) and described P electrode (105) is gold, nickel, silver, copper or its alloy, and described electronics-hole-recombination zone (102) are the structures of single heterojunction, double heterojunction, single quantum well or Multiple Quantum Well.
11, according to the described semiconductor chip of claim 1, it is characterized in that, the manufacturing materials of described N electrode (104) and described P electrode (105) is gold, nickel, silver, copper or its alloy, and described electronics-hole-recombination zone (102) are the structures of single heterojunction, double heterojunction, single quantum well or Multiple Quantum Well.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100279552A CN100573933C (en) | 2004-07-02 | 2004-07-02 | A kind of semiconductor chip |
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| CNB2004100279552A CN100573933C (en) | 2004-07-02 | 2004-07-02 | A kind of semiconductor chip |
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| CN1716647A CN1716647A (en) | 2006-01-04 |
| CN100573933C true CN100573933C (en) | 2009-12-23 |
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| CNB2004100279552A Expired - Fee Related CN100573933C (en) | 2004-07-02 | 2004-07-02 | A kind of semiconductor chip |
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