CN100570853C - Semiconductor element and manufacture method thereof - Google Patents
Semiconductor element and manufacture method thereof Download PDFInfo
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- CN100570853C CN100570853C CNB200710092048XA CN200710092048A CN100570853C CN 100570853 C CN100570853 C CN 100570853C CN B200710092048X A CNB200710092048X A CN B200710092048XA CN 200710092048 A CN200710092048 A CN 200710092048A CN 100570853 C CN100570853 C CN 100570853C
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Abstract
A kind of manufacture method of semiconductor element.At first, in substrate, form metal oxide semiconductor transistor, then, in substrate, form contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process, to increase the stress that contact hole etching stops layer.Afterwards, stop to form on the layer dielectric layer at contact hole etching.Continue it, carry out the second ultraviolet light curing process, to increase the stress of dielectric layer.Carry out CMP (Chemical Mechanical Polishing) process thereafter.Afterwards, on dielectric layer, form cap layer.
Description
Technical field
The present invention relates to a kind of integrated circuit component and manufacture method thereof, and be particularly related to a kind of semiconductor element and manufacture method thereof based on metal oxide semiconductor transistor.
Background technology
Along with the development of electronic equipment Development Technology such as communication, transistorized running speed heals and becomes quick.Yet because be subject to electronics and the hole translational speed in the silicon raceway groove, transistorized velocity interval also is restricted.
Utilizing the control of mechanical stress in the raceway groove (Mechanical-stress) to change electronics and the hole translational speed in raceway groove, is a kind of method that increases transistor running speed.
Known existing proposition utilizes the technology of materials such as germanium silicide (SiGe) extension as the main composition of transistor source/drain region.Its way is that the predetermined part that forms source/drain regions in the substrate is removed, and afterwards, utilizes and selects regional epitaxy technology, backfill germanium silicide.With the main composition of germanium silicide as source/drain regions, compare with the material behavior of silicon,, can bestow the raceway groove compression stress because germanium has bigger atomic volume, therefore form the mobility (Mobility) that source/drain regions can increase the hole with germanium silicide, and then the usefulness of lift elements.
Except utilizing the main composition of germanium silicide as source/drain regions, another kind of method then is after dielectric layer forms, and passes through O
2/ O
3/ N
2The surface of plasma treatment dielectric layer increases the stress of dielectric layer, to improve the firing current (I of element
On).Yet, can cause the electric charge accumulation with the plasma treatment dielectric layer, and influence the usefulness of element.Moreover, be the processing that belongs to the surface with the plasma treatment dielectric layer, it can't remove the inner aqueous vapor of dielectric layer, therefore, the problem when the dielectric layer window of can deriving is opened.In addition, can produce suspend (dangling) Si-O key or Si-N key, and make the increase degree of tensile stress of dielectric layer limited with the plasma treatment dielectric layer.
Summary of the invention
The invention provides a kind of semiconductor element and manufacture method thereof, to increase the stress of CESL and dielectric layer, what increase element opens the beginning electric current, promotes the ion yield value.
Another purpose of the present invention provides a kind of semiconductor element and manufacture method thereof, to reduce the aqueous vapor in the dielectric layer, the problem of avoiding contact hole to open.
The present invention proposes a kind of semiconductor element and manufacture method thereof, and it can avoid producing extra Si-O key or Si-N key, effectively increases the tensile stress of dielectric layer.
The present invention proposes a kind of manufacture method of semiconductor element, is applicable in the substrate that forms metal oxide semiconductor transistor.The step of the method comprises: form contact hole etching and stop layer in substrate; Carry out the first ultraviolet light curing process; Stop to form on the layer dielectric layer at contact hole etching; Carry out the second ultraviolet light curing process; On dielectric layer, form cap layer; And carry out CMP (Chemical Mechanical Polishing) process.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the temperature of carrying out first and second ultraviolet light curing process is that 150 degree Celsius are to 700 degree.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the time of carrying out first and second ultraviolet light curing process is 30 seconds to 60 minutes.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the pressure that carries out first and second ultraviolet light curing process is 3 milli torr to 500 torrs.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the ultraviolet light wavelength of carrying out first and second ultraviolet light curing process is 100nm to 400nm.
Described according to the embodiment of the invention, the step of manufacturing of above-mentioned semiconductor element is carried out according to following putting in order.At first, in substrate, form contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process.Then, stop to form on the layer dielectric layer at contact hole etching.Continue it, carry out the second ultraviolet light curing process.Carry out CMP (Chemical Mechanical Polishing) process thereafter.Afterwards, on dielectric layer, form cap layer.
Described according to the embodiment of the invention, the step of manufacturing of above-mentioned semiconductor element is carried out according to following putting in order.At first, in substrate, form contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process.Then, stop to form on the layer dielectric layer at contact hole etching.Continue it, on dielectric layer, form cap layer.Carry out second ultraviolet light curing process thereafter.Afterwards, carry out CMP (Chemical Mechanical Polishing) process.
Described according to the embodiment of the invention, the step of manufacturing of above-mentioned semiconductor element is carried out according to following putting in order.At first, in substrate, form contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process.Then, stop to form on the layer dielectric layer at contact hole etching.Afterwards, on dielectric layer, form cap layer.Continue it, carry out CMP (Chemical Mechanical Polishing) process.Then, carry out the second ultraviolet light curing process.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, also be included in contact hole etching and stop layer below formation resistance barrier oxide layer.
The present invention proposes a kind of manufacture method of semiconductor element, is applicable to that in the substrate that forms metal oxide semiconductor transistor, the step of the method comprises: form first contact hole etching and stop layer in substrate; Carry out the first ultraviolet light curing process; Stop to form on the layer second contact hole etching at first contact hole etching and stop layer; Stop to form on the layer dielectric layer at second contact hole etching; Carry out the second ultraviolet light curing process; On dielectric layer, form cap layer; And carry out CMP (Chemical Mechanical Polishing) process.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the temperature of carrying out first and second ultraviolet light curing process is respectively 150 degree Celsius to 700 degree.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the time of carrying out first and second ultraviolet light curing process was respectively 30 seconds to 60 minutes.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the pressure that carries out first and second ultraviolet light curing process is respectively 3 milli torr to 500 torrs.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the ultraviolet light wavelength of carrying out first and second ultraviolet light curing process is respectively 100nm to 400nm.
Described according to the embodiment of the invention, the step of manufacturing of above-mentioned semiconductor element is carried out according to following putting in order.At first, in substrate, form first contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process.Then, stop to form on the layer second contact hole etching at first contact hole etching and stop layer.Afterwards, stop to form on the layer dielectric layer at second contact hole etching.Continue it, carry out the second ultraviolet light curing process.Carry out CMP (Chemical Mechanical Polishing) process thereafter.Then, on dielectric layer, form cap layer.
Described according to the embodiment of the invention, the step of manufacturing of above-mentioned semiconductor element is carried out according to following putting in order.At first, in substrate, form first contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process.Then, stop to form on the layer second contact hole etching at first contact hole etching and stop layer.Continue it, stop to form on the layer dielectric layer at second contact hole etching.Then, on dielectric layer, form cap layer.Afterwards, carry out the second ultraviolet light curing process.Carry out CMP (Chemical Mechanical Polishing) process thereafter.
Described according to the embodiment of the invention, the step of manufacturing of above-mentioned semiconductor element is carried out according to following putting in order.At first, in substrate, form first contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process.Then, stop to form on the layer second contact hole etching at first contact hole etching and stop layer.Afterwards, stop to form on the layer dielectric layer at second contact hole etching.Continue it, on dielectric layer, form cap layer.Then, carry out CMP (Chemical Mechanical Polishing) process.Carry out second ultraviolet light curing process thereafter.
Described according to the embodiment of the invention, the manufacture method of above-mentioned semiconductor element also is included in contact hole etching and stops layer below formation resistance barrier oxide layer.
The present invention proposes a kind of manufacture method of semiconductor element, is applicable to that in the substrate that forms metal oxide semiconductor transistor, the step of the method comprises: form first contact hole etching and stop layer in substrate; Carry out the first ultraviolet light curing process; Stop to form on the layer second contact hole etching at first contact hole etching and stop layer; Carry out the second ultraviolet light curing process; Stop to form on the layer dielectric layer at second contact hole etching; Carry out the 3rd ultraviolet light curing process; On dielectric layer, form cap layer; And carry out CMP (Chemical Mechanical Polishing) process.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the temperature of carrying out first, second and the 3rd ultraviolet light curing process is respectively 150 degree Celsius to 700 degree.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the time of carrying out first, second and the 3rd ultraviolet light curing process was respectively 30 seconds to 60 minutes.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the pressure that carries out first, second and the 3rd ultraviolet light curing process is respectively 3 milli torr to 500 torrs.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned semiconductor element, the ultraviolet light wavelength of carrying out first, second and the 3rd ultraviolet light curing process is respectively 100nm to 400nm.
Described according to the embodiment of the invention, the step of manufacturing of above-mentioned semiconductor element is carried out according to following putting in order.At first, in substrate, form first contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process.Then, stop to form on the layer second contact hole etching at first contact hole etching and stop layer.Continue it, carry out the second ultraviolet light curing process.At second contact hole etching stop layer on to form dielectric layer thereafter.Then, carry out the 3rd ultraviolet light curing process.Carry out CMP (Chemical Mechanical Polishing) process thereafter.Afterwards, on dielectric layer, form cap layer.
Described according to the embodiment of the invention, the step of manufacturing of above-mentioned semiconductor element is carried out according to following putting in order.At first, in substrate, form first contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process.Then, stop to form on the layer second contact hole etching at first contact hole etching and stop layer.Continue it, carry out the second ultraviolet light curing process.Afterwards, stop to form on the layer dielectric layer at second contact hole etching.Then, on dielectric layer, form cap layer.Carry out three ultraviolet light curing process thereafter.Afterwards, carry out CMP (Chemical Mechanical Polishing) process.
Described according to the embodiment of the invention, the step of manufacturing of above-mentioned semiconductor element is carried out according to following putting in order.At first, in substrate, form first contact hole etching and stop layer.Then, carry out the first ultraviolet light curing process.Then, stop to form on the layer second contact hole etching at first contact hole etching and stop layer.Continue it, carry out the second ultraviolet light curing process.At second contact hole etching stop layer on to form dielectric layer thereafter.Then, on dielectric layer, form cap layer.Carry out CMP (Chemical Mechanical Polishing) process thereafter.Afterwards, carry out the 3rd ultraviolet light curing process.
Described according to the embodiment of the invention, the manufacture method of above-mentioned semiconductor element also is included in contact hole etching and stops layer below formation resistance barrier oxide layer.
The present invention proposes a kind of semiconductor element, comprises that metal oxide semiconductor transistor, contact hole etching stop layer, dielectric layer and cap layer, and wherein metal oxide semiconductor transistor is positioned in the substrate; Contact hole etching stops layer and covers metal oxide semiconductor transistor; Dielectric layer covers contact hole etching and stops layer, and the stress of dielectric layer is 0.1 to 1.0GPa; Cap layer covers dielectric layer.
Described according to the embodiment of the invention, in the above-mentioned semiconductor element, the material that contact hole etching stops layer comprising silicon nitride.
Described according to the embodiment of the invention, above-mentioned semiconductor element also comprises resistance barrier oxide layer, is positioned at contact hole etching and stops layer below.
Described according to the embodiment of the invention, in the above-mentioned semiconductor element, the material of resistance barrier oxide layer comprises silica.
The present invention can increase the stress of CESL and dielectric layer, and what increase element opens the beginning electric current, promotes the ion yield value.And, can reduce the aqueous vapor in the dielectric layer, the problem of avoiding contact hole to open.In addition, the present invention can avoid producing the extra key that suspends, and effectively increases the tensile stress of dielectric layer.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the structural representation according to a kind of semiconductor element that the embodiment of the invention illustrated.
Fig. 2 is the manufacturing flow chart according to a kind of semiconductor element that one embodiment of the invention illustrated.
Fig. 3 is the manufacturing flow chart according to a kind of semiconductor element that another embodiment of the present invention illustrated.
Fig. 4 is the manufacturing flow chart according to a kind of semiconductor element that yet another embodiment of the invention illustrated.
Fig. 5 is the manufacturing flow chart according to a kind of semiconductor element that yet another embodiment of the invention illustrated.
Fig. 6 is the manufacturing flow chart according to a kind of semiconductor element that further embodiment of this invention illustrated.
Fig. 7 is the manufacturing flow chart according to a kind of semiconductor element that further embodiment of this invention illustrated.
Fig. 8 is the manufacturing flow chart according to a kind of semiconductor element that further embodiment of this invention illustrated.
Fig. 9 is the manufacturing flow chart according to a kind of semiconductor element that further embodiment of this invention illustrated.
Figure 10 is the manufacturing flow chart according to a kind of semiconductor element that further embodiment of this invention illustrated.
Description of reference numerals
100: substrate 102: metal oxide semiconductor transistor
104: grid structure 106: source/drain regions
108: gate dielectric layer 110: grid conductive layer
110a: doped polysilicon layer 110b, 180: metal silicide layer
112: clearance wall 114: the source/drain extension area
116: source/drain contact zone 120,120a, 120b: contact hole etching stops layer
125: resistance barrier oxide layer 130: dielectric layer
140: cap layer 202～1018: step
Embodiment
Fig. 1 is the structural representation according to a kind of semiconductor element that the embodiment of the invention illustrated.
Please refer to Fig. 1, in substrate 100, formed metal oxide semiconductor transistor 102.Metal oxide semiconductor transistor 102 can be that n type channel metal oxide semiconductor transistor also can be a p type channel metal oxide semiconductor transistor.Metal oxide semiconductor transistor 102 comprises grid structure 104 and source/drain regions 106.Grid structure 104 comprises gate dielectric layer 108, grid conductive layer 110 and clearance wall 112.The material of gate dielectric layer 108 for example is a silica.The material of grid conductive layer 110 comprises the material based on silicon, for example is one of them of doped silicon, undoped silicon, doped polycrystalline silicon or undoped polycrystalline silicon.When the material of grid electricity layer 110 was doped silicon or doped polycrystalline silicon, the doping in silicon or polysilicon can be that the N type mixes, and also can be that the P type mixes.In one embodiment, grid conductive layer 110 is made of doped polysilicon layer 110a and metal silicide layer 110b.The material of metal silicide layer 110b for example is the silicide of refractory metal, and refractory metal for example is one of them of alloy of nickel, cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium, zirconium, platinum and those metals.The material of clearance wall 112 can be silica or silicon nitride, and it can be individual layer clearance wall or double gap wall.
Source/drain regions 106 comprises source/drain extension area 114 and source/drain contact zone 116.Have doping of n type or the doping of p type in the source/drain regions 106.It for example is phosphorus or arsenic that the n type mixes.It for example is boron or BF that the p type mixes
2 +Source/drain contact zone 116 is to be main material with the semi-conducting material.The formation method of semi-conducting material can form in substrate 100 after the groove, again via selecting regional epitaxy technique (selective area epitaxy growth process), epitaxial growth epitaxial growth of semiconductor material layer in groove.Doping in the source/drain contact zone 116 doping of can when selecting regional epitaxy technique, coming personally, or after selecting regional epitaxy technique, again via ion implantation technology to form.In one embodiment, metal oxide semiconductor transistor 102 is a n type channel metal oxide semiconductor transistor, the n type that is doped to of source/drain contact zone 116, and the semi-conducting material of source/drain contact zone 116 for example is a carbon doped silicon.In one embodiment, metal oxide semiconductor transistor 102 is a p type channel metal oxide semiconductor transistor, the p type that is doped to of source/drain contact zone 116, and the semi-conducting material of source/drain contact zone 116 for example is a sige alloy.
In one embodiment, also comprise metal silicide layer 180 on the source/drain contact zone 116.The material of metal silicide layer 180 for example is the silicide of refractory metal, and refractory metal for example is one of them of alloy of nickel, cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium, zirconium, platinum and those metals.The formation method of metal silicide layer 180 is cambium layer metal level (not illustrating) in substrate 100 earlier, and its material for example is one of them of alloy of refractory metal such as nickel, cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium, zirconium, platinum and those metals.The formation method of metal level comprises methods such as evaporation, sputter, plating, chemical vapor deposition (CVD) or physical vaporous deposition.Then, so that reacting, metal level forms metal silicide layer via annealing process again.
Metal oxide semiconductor transistor 102 be touched the window etching stopping layer (Contact etch stoplayer, CESL) 120, dielectric layer 130 and cap layer 140 cover.The material that contact hole etching stops layer 120 for example is a silicon nitride, its formation method for example is a high-temperature ammonolysis thing technology, or mode such as plasma enhanced chemical vapor deposition method (PECVD), sub-atmospheric pressure chemical vapour deposition technique (Sub-Atmospheric CVD), Low Pressure Chemical Vapor Deposition.In one embodiment, contact hole etching stops layer 120 can form required thickness with single deposition step, and thickness for example is to be about 100 dust to 2000 dusts.Afterwards, handle via the ultraviolet light curing process again, to increase its stress.For n type channel metal oxide semiconductor transistor, contact hole etching stops layer 120 and carries out the ultraviolet light curing process and handle and can increase its tensile stress.In another embodiment, contact hole etching stops layer 120 can form required thickness with two deposition steps, Chen Ji thickness for example is that thickness is about 50 dust to 1000 dusts each time, and carries out the ultraviolet light curing process and handle between two deposition steps, to increase its stress.In another embodiment, contact hole etching stops layer 120 can form required thickness with two deposition steps, Chen Ji thickness for example is about 50 for dust to 1000 dust each time, stop layer 120a and 120b and form contact hole etching, wherein carry out the ultraviolet light curing process after each deposition step respectively and handle, to increase its stress.The ultraviolet wavelength of ultraviolet light curing process is about 100nm to 400nm; Temperature is about 150 degree Celsius to 700 degree; The time of carrying out is about 30 seconds to 60 minutes; Pressure is about 3 milli torr to 500 torrs.
The material of dielectric layer 130 for example is silica, non-impurity-doped silex glass (USG), boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), or advanced low-k materials.Advanced low-k materials is that dielectric constant is lower than 4 material layer, for example is fluorine doped silicon glass (FSG); Silicon sesquichloride such as hydrogen silicon sesquichloride (Hydrogen silsesquioxane, HSQ), methyl silicon sesquichloride (Methylsilsesquioxane, MSQ) with mix organosilane polymer (Hybrido-organo siloxanepolymer, HOSP); Aromatic hydrocarbons (Aromatic hydrocarbon) is as SiLK; Parylene (Parylene); Fluorinated polymer (Fluoro-Polymer) is as PFCB, CYTOP, Teflon; Polyarylether (Poly (arylethers)) is as PAE-2, FLARE; Porous polymer (Porous polymer) is as XLK, Nanofoam, Aerogel; Coral etc.The method of the formation of dielectric layer 130 can using plasma enhanced chemical vapor deposition method, sub-atmospheric pressure chemical vapour deposition technique, high depth-width ratio ditch are filled out technology (High Aspect Ratio Process, HARP), mode such as high-temperature oxide (HTO) technology, low-pressure chemical vapor deposition process.The thickness of dielectric layer 130 for example is to be about 500 dust to 5000 dusts.
Can carry out the ultraviolet light curing process after dielectric layer 130 forms again and handle, can reduce the key that suspends (for example Si-OH key), increasing its stress, and reduce the problem that contact hole is opened.For n type channel metal oxide semiconductor transistor, dielectric layer 130 carries out the processing of ultraviolet light curing process can increase its tensile stress, and its stress can reach 0.1 to 1.0GPa, so firing current (On-current, the I of energy lift elements
On).The ultraviolet wavelength that dielectric layer 130 carries out the ultraviolet light curing process is about 100nm to 400nm; Temperature is about 150 degree Celsius to 700 degree; The time of carrying out is about 30 seconds to 60 minutes; Pressure is about 3 milli torr to 500 torrs.
The material of cap layer 140 for example is silicon nitride, carborundum, silicon oxide carbide (SiCO), carbonitride of silicium (SiCN), carbon silicon oxynitride (SiCNO), silicon oxynitride etc., and the method for formation for example is that high temperature nitrogen (oxygen) is changed modes such as thing technology, plasma enhanced chemical vapor deposition method, sub-atmospheric pressure chemical vapour deposition technique, low-pressure chemical vapor deposition process.
In one embodiment, carry out the ultraviolet light curing process of dielectric layer 130 immediately after forming dielectric layer 130, afterwards, carry out CMP (Chemical Mechanical Polishing) process again, the planarization that makes afterwards, is just carried out the depositing operation of cap layer 140 again.
In another embodiment, after forming dielectric layer 130 and cap layer 140, carry out the ultraviolet light curing process of dielectric layer 130 earlier, afterwards, carry out CMP (Chemical Mechanical Polishing) process again, so that dielectric layer 130 and cap layer 140 planarizations.
In another embodiment, then be after dielectric layer 130 and cap layer 140 form, carry out CMP (Chemical Mechanical Polishing) process earlier, so that dielectric layer 130 and cap layer 140 planarizations are beneficial to follow-up photoetching process.Afterwards, carry out the ultraviolet light curing process of dielectric layer 130.
In one embodiment, comprise not only on the metal oxide semiconductor transistor 102 that contact hole etching stops layer 120, dielectric layer 130 and cap layer 140, also comprise contact hole etching stop layer 120 under resistance barrier oxide layer 125, its material for example is a silica, the formation method for example is the high temperature thermal oxidation metallization processes, or plasma enhanced chemical vapor deposition method, sub-atmospheric pressure chemical vapour deposition technique, low-pressure chemical vapor deposition process etc.
The dielectric layer 130 of the embodiment of the invention is handled through the ultraviolet light curing process, and its stress can reach 0.1 to 1.0GPa.
Moreover in the mode on plasma treatment dielectric layer surface, the present invention can avoid the electric charge accumulation before or after carry out CMP (Chemical Mechanical Polishing) process at dielectric layer, and therefore, the usefulness of element is preferable.Moreover, be the processing that belongs to the surface with the plasma treatment dielectric layer, the present invention then is the slaking that belongs to comprehensive with the ultraviolet light slaking, and its surface of containing whole dielectric layer is with inner, and therefore, its effect that reduces aqueous vapor is preferable.In addition, can produce extra Si-O key or Si-N key, and the tensile stress of its rete is descended with the plasma treatment dielectric layer.
According to the above, the manufacture method of semiconductor element of the present invention can following several embodiment illustrates.
Fig. 2 to Figure 10 illustrates the flow chart of the manufacture method of semiconductor element of the present invention respectively.
Please refer to Fig. 2, step 202 at first, forms metal oxide semiconductor transistor in substrate.Then, step 204 forms contact hole etching and stops layer in substrate.Then, step 206 is carried out the first ultraviolet light curing process, increases so that contact hole etching stops the stress of layer.Continue it, step 208 stops to form on the layer dielectric layer at contact hole etching.Afterwards, step 210 is carried out the second ultraviolet light curing process, so that the stress of dielectric layer increases.Thereafter, step 212 is carried out CMP (Chemical Mechanical Polishing) process, so that dielectric layer flatening.Afterwards, step 214 forms cap layer on dielectric layer.
Please refer to Fig. 3, step 302 at first, forms metal oxide semiconductor transistor in substrate.Then, step 304 forms contact hole etching and stops layer in substrate.Then, step 306 is carried out the first ultraviolet light curing process, increases so that contact hole etching stops the stress of layer.Continue it, step 308 stops to form on the layer dielectric layer at contact hole etching.Afterwards, step 310 forms cap layer on dielectric layer.Then, step 312 is carried out the second ultraviolet light curing process, so that the stress of dielectric layer increases.Thereafter, step 314 is carried out CMP (Chemical Mechanical Polishing) process, so that dielectric layer and cap layer planarization.
Please refer to Fig. 4, step 402 at first, forms metal oxide semiconductor transistor in substrate.Then, step 404 forms contact hole etching and stops layer in substrate.Then, step 406 is carried out the first ultraviolet light curing process, increases so that contact hole etching stops the stress of layer.Continue it, step 408 stops to form on the layer dielectric layer at contact hole etching.Afterwards, step 410 forms cap layer on dielectric layer.Then, step 412 is carried out CMP (Chemical Mechanical Polishing) process, so that dielectric layer and cap layer planarization.Afterwards, step 414 is carried out the second ultraviolet light curing process, so that the stress of dielectric layer increases.
Please refer to Fig. 5, step 502 at first, forms metal oxide semiconductor transistor in substrate.Step 504 forms first contact hole etching and stops layer in substrate.Then, step 506 is carried out the first ultraviolet light curing process, increases so that first contact hole etching stops the stress of layer.Continue it, step 508 stops to form on the layer second contact hole etching at first contact hole etching and stops layer.Afterwards, step 510 stops to form on the layer dielectric layer at second contact hole etching.Then, step 512 is carried out the second ultraviolet light curing process, increases so that the dielectric layer and second contact hole etching stop the stress of layer.Thereafter, step 514 is carried out CMP (Chemical Mechanical Polishing) process, so that dielectric layer flatening.Thereafter, step 516 forms cap layer on dielectric layer.
Please refer to Fig. 6, step 602 at first, forms metal oxide semiconductor transistor in substrate.Step 604 forms first contact hole etching and stops layer in substrate.Then, step 606 is carried out the first ultraviolet light curing process.Continue it, step 608 stops to form on the layer second contact hole etching at first contact hole etching and stops layer.Afterwards, step 610 stops to form on the layer dielectric layer at second contact hole etching.Then, step 612 forms cap layer on dielectric layer.Afterwards, step 614 is carried out the second ultraviolet light curing process, increases so that the dielectric layer and second contact hole etching stop the stress of layer.Thereafter, step 616 is carried out CMP (Chemical Mechanical Polishing) process, so that dielectric layer and cap layer planarization.
Please refer to Fig. 7, step 702 at first, forms metal oxide semiconductor transistor in substrate.Step 704 forms first contact hole etching and stops layer in substrate.Then, step 706 is carried out the first ultraviolet light curing process, increases so that first contact hole etching stops the stress of layer.Continue it, step 708 stops to form on the layer second contact hole etching at first contact hole etching and stops layer.Afterwards, step 710 stops to form on the layer dielectric layer at second contact hole etching.Then, step 712 forms cap layer on dielectric layer.Afterwards, step 714 is carried out CMP (Chemical Mechanical Polishing) process, so that dielectric layer and cap layer planarization.Thereafter, step 716 is carried out the second ultraviolet light curing process, increases so that the dielectric layer and second contact hole etching stop the stress of layer.
Please refer to Fig. 8, step 802 at first, forms metal oxide semiconductor transistor in substrate.Then, step 804 forms first contact hole etching and stops layer in substrate.Then, step 806 is carried out the first ultraviolet light curing process, increases so that first contact hole etching stops the stress of layer.Continue it, step 808 stops to form on the layer second contact hole etching at first contact hole etching and stops layer.Afterwards, step 810 is carried out the second ultraviolet light curing process, increases so that second contact hole etching stops the stress of layer.Thereafter, step 812 stops to form on the layer dielectric layer at second contact hole etching.Then, step 814 is carried out the 3rd ultraviolet light curing process, so that the stress of dielectric layer increases.Continue it, step 816 is carried out CMP (Chemical Mechanical Polishing) process, so that dielectric layer flatening.Thereafter, step 818 forms cap layer on dielectric layer.
Please refer to Fig. 9, step 902 at first, forms metal oxide semiconductor transistor in substrate.Then, step 904 forms first contact hole etching and stops layer in substrate.Then, step 906 is carried out the first ultraviolet light curing process, increases so that first contact hole etching stops the stress of layer.Continue it, step 908 stops to form on the layer second contact hole etching at first contact hole etching and stops layer.Afterwards, step 910 is carried out the second ultraviolet light curing process, increases so that second contact hole etching stops the stress of layer.Thereafter, step 912 stops to form on the layer dielectric layer at second contact hole etching.Then, step 914 forms cap layer on dielectric layer.Afterwards, step 916 is carried out the 3rd ultraviolet light curing process, so that the stress of dielectric layer increases.Continue it, step 918 is carried out CMP (Chemical Mechanical Polishing) process, so that dielectric layer and cap layer planarization.
Please refer to Figure 10, step 1002 at first, forms metal oxide semiconductor transistor in substrate.Then, step 1004 forms first contact hole etching and stops layer in substrate.Then, step, 1006, carry out the first ultraviolet light curing process, so that stopping the stress of layer, first contact hole etching increases.Continue it, step 1008 stops to form on the layer second contact hole etching at first contact hole etching and stops layer.Afterwards, step 1010 is carried out the second ultraviolet light curing process, increases so that second contact hole etching stops the stress of layer.Thereafter, step 1012 stops to form on the layer dielectric layer at second contact hole etching.Then, step, 1014, on dielectric layer, form cap layer.Afterwards, step 1016 is carried out CMP (Chemical Mechanical Polishing) process, so that dielectric layer and cap layer planarization.Thereafter, step 1018 is carried out the 3rd ultraviolet light curing process, so that the stress of dielectric layer increases.
Experiment
Example 1
With elevated temperature heat technology deposited silicon nitride layer 550nm in substrate, afterwards, with the non-impurity-doped silex glass of chemical vapour deposition technique deposition 2000nm.Thereafter, carried out the ultraviolet light curing process 20 minutes, wherein ultraviolet wavelength is 100～400nm, and temperature is 400 degree Celsius; Pressure is 200 torrs.
Example 2
Behind deposited silicon nitride layer 550nm in the substrate, carried out the ultraviolet light curing process 5 minutes with elevated temperature heat technology.Afterwards, deposit the non-impurity-doped silex glass of 2000nm with chemical vapour deposition technique.Thereafter, carried out the ultraviolet light curing process 20 minutes, wherein ultraviolet wavelength is 100～400nm, and temperature is 400 degree Celsius; Pressure is 200 torrs.
Comparative example 1
With elevated temperature heat technology deposited silicon nitride layer 550nm in substrate, carried out the ultraviolet light curing process afterwards 5 minutes, deposit the non-impurity-doped silex glass of 2000nm again with chemical vapour deposition technique.In the ultraviolet light curing process, ultraviolet wavelength is 100～400nm.Temperature is 400 degree Celsius; Pressure is 200 torrs.
Comparative example 2
With elevated temperature heat technology deposited silicon nitride layer 550nm in substrate, afterwards, with the non-impurity-doped silex glass of chemical vapour deposition technique deposition 2000nm.
Above interpretation is in following table 1:
Table 1
| Flow process | Example 1 | Example 2 | Comparative example 1 | Comparative example 2 | |
| 1 | Deposited silicon nitride layer | 550nm | 550nm | 550nm | 550nm |
| 2 | The ultraviolet light slaking | Do not have | 5 minutes | 5 minutes | Do not have |
| 3 | Deposition non-impurity-doped silex glass | 2000nm | 2000nm | 2000nm | 2000nm |
| 4 | The ultraviolet light slaking | 20 minutes | 20 minutes | Do not have | Do not have |
| 5 | Stress (Mpa) | 600 | 900 | 530 | 200 |
Handle after the non-impurity-doped glass dielectric layer 20 minutes the amplitude that its stress promotes 50% nearly through experiment showed, with the ultraviolet light curing process.
Comprehensive the above, the present invention can increase the stress of CESL and dielectric layer, increases the firing current of element, promotes the firing current yield value.And, can reduce the aqueous vapor in the dielectric layer, the problem of avoiding contact hole to open.In addition, the present invention can avoid producing the extra key that suspends, and effectively increases the tensile stress of dielectric layer.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that accompanying Claim defines.
Claims (31)
1. the manufacture method of a semiconductor element is applicable to that in the substrate that forms metal oxide semiconductor transistor, this method comprises:
In this substrate, form contact hole etching and stop layer;
This contact hole etching is stopped layer carrying out the first ultraviolet light curing process;
Stop to form on the layer dielectric layer at this contact hole etching, wherein the material of this dielectric layer is silica, non-impurity-doped silex glass, boron-phosphorosilicate glass, phosphorosilicate glass or advanced low-k materials;
This dielectric layer is carried out the second ultraviolet light curing process;
On this dielectric layer, form cap layer; And
Carry out CMP (Chemical Mechanical Polishing) process.
2. the manufacture method of semiconductor element as claimed in claim 1, wherein carry out this first with the temperature of this second ultraviolet light curing process be that 150 degree Celsius are to 700 degree.
3. the manufacture method of semiconductor element as claimed in claim 1, wherein carry out this first with time of this second ultraviolet light curing process be 30 seconds to 60 minutes.
4. the manufacture method of semiconductor element as claimed in claim 1, wherein carry out this first with the pressure of this second ultraviolet light curing process be 3 milli torr to 500 torrs.
5. the manufacture method of semiconductor element as claimed in claim 1, wherein carry out this first with the ultraviolet light wavelength of this second ultraviolet light curing process be 100nm to 400nm.
6. the manufacture method of semiconductor element as claimed in claim 1, wherein those steps are to carry out according to following putting in order:
In this substrate, form this contact hole etching and stop layer;
Carry out this first ultraviolet light curing process;
Stop to form on the layer this dielectric layer at this contact hole etching;
Carry out this second ultraviolet light curing process;
Carry out CMP (Chemical Mechanical Polishing) process; And
On this dielectric layer, form cap layer.
7. the manufacture method of semiconductor element as claimed in claim 1, wherein those steps are to carry out according to following putting in order:
In this substrate, form this contact hole etching and stop layer;
Carry out this first ultraviolet light curing process;
Stop to form on the layer this dielectric layer at this contact hole etching;
On this dielectric layer, form cap layer;
Carry out this second ultraviolet light curing process; And
Carry out CMP (Chemical Mechanical Polishing) process.
8. the manufacture method of semiconductor element as claimed in claim 1, wherein those steps are to carry out according to following putting in order:
In this substrate, form this contact hole etching and stop layer;
Carry out this first ultraviolet light curing process;
Stop to form on the layer this dielectric layer at this contact hole etching;
On this dielectric layer, form cap layer;
Carry out CMP (Chemical Mechanical Polishing) process; And
Carry out this second ultraviolet light curing process.
9. the manufacture method of semiconductor element as claimed in claim 1 also is included in this contact hole etching and stops layer below formation resistance barrier oxide layer.
10. the manufacture method of a semiconductor element is applicable in the substrate that forms metal oxide semiconductor transistor, comprising:
In this substrate, form first contact hole etching and stop layer;
This first contact hole etching is stopped layer carrying out the first ultraviolet light curing process;
Stop to form on the layer second contact hole etching at this first contact hole etching and stop layer;
Stop to form on the layer dielectric layer at this second contact hole etching, wherein, the material of this dielectric layer is silica, non-impurity-doped silex glass, boron-phosphorosilicate glass, phosphorosilicate glass or advanced low-k materials;
This dielectric layer is carried out the second ultraviolet light curing process;
On this dielectric layer, form cap layer; And
Carry out CMP (Chemical Mechanical Polishing) process.
11. the manufacture method of semiconductor element as claimed in claim 10 is wherein carried out this and first is respectively 150 degree Celsius to 700 degree with the temperature of this second ultraviolet light curing process.
12. the manufacture method of semiconductor element as claimed in claim 10 is wherein carried out this and first was respectively 30 seconds to 60 minutes with time of this second ultraviolet light curing process.
13. the manufacture method of semiconductor element as claimed in claim 10 is wherein carried out this and first is respectively 3 milli torr to 500 torrs with the pressure of this second ultraviolet light curing process.
14. the manufacture method of semiconductor element as claimed in claim 10 is wherein carried out this and first is respectively 100nm to 400nm with the ultraviolet light wavelength of this second ultraviolet light curing process.
15. the manufacture method of semiconductor element as claimed in claim 10, wherein those steps are to carry out according to following putting in order:
In this substrate, form this first contact hole etching and stop layer;
Carry out this first ultraviolet light curing process;
Stop to form on the layer this second contact hole etching at this first contact hole etching and stop layer;
Stop to form on the layer this dielectric layer at this second contact hole etching;
Carry out this second ultraviolet light curing process;
Carry out this CMP (Chemical Mechanical Polishing) process; And
On this dielectric layer, form this cap layer.
16. the manufacture method of semiconductor element as claimed in claim 10, wherein those steps are to carry out according to following putting in order:
In this substrate, form this first contact hole etching and stop layer;
Carry out this first ultraviolet light curing process;
Stop to form on the layer this second contact hole etching at this first contact hole etching and stop layer;
Stop to form on the layer this dielectric layer at this second contact hole etching;
On this dielectric layer, form this cap layer;
Carry out this second ultraviolet light curing process; And
Carry out this CMP (Chemical Mechanical Polishing) process.
17. the manufacture method of semiconductor element as claimed in claim 10, wherein those steps are to carry out according to following putting in order:
In this substrate, form this first contact hole etching and stop layer;
Carry out this first ultraviolet light curing process;
Stop to form on the layer this second contact hole etching at this first contact hole etching and stop layer;
Stop to form on the layer this dielectric layer at this second contact hole etching;
On this dielectric layer, form this cap layer;
Carry out this CMP (Chemical Mechanical Polishing) process; And
Carry out this second ultraviolet light curing process.
18. the manufacture method of semiconductor element as claimed in claim 10 also is included in this first contact hole etching and stops layer below formation resistance barrier oxide layer.
19. the manufacture method of a semiconductor element is applicable in the substrate that forms metal oxide semiconductor transistor, comprising:
In this substrate, form first contact hole etching and stop layer;
This first contact hole etching is stopped layer carrying out the first ultraviolet light curing process;
Stop to form on the layer second contact hole etching at this first contact hole etching and stop layer;
This second contact hole etching is stopped layer carrying out the second ultraviolet light curing process;
Stop to form on the layer dielectric layer at this second contact hole etching, wherein, the material of this dielectric layer is silica, non-impurity-doped silex glass, boron-phosphorosilicate glass, phosphorosilicate glass or advanced low-k materials;
This dielectric layer is carried out the 3rd ultraviolet light curing process;
On this dielectric layer, form cap layer; And
Carry out CMP (Chemical Mechanical Polishing) process.
20. the manufacture method of semiconductor element as claimed in claim 19, wherein carry out this first, this second is respectively 150 degree Celsius to 700 degree with the temperature of the 3rd ultraviolet light curing process.
21. the manufacture method of semiconductor element as claimed in claim 19, wherein carry out this first, this second was respectively 30 seconds to 60 minutes with time of the 3rd ultraviolet light curing process.
22. the manufacture method of semiconductor element as claimed in claim 19, wherein carry out this first, this second is respectively 3 milli torr to 500 torrs with the pressure of the 3rd ultraviolet light curing process.
23. the manufacture method of semiconductor element as claimed in claim 19, wherein carry out this first, this second is respectively 100nm to 400nm with the ultraviolet light wavelength of the 3rd ultraviolet light curing process.
24. the manufacture method of semiconductor element as claimed in claim 19, wherein those steps are to carry out according to following putting in order:
In this substrate, form this first contact hole etching and stop layer;
Carry out this first ultraviolet light curing process;
Stop to form on the layer this second contact hole etching at this first contact hole etching and stop layer;
Carry out this second ultraviolet light curing process;
Stop to form on the layer this dielectric layer at this second contact hole etching;
Carry out the 3rd ultraviolet light curing process;
Carry out this CMP (Chemical Mechanical Polishing) process; And
On this dielectric layer, form this cap layer.
25. the manufacture method of semiconductor element as claimed in claim 19, wherein those steps are to carry out according to following putting in order:
In this substrate, form this first contact hole etching and stop layer;
Carry out this first ultraviolet light curing process;
Stop to form on the layer this second contact hole etching at this first contact hole etching and stop layer;
Carry out this second ultraviolet light curing process;
Stop to form on the layer this dielectric layer at this second contact hole etching;
On this dielectric layer, form this cap layer;
Carry out the 3rd ultraviolet light curing process; And
Carry out this CMP (Chemical Mechanical Polishing) process.
26. the manufacture method of semiconductor element as claimed in claim 19, wherein those steps are to carry out according to following putting in order:
In this substrate, form this first contact hole etching and stop layer;
Carry out this first ultraviolet light curing process;
Stop to form on the layer this second contact hole etching at this first contact hole etching and stop layer;
Carry out this second ultraviolet light curing process;
Stop to form on the layer this dielectric layer at this second contact hole etching;
On this dielectric layer, form this cap layer;
Carry out this CMP (Chemical Mechanical Polishing) process; And
Carry out the 3rd ultraviolet light curing process.
27. the manufacture method of semiconductor element as claimed in claim 19 also is included in this first contact hole etching and stops layer below formation resistance barrier oxide layer.
28. a semiconductor element comprises:
Metal oxide semiconductor transistor is positioned in the substrate;
Contact hole etching stops layer and covers this metal oxide semiconductor transistor;
Dielectric layer covers this contact hole etching and stops layer, this dielectric layer by the ultraviolet light curing process handle from and stress be 0.1 to 1.0GPa, the material of this dielectric layer is silica, non-impurity-doped silex glass, boron-phosphorosilicate glass, phosphorosilicate glass or advanced low-k materials; And
Cap layer covers this dielectric layer.
29. semiconductor element as claimed in claim 28, wherein this contact hole etching stop the layer material comprise silicon nitride.
30. semiconductor element as claimed in claim 28 also comprises resistance barrier oxide layer, is positioned at this contact hole etching and stops layer below.
31. semiconductor element as claimed in claim 30, wherein the material of this resistance barrier oxide layer comprises silica.
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| CNB200710092048XA CN100570853C (en) | 2007-04-04 | 2007-04-04 | Semiconductor element and manufacture method thereof |
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| CNB200710092048XA CN100570853C (en) | 2007-04-04 | 2007-04-04 | Semiconductor element and manufacture method thereof |
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| DE102018116726A1 (en) * | 2017-11-15 | 2019-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective high-k formation in a gate-load process |
| US10515809B2 (en) | 2017-11-15 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective high-K formation in gate-last process |
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