CN100568389C

CN100568389C - Reduce the semiconductor devices of coupled noise

Info

Publication number: CN100568389C
Application number: CNB2005100592556A
Authority: CN
Inventors: 边大锡
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2004-03-25
Filing date: 2005-03-25
Publication date: 2009-12-09
Anticipated expiration: 2025-03-25
Also published as: DE102005014627B4; JP2005276422A; DE102005014627A1; JP4772350B2; CN1674158A

Abstract

Semiconductor devices, semiconductor storage unit or flash memory comprise higher-pressure region, low-pressure area that contains low voltage component and the switching transistor that is connected higher-pressure region and low-pressure area such as the low tension switch transistor that contains high voltage device.Switching transistor reduces or eliminates the coupled noise of reading between the node, and chip area is increased.

Description

Reduce the semiconductor devices of coupled noise

The application requires the right of priority of the korean patent application that proposed on March 25th, 2004 2004-020424 number, quotes in full hereby, for your guidance.

Technical field

The present invention relates to semiconductor devices, be specifically related to be used to reduce the semiconductor devices of coupled noise.

Background technology

More and more need the higher memory device of density in the development aspect the multimedia application of cellular phone, PDA (personal digital assistant), digital camera etc. recently.Legacy memory comprises dynamic RAM (DRAM), static RAM (SRAM) and nonvolatile memory (NVM).Nonvolatile memory can comprise mask ROM (ROM), Electrically Erasable Read Only Memory (EEPROM) and flash memory.Nonvolatile memory can obliterated data in outage, but does not generally allow random access, and is slower than volatile memory.

Flash memory can form by combination Erasable Programmable Read Only Memory EPROM (EPROM) and Electrically Erasable Read Only Memory (EEPROM).Flash memory can be NAND or NOR flash memory.In flash memory,, can wipe and programming operation by different voltages are imposed on each flash memory cell.

Because to the requirements at the higher level of highly dense storer, the flash memory such as flash-EEPROM has been used in the supplementary storage or has needed in the systems programming application of renewal continuously.Flash-EEPROM can also have the integrated level higher than traditional E EPROM.

But because the coupled noise between the sense wire of page buffer, may there be readout error in flash memory.Readout error in order to reduce coupled noise and to cause can enlarge the space of reading between the node, maybe signal wire (for example, VDD or VSS line) can be inserted between the sense wire.These two kinds of solutions all exist needs to increase the storage core chip size and/or increase the shortcoming of manufacturing cost.

With reference to Fig. 1, the conventional flash memory part such as NAND type flash memory device can comprise the memory cell array 10 that is used to store data.Memory cell array 10 can comprise several unit strings (can be called the NAND string) that are connected with respective bit line.Each unit strings can comprise that the string select transistor that is connected with respective bit line, the ground that is connected with the common source polar curve select transistor and be connected on string select transistor and storage unit between the transistor is selected on ground.

Fig. 1 illustration 4 pairs of bit line (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O), still, the bit line of any amount (usually more than 4 pairs) can be connected with memory cell array 10.Each bit line is to being electrically connected with respective page impact damper PB0, PB1, PB2 and PB3.

Each of page buffer PB0, PB1, PB2 and PB3 can be used from and read/examine operation sensor amplifier effect and play a part according to being the driver that the program run data programmed drives bit line.Page buffer PB0, PB1, PB2 and PB3 can be identical, and therefore, the constituent element of page buffer PB0, PB1, PB2 and PB3 can be represented with same label, and only needs are described page buffer (for example, configuration PB0).

Page buffer PB0 can comprise bit line selection and biasing circuit 22, pre-charge circuit 24 and read and latch cicuit 26.Bit line is selected can comprise NMOS (N NMOS N-channel MOS N) transistor HT0, HT1, HT2 and HT3 with biasing circuit 22.Nmos pass transistor HT0 can be connected between power lead VIRPWR and the bit line BL0E and suspension control signal VBLe control.Nmos pass transistor HT1 can be connected between power lead VIRPWR and the bit line BL0_O and suspension control signal VBLo control.Nmos pass transistor HT2 can be connected bit line BL0_E and read between the node SO0, and nmos pass transistor HT3 can be connected bit line BL0_O and read between the node SO0.Nmos pass transistor HT2 and HT3 can distinguish suspension control signal BLSLTe and BLSLTo control.Each of nmos pass transistor HT0-HT3 can be for example to have the approximately high voltage transistor of the voltage breakdown of 28V.

Pre-charge circuit 24 can comprise PMOS transistor LT0, and PMOS transistor LT0 can be connected supply voltage and read between the node SO0 (also can be called sense wire) and suspension control signal PLOAD control.

Read with latch cicuit 26 and can comprise nmos pass transistor LT1, LT2 and LT3 and the latch LAT that comprises phase inverter INV0 and INV1.Nmos pass transistor LT2 and LT3 can be connected on latching between node N2 and the ground voltage of latch LAT.The grid of nmos pass transistor LT2 can be electrically connected with reading node SO0, and the grid of nmos pass transistor LT3 can connect into reception control signal PBLCH.Nmos pass transistor LT1 can be connected electrically in and read latching between the node N1 and suspension control signal LCHDRV control of node SO0 and latch LAT.Latch node N1 and can be used as page buffer data I/O node PB_DIO0, it is connected with column decoder 60.The PMOS of nmos pass transistor LT0-LT3 and formation phase inverter INV0 and INV1 and each of nmos pass transistor can be for example to have the approximately low voltage transistor of the voltage breakdown of 7V.

As mentioned above, high voltage transistor can be used in the bit line selection and biasing circuit 22 of each page buffer PB0, PB1, PB2 and PB3.This may be because the higher pressure that the source area of the string select transistor by memory array 10 can make high capacity (bulb) district that imposes on memory cell array 10 (for example, about 20V) is delivered to bit line (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O).For this reason, nmos pass transistor HT2 among each page buffer PB0, PB1, PB2 and the PB3 and HT3 can be made up of the higher pressure transistor, are passed to corresponding pre-charge circuit 24 and read and latch cicuit 26 to prevent higher pressure.

Similarly, nmos pass transistor HT0 among each page buffer PB0, PB1, PB2 and the PB3 and HT1 can be by during erase operations, can resist higher pressure and be passed to respective bit line (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O) higher pressure transistor is formed.

High voltage transistor can be made voltage breakdown, and low voltage transistor can be made the voltage breakdown that in P type/N type potential well, has about 7V with about 28V.Hereinafter, will form the transistorized zone of higher pressure and be called higher-pressure region (or high voltage circuit area), and the zone that will form than low voltage transistor is called low-pressure area (or low-voltage circuit district).

In each page buffer PB0, PB1, PB2 and PB3, the nmos pass transistor of respective bit line selection and biasing circuit 22 can form in the higher-pressure region and corresponding pre-charge circuit 24 can form in low-pressure area with the MOS transistor of reading with latch cicuit 26.

For example, with reference to Fig. 2 a and Fig. 2 b, Fig. 2 a illustration the sequential chart of read operation of the flash memory of Fig. 1 described, Fig. 2 b illustration the example layout of page buffer PB0, PB1, PB2 and PB3 of Fig. 1, the constituent element of selection of page buffer PB0 neutrality line and biasing circuit 22 (promptly, high voltage transistor) can be arranged in higher-pressure region 30, pre-charge circuit 24 can be arranged in low-pressure area 32 with the constituent element of reading with latch cicuit 26 (that is low voltage transistor) among the page buffer PB0.Similarly, the constituent element of selection of page buffer PB1 neutrality line and biasing circuit 22 (promptly, high voltage transistor) also can be arranged in higher-pressure region 34, and pre-charge circuit 24 can be arranged in low-pressure area 36 with the constituent element of reading with latch cicuit 26 (that is low voltage transistor) among the page buffer PB1.Other page buffer for example high voltage transistor of PB2, PB3 etc. also can be arranged in corresponding higher-

pressure region

38,42 etc., and the low voltage transistor of other page buffer also can be arranged in corresponding low-pressure area 40,44 etc.

Shown in Fig. 2 b, higher-

pressure region

30,34,38 and 42 collectives can be arranged with bit line (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O) more approaching, with low-

pressure area

32,36,40 and 44 collectives can be arranged the line of offing normal (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O) more farther.The advantage of An Paiing is to reduce the repetition in the potential well space between higher-pressure region and the low-pressure area like this.If do not use the arrangement as shown in Fig. 2 b that is a kind of, must repeat the potential well space between higher-pressure region and the low-pressure area, thereby increase layout dimension.

But, when the page buffer layout with Fig. 2 b be used for page buffer PB0, PB1, PB2 and PB3 read node the time, sense wire SO0, SO1, SO2 and SO3 may be from the higher-

pressure region

30,34,38 and 42 extend to low-

pressure area

32,36,40 and 44.This layout may cause more clearly obtain illustrative readout error in Fig. 2 a.

As mentioned above, Fig. 2 a illustration the sequential chart of read operation of the such flash memory device of the device of image pattern 1.As shown in the figure, the read operation of flash memory device can comprise page buffer reset the interval T1 of interval T0, bit-line pre-charge, read interval T2 and latch interval T3.Be described in more detail below each interval.

In page buffer resets interval T0, control signal VBLe, VBLo, BLSLTe, BLSLTo, LCHDRV and PLOAD can be arranged to first level (for example, " height " level) and ground voltage can be supplied to power lead VIRPWR.This makes bit line BLi_E and BLi_O (i=1-3) and latchs node N1 and be connected with power lead VIRPWR.Bit line BLi_E and BLi_O and latch node N1 and can be configured to ground voltage.That is to say bit line BLi_E and BLi_O and latch node N1 and can in page buffer resets interval T0, be resetted.

The odd bit lines BLi_O that supposes to select the right even bitlines BLi_E of bit line and do not select it, in the interval T1 of bit-line pre-charge, control signal VBLe, BLSLTo, LCHDRV and PLOAD (for example can be arranged to second level, and control signal VBLo continues to remain on first level (height) " low " level).Control signal BLSLTe can be configured to the voltage of about 1.5V.

Under these conditions, bit selecting line BLi_O can not select to be electrically connected with power lead VIRPWR with the nmos pass transistor HT1 of biasing circuit 22 by respective bit line.That is to say that the sparking voltage on the bit selecting line BLi_O can not remain unchanged.

Simultaneously, along with the PMOS transistor LT0 conducting of page buffer PB0-PB3, can be with supply voltage to reading node SO0-SO3 charging.Be applied in grid because voltage is the control signal BLSLTe of about 1.5V, use (1.5V-Vth) (Vth is the starting voltage of nmos pass transistor) selected bit line BLi_E precharge to the nmos pass transistor HT2 of page buffer PB0-PB3.For example, can be with about 0.8V to selected bit line BLi_E precharge.

In reading interval T2, control signal VBLe, VBLo, BLSLTo, LCHDRV and PLOAD can remain on situation identical in the interval T1 of bit-line pre-charge under, and control signal BLSLTe is configured to second (low) level.So just turn-offed the nmos pass transistor HT2 of page buffer PB0-PB3.In this state, can keep or reduce pre-charge voltage on the selected bit line BLi_E according to the state (" conducting " state or " shutoff " state) of the storage unit that is connected with selected bit line BLi_E.Shown in Fig. 2 a, the storage unit of supposing conducting state is connected with BL3_E with selected bit line BL0_E, BL2_E, be connected with selected bit line BL1_E with the storage unit of off state, therefore, pre-charge voltage on selected bit line BL0_E, BL2_E and the BL3_E ground voltage can be lowered into, and the pre-charge voltage on the selected bit line BL1_E can be kept.

Along with control signal PLOAD is configured to first (height) level in latching interval T3, can turn-off the PMOS transistor LT0 of page buffer PB0-PB3, cause and read node SO0, SO1, SO2 and SO3 and " floated ".Under this situation, approximately the voltage of 1.0V imposes on control signal BLSLTe.Because the pre-charge voltage on the bit line BL1_E remains unchanged, the nmos pass transistor HT2 of page buffer PB1 is turned off.This is because the grid-source voltage Vgs (Vgs=1.0V-0.8V=0.2V) of nmos pass transistor HT2 is lower than starting voltage (0.7V) among the page buffer PB1.On the other hand, because the pre-charge voltage on bit line BL0_E, BL2_E and the BL3_E is by the storage unit discharge of conducting state, the nmos pass transistor HT2 conducting of other page buffer PB0, PB2 and PB3.The voltage of reading on node SO0, SO2 and the SO3 can discharge into ground voltage from supply voltage, and the voltage of reading on the node SO1 remains unchanged.

So just force and read the nmos pass transistor LT1 conducting that node SO1 is connected, turn-off with the nmos pass transistor LT2 that forces and read node SO0, SO2 to be connected with SO3.Thereafter, shown in Fig. 2 a, as control signal PBLCH during by chopping, among the page buffer PB0-PB3 value of latch LT according to read node SO0-SO3 go up voltage come fixed.

As mentioned above, the voltage of reading under floating state on the node SO0-SO3 can change over ground voltage from supply voltage selectively.Reading node and may be subjected to adjacent influence of reading the change in voltage of node under the floating state by for example coupling capacitance.

Shown in Fig. 2 b,, may exist coupling capacitance between the adjacent sense wire (in Fig. 2 b, C0-C2) because the adjacent node (or sense wire) of reading may be arranged in the direction vertical with bit line overlappingly.

Read voltage on node SO0 and the SO2 when supply voltage changes over ground voltage when adjacent, the voltage on the node SO1 read of floating state has reduced the corresponding voltage of coupling ratio (α) with coupling capacitance.This can be called coupled noise or read noise.

If floating state read voltage on the node SO1 is lower than nmos pass transistor LT2 because of coupled noise becomes (trip) voltage that opens circuit, as control signal PBLCH during, in latch LAT, may latch misdata by chopping.As a result, arrange for the page buffer layout shown in Fig. 2 b, the coupled noise between the adjacent sense wire (or node) may cause readout error.

Summary of the invention

One exemplary embodiment of the present invention aim to provide the coupled noise read between the node reduced or eliminated, comprise for example semiconductor storage unit of flash memory.

One exemplary embodiment of the present invention aims to provide and comprises the higher-pressure region of containing high voltage device, the low-pressure area that contains low voltage component and the semiconductor devices that is connected to the switching transistor between higher-pressure region and the low-pressure area, semiconductor storage unit or flash memory such as the low tension switch transistor.

In one exemplary embodiment of the present invention, in the higher-pressure region, adjacent sense wire is not overlapping in the direction vertical with bit line in the higher-pressure region.

In one exemplary embodiment of the present invention, in the higher-pressure region, adjacent sense wire is enough opened every getting mutually.

In one exemplary embodiment of the present invention, in the higher-pressure region, adjacent sense wire is not overlapping.

In one exemplary embodiment of the present invention, in the higher-pressure region, adjacent sense wire is not mutually face-to-face.

In one exemplary embodiment of the present invention, in the higher-pressure region, adjacent sense wire is in direction staged ground vertical with bit line or arrangement diagonally.

In one exemplary embodiment of the present invention, low-pressure area comprises that sense wire and higher-pressure region do not comprise sense wire.

One exemplary embodiment of the present invention aims to provide semiconductor devices, semiconductor storage unit, comprise the flash memory of several page buffers, flash memory one or several page buffers or be used for the circuit of flash memory.Each page buffer can comprise bit line selection and biasing circuit, read with latch cicuit with such as the transistorized switching transistor of low tension switch.

Description of drawings

In conjunction with the drawings, the preferred embodiments of the present invention are carried out following description, can more fully understand the present invention, provide these accompanying drawings just for illustrative purpose, rather than in order to limit the present invention.

Fig. 1 illustration the conventional flash memory part such as NAND type flash memory device;

Fig. 2 a illustration the sequential chart of read operation of the flash memory of Fig. 1 described;

Fig. 2 b illustration such as the example layout of the page buffer of the such conventional flash memory part of the device of Fig. 1;

Fig. 3 illustration according to the present invention the page buffer of the flash memory device of one exemplary embodiment;

Fig. 4 a illustration the sequential chart of the read operation of the flash memory of one exemplary embodiment according to the present invention described;

Fig. 4 b illustration according to the present invention the example layout of the page buffer of the flash memory device of one exemplary embodiment;

Fig. 5 illustration according to the present invention the page buffer of the flash memory device of another one exemplary embodiment;

Fig. 6 a illustration according to the present invention the reading and latch cicuit of one exemplary embodiment;

Fig. 6 b illustration according to the present invention one exemplary embodiment Fig. 6 a read sequential chart with latch cicuit.

Should be noted that these figures are used for the method for illustration one exemplary embodiment of the present invention and the general features of device, so that describe such one exemplary embodiment.But these figure do not draw in proportion and can not accurately reflect the feature of any given embodiment, should not be interpreted as the scope or the characteristic definition of the value of one exemplary embodiment or are defined as scope of the present invention.

Especially, for the sake of clarity, the relative thickness and the location in layer or zone may be reduced or exaggerative.And, when on directly forming or be stacked in other layer on the reference layer or pattern in reference layer or the substrate, forming one deck, think this layer be " " another layer or substrate " on " formation.

Embodiment

Fig. 3 illustration according to the present invention the page buffer of the flash memory device of one exemplary embodiment.As shown in Figure 3, one or more page buffer PB0 of the present invention, PB1, PB2 and PB3 can comprise switching transistor LT4.In Fig. 3, with those identical constituent elements among Fig. 1 with identical labelled notation, therefore, omit description of them.

Each switching transistor LT4 of page buffer PB0, PB1, PB2 and PB3 can be a low voltage transistor, and it is at the pre-charge circuit 24 that forms each page buffer PB0, PB1, PB2 and PB3 and read formation in the low-pressure area (or low-voltage circuit district) with latch cicuit 26.In each page buffer circuit, the drain electrode of switching transistor LT4 can be electrically connected with the grid that transistorized nmos pass transistor LT2 is read in conduct by corresponding sense wire SOi (i=0-3).The source electrode of switching transistor LT4 can be electrically connected with nmos pass transistor HT2 and HT3 to sense wire line segment BL_SOi by respective bit line.The switching transistor LT4 of page buffer PB0, PB1, PB2 and PB3 can control by suspension control signal BLSHF jointly.

In the flash memory of one exemplary embodiment according to the present invention, during read operation, supply voltage is imposed on the grid of the nmos pass transistor (HT2 or HT3) that is connected with selected bit line, and, in the different intervals of read operation, different voltages are imposed on the grid of switching transistor LT4.

In an exemplary embodiment, during read operation, switching transistor LT4 in conjunction with the described nmos pass transistor of Fig. 1 (HT2 or HT3), this means that bit line can be used as the part of selected bit line to sense wire line segment BL_SOi, rather than is used as the part of sense wire above can play a part.Different with Fig. 2 b, along existing a small amount of between the adjacent sense wire of the direction vertical or not having possibility to cause the coupling capacitance (in Fig. 2 b, being shown as C0-C2) of coupled noise with bit line.

For this layout arrangement, because adjacent sense wire is enough opened every getting mutually, so that it is not overlapping in the direction vertical with bit line, for example, not mutually " face-to-face " (or staged ground or arrangement diagonally), the sense wire of floating state are not subjected to the influence of the change in voltage (otherwise from the supply voltage to the ground voltage or) of adjacent sense wire.

Fig. 4 a illustration the example layout structure of the page buffer of the flash memory device of one exemplary embodiment of having described the sequential chart of read operation of flash memory of Fig. 3 and Fig. 4 b illustration according to the

present invention.Label

30,34,38 and 42 expression higher-pressure regions (or high voltage circuit area), and

label

32,36,40 and 44 expression low-pressure areas (or low-voltage circuit district).In page buffer PB0, PB1, PB2 and PB3, nmos pass transistor in bit line selection and the biasing circuit 22 can form in the higher-pressure region, and switching transistor LT4 and pre-charge circuit 24 can form in low-pressure area with the MOS transistor of reading with latch cicuit 26.

For example, with reference to Fig. 4 b, the bit line of page buffer PB0 is selected can be arranged in higher-pressure region 30 with the constituent element (that is high voltage transistor) of biasing circuit 22, and switching transistor LT4 and pre-charge circuit 24 can be arranged in low-pressure area 32 with the constituent element of reading with latch cicuit 26 (that is low voltage transistor).The bit line selection of page buffer PB1 and the constituent element of biasing circuit 22 are (promptly, high voltage transistor) can be positioned at higher-pressure region 34, and switching transistor LT4 and pre-charge circuit 24 can be arranged in low-pressure area 36 with the constituent element of reading with latch cicuit 26 (that is low voltage transistor).The high voltage transistor of other page buffer also can be arranged in corresponding higher-

pressure region

38 and 42 and the low voltage transistor (comprising switching transistor LT4) of other page buffer can be arranged in the corresponding low-pressure area 40 of low pressure and 44.

Although not shown in Fig. 3,4a and 4b, each low-pressure area can comprise P type potential well and N type potential well.Low voltage nmos transistor (for example, the nmos pass transistor of LT1, LT2, LT3, LT4 and phase inverter INV0 and INV1) can in P type potential well, form, and low voltage transistor (for example, the PMOS transistor of LT0 and phase inverter INV0 and INV1) can form in N type potential well.

Higher-

pressure region

30,34,38 and 42 collectives can be arranged in a zone neutralization that is arranged in the row with the more approaching zone neutralization of bit line and low-

pressure area

32,36,40 and 44 collectives can be arranged in away from bit line is arranged in the row.As mentioned above, can make higher-pressure region and low-pressure area collective be arranged in the same general position that is used for identical purpose.

Shown in Fig. 4 b, can partly sense wire SO0, SO1, SO2 and SO3 only be arranged in the corresponding low-pressure area.Especially, can partly sense wire SO0-SO3 be arranged in the corresponding low-pressure area, make the direction vertical not overlapping (making not " face-to-face " mutually) with bit line.In other words, sense wire SO0-SO3 can or be arranged in the corresponding low-pressure area diagonally by staged ground, makes in the direction vertical with bit line not overlapping.

Can partly sense wire SO0-SO3 be arranged in the corresponding low-pressure area, make to have identical or essentially identical length mutually, or make to have different length mutually.So the sort of different with shown in Fig. 2 b are along existing a small amount of between the adjacent sense wire of the direction vertical with bit line or not having possibility to cause that the coupling capacitance of coupled noise is (in Fig. 2 b, C0-C2).

For this layout arrangement and since adjacent sense wire mutually every enough open, any sense wire of floating state is not subjected to the influence of the change in voltage (otherwise from the supply voltage to the ground voltage or) of adjacent sense wire.

As mentioned above,, under floating state, read voltage on node (or line) SO0-SO3 and have selectively and change over ground voltage from supply voltage although in reading the interval, floating state read the influence that node is not subjected to the change in voltage of adjacent sense wire.

As mentioned above, Fig. 4 a illustration relevant according to the present invention the sequential chart of the read operation of the flash memory device of one exemplary embodiment, below this is made more detailed description.

In page buffer resetted interval T0, control signal VBLe, VBLo, BLSLTe, BLSLTo, LCHDRV, PLOAD and BLSHF transitted to first level (for example, " height " level), and ground voltage is supplied to power lead VIRPWR.This makes bit line BLi_E and BLi_O (i=1-3) and latchs node N1 and be connected with power lead VIRPWR.Bit line BLi_E and BLi_O and latch node N1 and can be configured to ground voltage that is to say, bit line BLi_E and BLi_O and latch node N1 and can be resetted in page buffer resets interval T0.The odd bit lines BLi_O that supposes to select the right even bitlines BLi_E of bit line and do not select it.

In the interval T1 of bit-line pre-charge, control signal VBLe, BLSLTo, LCHDRV and PLOAD can be arranged to second level (for example, " low " level), and control signal VBLo and BLSLTe continue to remain on first (height) level.At this moment, shown in Fig. 4 a, control signal BLSHF can be configured to have the voltage of about 1.5V.For these conditions, bit selecting line BLi_O can not select to be electrically connected with power lead VIRPWR with the nmos pass transistor HT1 of biasing circuit 22 by respective bit line.That is to say that the sparking voltage on the bit selecting line BLi_O does not remain unchanged.

Simultaneously, along with the PMOS transistor turns of page buffer PB0, PB1, PB2 and PB3, charge to reading node SO0-SO3 with supply voltage.Because the control signal BLSLTe of high level is applied in the grid to the nmos pass transistor HT2 of page buffer PB0, PB1, PB2 and PB3, nmos pass transistor HT2 conducting, pairs of bit line precharge fully.Because the control signal BLSHF with voltage of about 1.5V is applied in the grid to nmos pass transistor LT4, with (1.5V-Vth) (Vth is the starting voltage of nmos pass transistor) to selected bit line BLi_E precharge.That is to say, with about 0.8V to selected bit line BLi_E precharge.

In reading interval T2, control signal VBLe, VBLo, BLSLTe, BLSLTo, LCHDRV and PLOAD can remain on situation identical in the interval T1 of bit-line pre-charge under, and control signal BLSHF is configured to the low level of ground voltage.So just turn-offed the nmos pass transistor LT4 of page buffer PB0-PB3.In this state, can keep or reduce pre-charge voltage on the selected bit line BLi_E according to the state (" conducting " state or " shutoff " state) of the storage unit that is connected with selected bit line BLi_E.Shown in Fig. 4 a, the storage unit of supposing conducting state is connected with BL3_E with selected bit line BL0_E, BL2_E, be connected with selected bit line BL1_E with the storage unit of off state, therefore, pre-charge voltage on bit line BL0_E, BL2_E and the BL3_E can be lowered into ground voltage, and keep the pre-charge voltage on the selected bit line BL1_E constant.

Along with control signal PLOAD is configured to first (height) level in latching interval T3, can turn-off the PMOS transistor LT0 of page buffer PB0-PB3, cause and read node SO0, SO1, SO2 and SO3 and be in floating state.Under this situation, the voltage of about 1.0V can be imposed on control signal BLSHF.Because the pre-charge voltage on the bit line BL1_E remains unchanged, the nmos pass transistor HT2 of page buffer PB1 can turn-off.This is because the grid-source voltage Vgs (Vgs=1.0V-0.8V=0.2V) of nmos pass transistor LT4 is lower than starting voltage (0.7V) among the page buffer PB1.

On the other hand, because the pre-charge voltage on bit line BL0_E, BL2_E and the BL3_E is by the storage unit discharge of conducting state, the nmos pass transistor LT4 conducting of other page buffer PB0, PB2 and PB3.Shown in Fig. 4 a, the voltage of reading on node SO0, SO2 and the SO3 discharges into ground voltage from supply voltage, and the voltage of reading on the node SO1 remains unchanged.So just force and read the nmos pass transistor LT2 conducting that node SO1 is connected, and the nmos pass transistor LT2 that forces and read node SO0, SO2 to be connected with SO3 turn-offs.Thereafter, shown in Fig. 4 a, as control signal PBLCH during by chopping, among page buffer PB0, PB1, PB2 and the PB3 value of latch LAT can according to read node SO0-SO3 go up voltage come fixed.

As mentioned above, although in reading the interval, the voltage of reading under floating state on node (or line) SO0-SO3 changes over ground voltage from supply voltage selectively, but the node of reading under the floating state is not subjected to adjacent influence of reading the change in voltage of node (or line).

Shown in Fig. 4 b,, between adjacent sense wire (or node), exist on a small quantity or do not have coupling capacitance (in Fig. 2 b, C0-C2) because adjacent sense wire (or node) is arranged in the direction vertical with bit line not overlapping (or not mutually " face-to-face ").So coupled noise can not cause readout error.

Although in the one exemplary embodiment of Fig. 3 of the present invention, in Fig. 4 a and 4b illustration page buffer and the layout structure of 4 bit lines to being connected, apparent, can repeat and identical circuit-mode as shown in Figs. 4a and 4b.

In addition, the control signal BLSHF that imposes on the grid of switching transistor LT4 in erase operation can be configured to supply voltage or ground voltage.During program run, control signal BLSHF can be configured to identical with supply voltage or higher than supply voltage voltage, so that according to the data that are stored in the latch supply voltage or ground voltage are supplied to bit line.In addition, examining operating period, can be uniformly set control signal BLSHF with read operation.As a result, can easily revise reading and latch cicuit of each page buffer 26.

For example,, can realize reading in each page buffer the nmos pass transistor LT1 with latch cicuit 26 like this, it is not connected with sense wire SOi (i=0-3), but be connected to sense wire BL_SOi with bit line with reference to Fig. 5.In this example, the sense wire of each page buffer PB0, PB1, PB2 and PB3 can be arranged in the corresponding low-pressure area (or low-voltage circuit district), so that adjacent sense wire is arranged in the direction vertical with bit line not overlapping (or not mutually " face-to-face ").

And, with reference to Fig. 6 a and 6b, can realize like this reading and latch cicuit 26, make the voltage of reading on the node SOi be delivered to latch LAT by nmos pass transistor LT5.In this case, latch LAT can suspension control signal CSEN, CSENB, CLAT and CLATB control, to latch the voltage (or data) that transmits by transistor LAT5.In order to reach this purpose, shown in Fig. 6 a, can activate phase inverter INV2 by control signal CSEN and CSENB, can activate phase inverter INV3 by control signal CLAT and CLATB then.

One exemplary embodiment of the present invention can be a semiconductor devices.

One exemplary embodiment of the present invention can be a nonvolatile memory.

One exemplary embodiment of the present invention can be a flash memory.

One exemplary embodiment of the present invention can be NAND or NOR flash memory.

Although one exemplary embodiment of the present invention is described by means of 4 pairs of bit line and 4 page buffers, those of ordinary skill in the art should be understood that and can utilize any other number, and do not depart from scope and spirit of the present invention.

Although one exemplary embodiment of the present invention is described by means of switching transistor, those of ordinary skill in the art should be understood that and can use any other circuit arrangement, and do not depart from scope and spirit of the present invention.

Although one exemplary embodiment of the present invention is described at exemplary voltage, those of ordinary skill in the art should be understood that each that can change these voltages, and does not depart from scope and spirit of the present invention.For example, the voltage of definition higher-pressure region or high voltage transistor can be any voltage, as long as the voltage of definition higher-pressure region or high voltage transistor is greater than the voltage of definition low-pressure area or low voltage transistor.

Although one exemplary embodiment of the present invention is described as and utilizes the logic state low ' and ' height ', those of ordinary skill in the art should be understood that these logic states are tradable, and does not depart from scope and spirit of the present invention.

Although one exemplary embodiment of the present invention is described as and comprises that NMOS and PMOS transistor, those of ordinary skill in the art should be understood that and can use any other circuit arrangement, and does not depart from scope and spirit of the present invention.

For the person of ordinary skill of the art, apparent, in above-mentioned one exemplary embodiment, can make other changes and improvements, and do not depart from scope of the present invention, and it is exemplary to this means that all the elements that comprise in the above description should be interpreted as, rather than restrictive.

Claims

1. flash memory comprises:

First page buffer that contains first pairs of bit line; With

Second page buffer that contains second pairs of bit line;

In first and second page buffers each all comprises

Select the high-tension circuit of a bit lines of bit line pairs;

Low-voltage circuit by bit line sensing element data; With

The switching transistor that is connected with sense wire wherein, is being arranged to the sense wire staged in first and second page buffers, so that not overlapping in the direction vertical with bit line.

2. flash memory according to claim 1, each low-voltage circuit further comprises: the latch of latch data and read transistor.

3. flash memory according to claim 1, wherein, it is more right near respective bit line than each low-voltage circuit that each high-tension circuit is placed.

4. flash memory according to claim 2, wherein, each low-voltage circuit is placed in the low-pressure area, and low-pressure area comprises first and second potential well areas that are arranged in the row.

5. flash memory according to claim 4, wherein, the sense wire of first page buffer is arranged in first potential well area, and the sense wire of second page buffer is arranged in second potential well area.

6. flash memory according to claim 5, wherein, first potential well area comprises a transistorized P type potential well and a N type potential well of the low-voltage circuit that forms first page buffer, and second potential well area comprises transistorized the 2nd P type potential well and the 2nd N type potential well of the low-voltage circuit that forms second page buffer.

7. flash memory according to claim 1, wherein, the switching transistor in first and second page buffers is the low tension switch transistor.

8. flash memory according to claim 7, wherein, the switching transistor in first and second page buffers exists in the current path between high-tension circuit and the sense wire, and control signal is supplied to the grid of switching transistor.

9. flash memory according to claim 7, wherein, in the bit-line pre-charge interval, to read the interval be different with latching interval inner control voltage of signals.

10. flash memory according to claim 1, wherein, each low-voltage circuit comprises the precharge transistor of suspension control signal control.

11. a flash memory comprises:

Each all comprises several page buffers of pair of bit lines, and each page buffer comprises:

The bit line that contains the high voltage transistor of a bit lines of selecting bit line pairs is selected and biasing circuit;

Contain reading and latch cicuit of low voltage transistor by bit line sensing element data; With

At least one of connection high voltage transistor and at least one of low voltage transistor and the low tension switch transistor that is connected with sense wire wherein, are being arranged to the sense wire staged of adjacent page impact damper, so that not overlapping in the direction vertical with bit line.

12. flash memory according to claim 11, wherein, each is read with latch cicuit and low tension switch transistor and is placed in the low-pressure area, and low-pressure area comprises first and second potential well areas that are arranged in the row.

13. flash memory according to claim 11, wherein, the sense wire of first of several page buffers is arranged in first potential well area, and second sense wire of several page buffers is arranged in second potential well area.

14. flash memory according to claim 13, wherein, first potential well area comprises a P type potential well and the N type potential well with the low voltage transistor of latch cicuit of reading that forms first page buffer, and second potential well area comprises the 2nd P type potential well and the 2nd N type potential well with the low voltage transistor of latch cicuit of reading that forms second page buffer.

15. flash memory according to claim 11, wherein, each is read with latch cicuit and comprises: the latch of latch data and read transistor.

16. a flash memory comprises:

First page buffer that contains first pairs of bit line; With

Second page buffer that contains second pairs of bit line;

In first and second page buffers each comprises

The first high pressure bit line selection transistor circuit that is connected to the sense wire line segment with first bit line,

The second high pressure bit line selection transistor circuit that is connected to the sense wire line segment with second bit line and

The low tension switch transistor that is connected with sense wire,

Wherein, first bit line is connected with corresponding low tension switch transistor to the sense wire line segment with second bit line to the sense wire line segment;

Wherein, it is not overlapping that the sense wire of adjacent page impact damper is arranged in the direction vertical with the direction of every pairs of bit line.

17. flash memory according to claim 16, wherein, each first high pressure bit line selection transistor circuit and each second high pressure bit line selection transistor circuit are placed more right near respective bit line than each low tension switch transistor.

18. flash memory according to claim 16, wherein, each low tension switch transistor is placed in the low-pressure area, and low-pressure area comprises first and second potential well areas that are arranged in the row.

19. flash memory according to claim 18, wherein, the sense wire of first page buffer is arranged in first potential well area, and the sense wire of second page buffer is arranged in second potential well area.

20. flash memory according to claim 19, wherein, first potential well area comprises a transistorized P type potential well of the low tension switch that forms first page buffer and a N type potential well, and second potential well area comprises transistorized the 2nd P type potential well of the low tension switch that forms second page buffer and the 2nd N type potential well.

21. flash memory according to claim 16, wherein, each in first and second page buffers all comprises and is used for carrying out precharge low pressure precharge transistor to reading node.

22. flash memory according to claim 16, wherein, each in first and second page buffers all comprise with bit line to the corresponding low voltage driving transistor of sense wire line segment.

23. flash memory according to claim 16, wherein, each in first and second page buffers all comprises and the corresponding low voltage driving transistor of sense wire.

24. a semiconductor devices comprises:

Memory cell array contains several unit strings, and each unit strings is electrically connected with respective bit line, and wherein, in the middle of respective bit line, two adjacent bit lines formation bit lines are right;

With first page buffer of first bit line to being connected;

With second page buffer of second bit line to being connected;

In first and second page buffers each comprises

Select a bit lines of respective bit line centering, the bit line of selected bit line and sense wire coupling is selected and biasing circuit, bit line is selected to contain the high voltage device that is arranged in the higher-pressure region with biasing circuit,

With bit line to coupling, by bit line to the reading and latch cicuit of sensing element data, read with latch cicuit contain the low voltage component that is arranged in low-pressure area and

Connect bit line selection and biasing circuit and read and latch cicuit and the switching transistor that is connected with sense wire, wherein, arranging to the adjacent sense wire staged in first and second page buffers, so that not overlapping in the direction vertical with bit line; With

Select at least one in first and second page buffers, with the column selection circuit passband of selected page buffer and data bus coupling.

25. semiconductor devices according to claim 24, wherein, semiconductor devices is a flash memory.

26. a flash memory comprises:

The memory cell array that contains several unit strings, each of described several unit strings is electrically connected with respective bit line, and wherein, in the middle of respective bit line, two adjacent bit lines formation bit lines are right; With

With first and second page buffers of bit line to being connected, each page buffer comprises

Select a bit lines of respective bit line centering, with the high-tension circuit of selected bit line and sense wire coupling,

With described bit line to the coupling, by the low-voltage circuit of bit line to the sensing element data, described low-voltage circuit contains latch cicuit, first switching transistor and precharge transistor, first switching transistor is connected selected bit line with sense wire, wherein, arranging to adjacent sense wire staged in first and second page buffers, so that it is not overlapping in the direction vertical with bit line, control signal is supplied to the grid of first switching transistor, and precharge transistor is connected with sense wire, make sense wire be pre-charged to the required voltage level.

27. flash memory according to claim 26, wherein, in the bit-line pre-charge interval, to read the interval be different with latching interval inner control voltage of signals.

28. flash memory according to claim 26, wherein, low-voltage circuit further comprises the second switch transistor.

29. flash memory according to claim 28, the second switch transistor connects the node of sense wire and latch cicuit.

30. flash memory according to claim 28, the second switch transistor connects the node of selected bit line and latch cicuit.

31. flash memory according to claim 28, the second switch transistor is in the conducting of page buffer reseting period.

32. a flash memory comprises:

With bit line several page buffers to being connected, each page buffer comprises

Select a bit lines of respective bit line centering, with bit line selection and biasing circuit with selected bit line and sense wire coupling,

With bit line to coupling, by bit line to the reading and latch cicuit of sensing element data, read with latch cicuit and contain a latch units at least,

First switching transistor that connects bit line selection and biasing circuit and sense wire,

Connect sense wire and latch units node the second switch transistor and

Be connected, make sense wire to be pre-charged to the precharge transistor of required voltage level with sense wire.

33. flash memory according to claim 32, wherein, first switching transistor is controlled by three different voltage levels at least.

34. flash memory according to claim 32, wherein, the second switch transistor is in the conducting of page buffer reseting period.

35. a flash memory comprises:

With bit line to coupling, by bit line to the reading and latch cicuit of sensing element data, read with latch cicuit and contain at least one latch units,

Connect bit line selection and biasing circuit and latch units node the second switch transistor and

Be connected with sense wire, make sense wire be pre-charged to the precharge transistor of required voltage level.

36. flash memory according to claim 35, wherein, first switching transistor is controlled by three different voltage levels at least.

37. flash memory according to claim 35, wherein, the second switch transistor is in the conducting of page buffer reseting period.

38. the page buffer of a flash memory, this page buffer comprises:

Select and the right bit lines of page buffer corresponding bit line, the bit line of selected bit line and sense wire coupling is selected and biasing circuit;

First switching transistor that connects bit line selection and biasing circuit and sense wire;

With bit line to coupling, by bit line to the reading and latch cicuit of sensing element data, read with latch cicuit and contain

At least one latch units and

The second switch transistor, the node of connection bit line selection and biasing circuit and described at least one latch units; With

39. a circuit that is used for flash memory, this circuit comprises:

With read first switching transistor that node is connected;

At least one latch units of latch units data;

The second switch transistor connects the node of first switching transistor and described at least one latch units, and wherein, the described node of reading is between described first switching transistor and described second switch transistor; With

Precharge transistor is connected with described first switching transistor, reads node and is pre-charged to the required voltage level to make by described first switching transistor.