JP2005276422A - Semiconductor device for reducing coupling noise - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for reducing coupling noise. <P>SOLUTION: This semiconductor device, a semiconductor memory device or a flash memory includes a high voltage region including a high voltage component, a low voltage region including a low voltage component and a switch transistor for connecting the high voltage region and the low voltage region, such as a low voltage switch transistor. The switch transistor reduces or eliminates coupling noise between sensitive nodes, without increasing chip area. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

 The present invention relates to a nonvolatile semiconductor device, and more particularly to a NAND flash memory device.

 Newly developed products in the field of multimedia applications such as mobile phones, PDAs, digital cameras, etc. require increasingly highly integrated memory devices. Generally, a semiconductor device includes a dynamic random access memory (DRAM), a static random access memory (SRAM), and a nonvolatile memory (NVM). Non-volatile memories are classified into mass chrome (Read Only Memory) ROM, electrically erasable and programmable memory (EEPROM), and flash memory. Non-volatile memory does not lose data even when the power is turned off, but generally random access is not possible. Also slower than volatile memory.

 Flash memory consists of a combination of erasable and programmable memory (EPROM) and electrically erasable and programmable memory (EEPROM). The flash memory is a NAND or NOR flash memory. The erase and program operations of the flash memory are performed by applying another voltage to each flash memory cell.

 Due to the increasing demand for highly integrated memory, flash memory, such as flash EEPROM, has been used for auxiliary memory and system program applications that require continuous updates. A flash EEPROM has a higher integration density than a general EEPROM.

 However, in the flash memory, a read error due to coupling noise between the sensing lines of the page buffer can occur. To reduce coupling noise and read errors, the space between the sensing nodes is reduced or signal lines (eg, VDD or VSS lines) are inserted between the sensing lines. Both such solutions have the problem of increasing memory chip size and / or production costs.

 Referring to FIG. 1, a typical flash memory device such as a NAND type flash memory device includes a memory cell array 10 for storing data. The memory cell array 10 includes a number of cell strings (hereinafter referred to as NAND strings) connected to corresponding bit lines. Each cell string includes a string selection transistor connected to a corresponding bit line, a ground selection transistor connected to a common source line, and a memory cell connected in series between the string and the ground selection transistor.

 FIG. 1 shows four pairs of bit lines (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O), (BL3_E, BL3_O). However, a predetermined number (usually 4 or more) of bit lines are connected to the memory cell array 10. Each bit line pair is electrically connected to a corresponding page buffer PB0, PB1, PB2, PB3.

 Each of the page buffers PB0, PB1, PB2, and PB3 serves as a sense amplifier for a read / verify operation and as a driver that drives a bit line according to data programmed for a program operation. Operate. The page buffers PB0, PB1, PB2, and PB3 are the same, and therefore the components of the page buffers PB0, PB1, PB2, and PB3 are indicated by the same reference numerals. Only the features of one page buffer (for example, PB0) will be described.

 The page buffer PB 0 includes a bit line selection and bias circuit 22, a precharge circuit 24, and a sensing and latch circuit 26. The bit line selection and bias circuit 22 includes NMOS transistors HT0, HT1, HT2, and HT3. The NMOS transistor HT0 is connected between the power line VIRPWR and the bit line BL0_E and is controlled by a control signal VBLe. The NMOS transistor HT1 is connected between the power line VIRPWR and the bit line BL0_O and is controlled by a control signal VBLo. The NMOS transistor HT2 is connected between the bit line BL0_E and the sense node SO0, and the NMOS transistor HT3 is connected between the bit line BL0_O and the sense node SO0. The NMOS transistors HT2 and HT3 are controlled by control signals BLSLTe and BLSLTo, respectively. Each NMOS transistor HT0-HT3 is a high voltage transistor having a breakdown voltage of about 28V, for example.

 The precharge circuit 24 includes a PMOS transistor LT0. The PMOS transistor LT0 is controlled by a control signal PLOAD if it is connected between a power supply voltage and the sense node SO0 (hereinafter also referred to as a sense line).

 The sensing and latch circuit 26 includes a latch LAT having NMOS transistors LT1, LT2, LT3 and inverters INV0 and INV1. The NMOS transistors LT2 and LT3 are connected in series between the latch node N2 of the latch LAT and the ground voltage. The gate of the NMOS transistor LT2 is electrically connected to the sensing node SO0, and the gate of the NMOS transistor LT3 is connected to receive a control signal PBLCH. The NMOS transistor LT1 is electrically connected between the sense node SO0 and the latch node N1 of the latch LAT, and is controlled by a control signal LCHDRV. The latch node N1 is used as a page buffer data input / output node PB_DIO0 connected to the column decoder 60. The PMOS and NMOS transistors constituting each of the NMOS transistors LT1-LT3 and the inverters INV0, INV1 are, for example, low voltage transistors having a breakdown voltage of about 7V.

 As described above, the high voltage transistor is used for the bit line selection and bias circuit 22 of each of the page buffers PB0, PB1, PB2, and PB3. This is because a high voltage (for example, about 20V) applied to the bulk region of the memory cell array 10 passes through the source region of the string selection transistor of the memory array 10 and the bit lines (BL0_E, BL0_O), (BL1_E, BL1_O). ), (BL2_E, BL2_0), (BL3_E, BL3_0). Accordingly, the NMOS transistors HT2 and HT3 of each page buffer PB0, PB1, PB2, and PB3 are used to prevent a high voltage from being transmitted to the corresponding precharge circuit 24 and the sensing and latch circuit 26. Consists of high voltage transistors.

 Similarly, the NMOS transistors HT0 and HT1 of each page buffer PB0, PB1, PB2, and PB3 are connected to the corresponding bit lines (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_0) during an erase operation. ), (BL3_E, BL3_0), the high voltage transistor which can withstand the high voltage transmitted.

 The high voltage transistor is formed to have a breakdown voltage of about 28V, while the low voltage transistor is formed in the P-type / N-type well to have a breakdown voltage of about 7V. Hereinafter, a region where the high voltage transistor is formed is a high voltage region (or high voltage circuit region), and a region where the low voltage transistor is formed is a low voltage region (or low voltage circuit region).

 Each page buffer PB 0, PB 1, PB 2, PB 3, the corresponding bit line selection and bias circuit 22 NMOS transistor is formed in the high voltage region, the corresponding precharge circuit 24, and the corresponding precharge of the sensing and latch circuit 26. The MOS transistor of the circuit 24 is formed in the low voltage region.

 For example, FIG. 2A shows a timing diagram for describing the read operation of the flash memory of FIG. 1, and FIG. 2B shows an exemplary layout of the page buffers PB0, PB1, PB2, and PB3 of FIG. Referring to FIGS. 2A and 2B, the bit line selection and bias circuit 22 components of the page buffer PB0 (ie, high voltage transistors) are disposed in a high voltage region. The precharge circuit 24 of the page buffer PB0 and the components of the sense and latch circuit 26 (ie, low voltage transistors) are disposed in a low voltage region 36. The high voltage transistors such as the other page buffers PB2 and PB3 are disposed in the corresponding high voltage regions 38 and 42, and the low voltage transistors of the other page buffers are disposed in the corresponding low voltage regions 40 and 44.

 As shown in FIG. 2B, the high voltage regions 30, 34, 38, and 42 are gathered near the bit lines (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_0), (BL3_E, BL3_0). The low voltage regions 32, 36, 40, 44 are collectively aligned apart from the bit lines (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_0), (BL3_E, BL3_0). Is done. The advantage of such alignment is that the repetition of the well space between the high voltage region and the low voltage region can be reduced. If the alignment as shown in FIG. 2B is not used, the well space between the high voltage region and the low voltage region becomes repetitive, increasing the size of the layout.

 However, when using the page buffer layout shown in FIG. 2B for the sensing nodes of page buffers PB0, PB1, PB2, and PB3, the sensing lines SO0, SO1, SO2, and SO3 are connected to the high voltage regions 30, 34, respectively. , 38, 42 to the low voltage region 32, 36, 40, 44. Such a layout can cause read errors, which are clearly represented in FIG.

 As described above, FIG. 2A is a timing diagram illustrating a read operation of a flash memory device such as the device shown in FIG. The read operation of the flash memory device includes a page buffer reset period T0, a bit line precharge period T1, a sensing period T2, and a latch period T3. Each section is described in detail below.

 In the page buffer reset period T0, the control signals VBLe, VBLo, BLSLTe, BLSLTo, LCHDRV, and PLOAD are set to the first level (eg, high level), and the ground voltage is supplied to the power supply line VIRPWR. This connects the bit lines BLi_E, BLi_O (i = 0-3) and the latch node N1 to the power line VIRPWR. The bit lines BLi_E and BLi_O and the latch node N1 are fixed to the ground voltage. That is, the bit lines BLi_E and BLi_O and the latch node N1 are reset in the page buffer reset period T0.

 If the even bit line BLi_E of the bit line pair is selected and the odd bit line BLi_O is not selected, the control signals VBLe, BLSLTo, LCHDRV, and PLOAD are Fixed to the second level (yes, low level). On the other hand, the control signal VBLo maintains the first level (high). The control signal BLSLTe is fixed to have about 1.5V.

 Under such conditions, the unselected bit line BLi_O is electrically connected to the power line VIRPWR through the corresponding bit line selection and bias transistor 22 NMOS transistor HT1. That is, the discharged voltage of the unselected bit line BLi_O is maintained.

 At the same time, the PMOS transistors LT0 of the page buffers PB0 to PB3 are turned on, so that the sense nodes SO0 to SO3 are charged to the power supply voltage. Since the control signal BLSLTe of about 1.5V is applied to the gates of the NMOS transistors HT2 of the page buffers PB0 to PB3, the selected bit line BLi_E is precharged to a voltage of 1.5V-Vth (here , Vth is a threshold voltage of the NMOS transistor). For example, the selected bit line BLi_E is discharged to about 0.8V.

 In the sensing period T2, the control signals VBLe, VBLo, BLSLTo, LCHDRV, and PLOAD maintain the same conditions as the bit line precharge period T1. Meanwhile, the control signal BLSLTe is set to the second level (low). This turns off the NMOS transistors HT2 of the page buffers PB0-PB3. In this state, the precharge voltage of the selected bit line BLi_E is maintained according to the state of the memory cell connected to the selected bit line BLi_E (“ON” or “OFF” state), or Be lowered. Assuming that the memory cells in the on state are connected to the selected bit lines BL0_E, BL2_E, and BL3_E, and the memory cells in the off state are connected to the selected bit lines BL0_E, BL2_E, and BL3_E, FIG. As shown, the precharge voltages of the bit lines BL0_E, BL2_E, and BL3_E are dropped to the ground voltage, while the precharge voltage of the bit line BL1_E is maintained.

 When the control signal PLOAD is set to the first (high) level in the latch period T3, the PMOS transistors LT0 of the page buffers PB0 to PB3 are turned off, and the sensing nodes SO0, SO1, SO2, and SO3 are floated (Float). ) Under such conditions, a voltage of about 1.0 V is applied to the control signal BLSLTe. Since the precharge voltage of the bit line BL1_E is maintained, the NMOS transistor HT2 of the page buffer PB1 is cut off. This is because the gate-source voltage (Vgs, Vgs = 1.0V−0.8V = 0.2V) of the NMOS transistor PB2 of the page buffer PB1 is smaller than the threshold voltage 0.7V. Meanwhile, since the precharge voltages of the bit lines BL0_E, BL2_E, and BL3_E are discharged through the ON memory cells, the NMOS transistors HT2 of the other page buffers PB0, PB2, and PB3 are turned on. The voltages at the sensing nodes SO0, SO2, and SO3 are discharged from the power supply voltage to the ground voltage, while the voltage at the sensing node SO1 is maintained.

 Accordingly, the NMOS transistor LT2 connected to the sense node SO1 is turned on, and the NMOS transistor LT2 connected to the sense nodes SO0, SO2, and SO3 is turned off. Accordingly, as shown in FIG. 2A, when the control signal PBLCH is pulsed, the value of the latch LT1 of the page buffers PB0 to PB3 is determined according to the voltage of the sensing nodes SO0 to SO3.

 As described above, the voltage of the sense nodes SO0-SO3 is selectively changed between the power supply voltage and the ground voltage in a floating state. The floating sensing node is affected by a voltage change of an adjacent sensing node due to, for example, a coupling capacitance.

 As shown in FIG. 2B, the coupling capacitances (C0-C2 in FIG. 2B) are adjacent sensing nodes because adjacent sensing nodes (or sensing lines) are positioned to overlap in a direction perpendicular to the bit lines. Exists between the lines.

 When the voltages of the adjacent sensing nodes SO0 and SO2 change from the power supply voltage to the ground voltage, the voltage of the floating sensing node SO1 is lowered to the coupling ratio α of the coupling capacitance by the corresponding voltage. This is called coupling noise or sensing noise.

 If the voltage of the sensing node SO1 in the floating state becomes smaller than the trip voltage of the NMOS transistor LT2 due to the coupling noise, error data is latched in the latch LAT when the control signal PBLCH is pulsed. As a result, the page buffer layout alignment shown in FIG. 2 may cause a read error due to coupling noise between adjacent sensing lines (or nodes).

 It is an object of the present invention to provide a semiconductor device such as a semiconductor memory device including a flash memory that does not stretch a chip area and can reduce or eliminate coupling noise between sensing nodes.

 In accordance with the purpose of the present invention, a semiconductor comprising a high voltage region including a high voltage component, a low voltage region including a low voltage component, and a switch transistor connecting the high voltage region and the low voltage region, such as a low voltage switch transistor. An apparatus, a semiconductor memory device, or a flash memory is provided.

 According to an embodiment of the present invention, in a high voltage region, adjacent sensing lines do not overlap in a direction perpendicular to bit lines in the high voltage region.

 According to an embodiment of the present invention, adjacent sensing lines are sufficiently separated from each other in the high voltage region.

 According to an embodiment of the present invention, adjacent sensing lines do not overlap in the high voltage region.

 According to an embodiment of the present invention, adjacent sensing lines do not face each other in the high voltage region.

 According to an embodiment of the present invention, adjacent sensing lines are aligned stepwise or diagonally in a direction perpendicular to the bit lines in the high voltage region.

 According to an embodiment of the present invention, the low voltage region includes a sense line and does not include the high voltage region.

 Another object of the present invention is to provide a semiconductor device, a semiconductor memory device, or a flash memory including a plurality of page buffers, a page buffer, or a plurality of buffers of a flash memory, or a circuit for the flash memory. Each page buffer includes a bit line select and bias circuit, a sense and latch circuit, and a switch transistor such as a low voltage switch transistor.

 Even if the voltage of the sensing node (or line) is selectively changed from the power supply voltage to the ground voltage in the floating state during the sensing period, the sensing node affects the voltage change of the adjacent sensing node (or line) in the floating state. Not receive.

 Also, since adjacent sensing lines (or nodes) are placed so that they do not overlap (or face each other) in the vertical direction with the bit lines, coupling capacitors between adjacent sensing lines (or nodes) are almost generated. do not do. Therefore, a read error due to coupling noise is not caused.

 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

 FIG. 3 illustrates a page buffer of a flash memory device according to a preferred embodiment of the present invention. Referring to FIG. 3, one or more of the page buffers PB0, PB1, PB2, and PB3 of the present invention include a switch transistor LT4. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

 The switch transistor LT4 of each of the page buffers PB0, PB1, PB2, and PB3 is a low voltage transistor. The low voltage transistor is formed in a low voltage region (or a low voltage circuit region) where the precharge circuit 24 and the sensing and latch circuit 26 of each page buffer PB0, PB1, PB2, and PB3 are formed. In each page buffer, the drain of the switch transistor LT4 is connected to the gate of the NMOS transistor LT2 as a sense transistor through a corresponding sense line SOi (i = 0-3). The source of the switch transistor LT4 is electrically connected to the NMOS transistors HT2 and HT3 through a corresponding bit line-sense line segment BL_SOi. In general, the switch transistor LT4 of the page buffers PB0, PB1, PB2, and PB3 is controlled by a control signal BLSHF.

 In a flash memory device according to an embodiment of the present invention, during a read operation, a power supply voltage is applied to the gate of the NMOS transistor HT2 or HT3 connected to a selected bit line, and another voltage is applied to the read operation. During the other period, the voltage is applied to the gate of the switch transistor LT4.

 In one embodiment, during the read operation, the switch transistor LT4 operates as the NMOS transistor HT2 or HT3 as described above with reference to FIG. That is, the bit line-sense line segment BL_SOi is used as a selected bit line, not as a part of the sense line. Unlike the illustration of FIG. 2B, coupling capacitance (C0-C2 in FIG. 2B) that causes coupling noise between sensing lines adjacent in the direction perpendicular to the bit line hardly occurs.

 Such layout alignment ensures that adjacent sensing lines do not overlap (i.e., face each other or are not stepped or diagonally aligned) and spaced sufficiently apart in a direction perpendicular to the bit line direction. Therefore, the floating sensing line is not affected by the voltage change of the adjacent sensing line (from the power supply voltage to the ground voltage or vice versa).

 4A is a timing diagram for explaining a read operation of the flash memory of FIG. 3, and FIG. 4B is a diagram illustrating an exemplary layout structure of a page buffer of the flash memory device. Reference numbers 30, 34, 38, and 42 indicate high voltage regions (or high voltage circuit regions), and reference numbers 32, 36, 40, and 44 indicate low voltage regions (or low voltage circuit regions). In the page buffers PB0, PB1, PB2, and PB3, the NMOS transistor of the bit line selection and bias circuit 22 is formed in a high voltage region, the switch transistor LT4, the MOS transistor of the precharge circuit 24, and the sensing and latch circuit 26 are low. Formed in the voltage region.

 For example, referring to FIG. 4B, the bit line of the page buffer PB0 and the components of the bias circuit 22 (ie, the high voltage transistor) are disposed in the high voltage region 30, the switch transistor LT4, the precharge circuit 24, and the sensing and Components of the latch circuit 26 (that is, low voltage transistors) are disposed in the low voltage region 32. The bit line selection and bias circuit 22 components (ie, high voltage transistors) of the page buffer PB1 are disposed in the high voltage region 34, the switch transistor LT4, the precharge circuit 24, and the sensing and latch circuit 26 components. (Ie, the low voltage transistor) is disposed in the low voltage region 36. The high voltage transistors of the other page buffers are arranged in the corresponding high voltage regions 38, 42, and the low voltage transistors (including the switch transistor LT4) of the other page buffers are arranged in the corresponding low voltage regions 40, 44. .

 Although not shown in FIGS. 3, 4A and 4B, each of the low voltage regions includes P-type and N-type wells. Low voltage NMOS transistors (eg, LT1, LT2, LT3, LT4, and NMOS transistors of inverters INV0, INV1) are formed in a P-type well, and low voltage transistors (eg, PMOS transistors of LT0, inverters INV0, INV1 are described above). It is formed in an N-type well.

 The high voltage regions 30, 34, 38, 42 are collectively aligned in regions and columns close to the bit lines, and the low voltage regions 32, 36, 40, 44 are regions and column regions away from the bit lines. Are collectively aligned. As described above, the high voltage region and the low voltage region are collectively arranged at the same position for the same purpose.

 As shown in FIG. 4B, the sensing lines SO0, SO1, SO2, SO3 are located locally only in the corresponding low voltage region. In particular, the sense lines SO0-SO3 are locally placed in a corresponding low voltage region so as not to overlap with the bit lines in a vertical direction (that is, not to face each other). Describing again, the sense lines SO0-SO3 are stepped or shaded in a corresponding low voltage region so as not to overlap with the bit lines in the vertical direction.

 The sensing lines SO0-SO3 are the same as other regions, are locally placed in a corresponding low voltage region to have substantially the same length, or have a different length from the other regions. Be placed. Therefore, unlike the illustration of FIG. 2B, coupling capacitance (C0-C2 of FIG. 2B) that causes coupling noise is hardly generated between the sense lines adjacent to the bit line in the vertical direction.

 With this layout alignment, adjacent sensing lines are sufficiently separated from each other, so any floating sensing line will change in voltage (from power supply voltage to ground voltage or vice versa) in the adjacent sensing line. Not affected.

 As described above, even if the voltage of the sensing nodes (or lines) SO0-SO3 is selectively changed from the power supply voltage to the ground voltage in the floating state during the sensing period, the floating sensing node is adjacent to the sensing node. Unaffected by node voltage changes.

 FIG. 4A is a timing diagram for a read operation of a flash memory device according to a preferred embodiment of the present invention described below.

 In the page buffer reset period T0, the control signals VBLe, VBLo, BLSLTe, LCHDRV, PLOAD, and BLSHF transition to the first level (for example, high level), and the ground voltage is supplied to the power line VIRPWR. This connects the bit lines BLi_E, BLi_O, i-0-3 and the latch node N1 to the power line VIRPWR. The bit lines BLi_E, BLi_O, i-0-3 and the latch node N1 are set as the ground voltage. That is, the bit lines BLi_E, BLi_O, i-0-3 and the latch node N1 are reset in the page buffer reset period T0. It is assumed that the even bit line BLi_E of the bit line pair is selected and the odd bit line BLi_O is not selected.

 In the bit line precharge period T1, the control signals VBLe, BLSLTe, LCHDRV, and PLOAD are set to a second level (for example, a low level). On the other hand, the control signals VBLo and BLSLTe are maintained at the first (high) level. In this case, as shown in FIG. 4A, the control signal BLSHF is set to have a voltage of about 1.5V. Under such conditions, the unselected bit line BLi_O is electrically connected to the power line VIRPWR through the corresponding bit line selection and bias circuit 22 NMOS transistor HT1. That is, the non-selected BLi_O discharge voltage is maintained.

 At the same time, the PMOS transistors LT0 of the page buffers PB0, PB1, PB2, and PB3 are turned on, so that the sense nodes SO0 to SO3 are charged to the power supply voltage. Since the high level control signal BLSLTe is sent to the gates of the NMOS transistors HT2 of the page buffers PB0, PB1, PB2, and PB3, the NMOS transistor HT2 is turned on to precharge the bit line. This is because if the control signal BLSHF having a voltage of about 1.5V is applied to the NMOS transistor LT4, the selected bit line BLi_E is preliminarily set to a voltage of 1.5V-Vth (Vth is a threshold voltage of the NMOS transistor). This is because it is charged. That is, the selected bit line BLi_E is precharged to about 0.8V.

 In the sensing period T2, the control signals VBLe, VBLo, BLSLTe, BLSLTo, LCHDRV, and PLOAD maintain the same conditions as the bit line precharge period T1. On the other hand, the control signal BLSHF is set to the low level of the ground voltage. This turns off the NMOS transistor LT4 of the page buffers PB0-PB3. In this state, the precharged voltage of the selected bit line BLi_E is maintained or lowered as it is according to the state (ON or OFF state) of the memory cell connected to the selected bit line BLi_E. As shown in FIG. 4A, the memory cells in the on state are connected to the selected bit lines BL0_E, BL2_E, and BL3_E, and the memory cells in the off state are connected to the selected bit line BL1_E. The precharged voltages of the bit lines BL0_E, BL2_E, and BL3_E are dropped to the ground voltage, while the precharged voltages of the bit lines BL1_E are maintained.

 Since the control signal PLOAD is fixed to the first (high) level in the latch period T3, the PMOS transistors LT0 of the page buffers PB0 to PB3 are turned off, and the sensing nodes SO0, SO1, SO2, and SO3 are floating. Is done. Under such conditions, a voltage of about 1.0 V is applied to the control signal BLSHF. Since the precharged voltage of the bit line BL1_E is maintained, the NMOS transistor LT4 of the page buffer PB1 is short-circuited. This is because the gate-source voltage (Vgs, Vgs = 1.0 V−0.8 V = 0.2 V) of the NMOS transistor LT4 in the page buffer PB1 is lower than the threshold voltage 0.7V.

 On the other hand, since the precharged voltages of the bit lines BL0_E, BL2_E, and BL3_E are discharged through the on-state memory cells, the NMOS transistors LT4 of the other page buffers PB0, PB2, and PB3 are turned on. As shown in FIG. 4A, the voltages of the sensing nodes SO0, S02, and SO3 are discharged from the power supply voltage to the ground voltage, while the voltage of the sensing node SO1 is maintained. This causes the NMOS transistor LT2 to be turned on to be connected to the sense node SO1, and the NMOS transistor LT2 to be connected to the sense nodes SO0, SO2 and SO3 to be turned off. Thereafter, as shown in FIG. 4A, when the control signal PBLCH is pulsed, the value of the latch LAT of the page buffers PB0 to PB3 is determined by the voltage of the sensing nodes SO0 to SO3.

 As described above, even if the voltage of the sensing nodes (or lines) SO0 to SO3 is selectively changed from the power supply voltage to the ground voltage in the floating state during the sensing period, the sensing node is adjacent to the sensing node (in the floating state). It is not affected by the voltage change of the line).

 As shown in FIG. 4B, adjacent sensing lines (or nodes) are placed so that they do not overlap (or face each other) in the vertical direction with the bit lines. Coupling capacitance (C0-C2 in FIG. 2B) hardly occurs. Therefore, a read error due to coupling noise is not caused.

 In the embodiment according to FIG. 3 of the present invention, the layout structure of the page buffer connected to four bit line pairs is not shown in FIGS. 4A and 4B, but the same pattern as the circuit pattern shown in FIGS. 4A and 4B is used. It is clear that it is repeated.

 Further, the control signal BLSHF applied to the gate of the switch transistor LT4 is set to the power supply voltage or the ground voltage by the erase operation. In the program operation, the control signal BLSHF is set equal to or higher than the power supply voltage, and the power supply voltage or the ground voltage is supplied to the bit line according to the data stored in the latch. Also, during the verify operation, the control signal BLSHF is set to be the same as the read operation. As a result, the latch and sensing circuit of each page buffer 26 can be easily modified.

 For example, referring to FIG. 5, in each page buffer, DT is latched and the NMOS transistor LT1 of the sensing circuit 26 is connected to the bit line-sense line BL_SOi instead of the sense line (SOi, i = 0-3). Can be. In this example, the sensing lines of each page buffer PB0-PB3 are placed in the corresponding low voltage region (or low voltage circuit region), so that adjacent sensing lines overlap with the bit lines in the vertical direction ( Or they are arranged so as not to face each other.

 6A and 6B, when the sensing and latch circuit 26 is realized, the voltage of the sensing node SOi is transmitted to the latch LAT via the NMOS transistor LT5. In this case, the latch LAT is controlled by control signals CSEN, CSENB, CLAT, and CLATB to latch the voltage (or data) that has passed through the transistor LT5. In order to obtain such a result, as shown in FIG. 6A, the inverter INV2 is activated by the control signals CSEN and CSENB, and the inverter INV3 is activated by the control signals CLAT and CLATB.

 A desirable embodiment of the present invention is a semiconductor device.

 A preferred embodiment of the present invention is a non-volatile memory.

 A preferred embodiment of the present invention is a flash memory.

 A preferred embodiment of the present invention is a NAND or NOR flash memory.

 Although the preferred embodiment of the present invention has been described as including four bit line pairs and four page buffers, various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

 Although the preferred embodiment of the present invention has been described as including a switch transistor, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the present invention.

 Although preferred embodiments of the present invention have been described according to exemplary voltages, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the present invention. For example, the voltage defining the high voltage region or the high voltage transistor may be any within the range where the voltage is greater than the voltage defining the low voltage region or the low voltage transistor.

 Although the preferred embodiment of the present invention has been described as utilizing high and low logic states, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the present invention. It is.

 Although the preferred embodiment of the present invention has been described as including an NMOS transistor and a PMOS transistor, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the present invention. .

 In the above, the configuration and operation of the circuit according to the present invention have been illustrated on the basis of the above description and the drawings, but this is only described by way of example, and does not depart from the technical idea and scope of the present invention. Of course, various changes and modifications are possible.

1 shows a typical flash memory device such as a NAND flash memory device. FIG. 2 is a timing diagram for explaining a read operation of the flash memory of FIG. 1. 2 shows a page buffer layout of a typical flash memory device such as the device of FIG. 1 illustrates a page buffer of a flash memory device according to a preferred embodiment of the present invention. FIG. 5 is a timing diagram illustrating a read operation of a flash memory device according to an embodiment of the present invention. 2 illustrates a page buffer layout of a flash memory device according to an embodiment of the present invention; 6 shows a page buffer of a flash memory device according to another embodiment of the present invention. 2 illustrates a sensing and latch circuit according to a preferred embodiment of the present invention. FIG. 6B is a timing diagram of the sensing and latch circuit of FIG. 6A according to a preferred embodiment of the present invention.

Explanation of symbols

10 memory cell array 22 bit line selection and bias circuit 24 precharge circuit 26 sensing and latch circuit 60 column decoder PB0, PB1, PB2, PB3 page buffer LT4 switch transistor BL0_E, BL0_O, BL1_E, BL1_O, BL2_E, BL2_O, BL3_E, BL3_O bit Line SO0, SO1, SO2, SO3 sensing line

Claims (39)

A first page buffer including a first bit line pair;
A second page buffer including a second bit line pair;
Each of the first and second page buffers is
A high voltage circuit for selecting one of the bit line pairs;
A low voltage circuit for sensing cell data via the bit line;
A switch transistor coupled to the sense line;
The flash memory according to claim 1, wherein the sensing lines of the first and second page buffers are stepped so as not to overlap with the bit lines.  The flash memory of claim 1, wherein each low voltage circuit further comprises a latch for latching data and a sense transistor.  2. The flash memory of claim 1, wherein each high voltage circuit is located closer to the corresponding bit line pair than each low voltage circuit.  3. The flash memory according to claim 2, wherein each low voltage circuit includes first and second well regions arranged in a column direction when each low voltage circuit is disposed in a low voltage region.  The flash memory of claim 4, wherein the sensing line of the first page buffer is located in the first well region, and the sensing line of the second page buffer is located in the second region.  The first well region includes a first P-type well and a first N-type well in which a transistor of a low voltage circuit of the first page buffer is formed, and the second well region is a transistor of a low voltage circuit of the second page buffer. The flash memory according to claim 5, further comprising a second P-type well and a second N-type well in which are formed.  2. The flash memory according to claim 1, wherein the switch transistors of the first and second page buffers are low voltage switch transistors.  8. The switch transistors of the first and second page buffers have a current path between the high voltage circuit and the sensing line, and a control signal is applied to the gate of the switch transistor. Flash memory as described in.  The flash memory of claim 7, wherein the control signal has different voltages in a bit line precharge period, a sensing period, and a latch period.  12. The flash memory according to claim 11, wherein each low voltage circuit includes a precharge transistor controlled by a control signal. Including a number of page buffers containing each bitline pair;
Each page buffer
A bit line selection and bias circuit including a high voltage transistor for selecting one of the bit line pairs;
A sensing and latching circuit including a low voltage transistor for sensing cell data via the bit line;
At least one of the low voltage transistors and a low voltage switch transistor connecting at least one of the high voltage transistors and connected to a sense line;
The flash memory according to claim 1, wherein the sensing lines of the adjacent page buffers are arranged in a staircase pattern so as not to overlap each bit line pair in a vertical direction.  12. The sensing and latch circuit, and each of the low voltage transistors are located in a low voltage region, and the low voltage region includes first and second well regions arranged in a column direction. Flash memory.  The sensing line of the first page buffer of the plurality of page buffers is located in the first well region, and the sensing line of the second page buffer of the plurality of page buffers is located in the second well region. The flash memory according to claim 11.  The first well region includes a first P type well and a first N type well in which a transistor of the low voltage circuit of the first page buffer is formed, and the second well region is a transistor of the low voltage circuit of the second page buffer. 14. The flash memory according to claim 13, further comprising a second P-type well and a second N-type well in which is formed.  The flash memory of claim 11, wherein each of the sense and latch circuits includes a latch and a sense transistor for latching data. A first page buffer including a first bit line pair;
A second page buffer including a second bit line pair;
Each of the first and second page buffers is
A first high voltage bit line select transistor circuit coupled to the first bit line-sense line segment;
A second high voltage bit line select transistor circuit coupled to the second bit line-sense line segment;
A low voltage switch transistor coupled to the sense line;
The first bit line-sense line segment and the second bit line-sense line segment are coupled to the corresponding low voltage switch transistor;
The flash memory according to claim 1, wherein the sensing lines of adjacent page buffers are arranged in a stepped manner so as not to overlap each bit line pair in a vertical direction.  The method of claim 16, wherein each of the first high voltage bit line selection transistor circuit and the second high voltage bit line selection transistor is closer to the corresponding bit line pair than the respective low voltage switch transistor. The flash memory described.  17. The flash memory of claim 16, wherein each of the low voltage switch transistors is located in a low voltage region, and the low voltage region includes first and second well regions arranged in a column direction.  The flash memory of claim 18, wherein the sensing line of the first page buffer is located in the first well region, and a sensing line of the second page buffer is located in the second well region.  The first well region includes a first P type well and a first N type well in which a transistor of the low voltage circuit of the first page buffer is formed, and the second well region is a transistor of the low voltage circuit of the second page buffer. The flash memory according to claim 19, comprising a second P-type well and a second N-type well in which are formed.  The flash memory of claim 16, wherein each of the first and second page buffers includes a low voltage precharge transistor for precharging a sense node.  The flash memory of claim 16, wherein each of the first and second page buffers includes a low voltage drive transistor corresponding to a bit line-sense line segment.  The flash memory of claim 16, wherein each of the first and second page buffers includes a low voltage drive transistor corresponding to a sense line. A memory cell array including a plurality of cell strings electrically connected to the corresponding bit line, in which two adjacent bit lines form a bit line pair between the corresponding bit lines;
A first page buffer coupled to the first bit line pair;
A second page buffer coupled to the second bit line pair;
Each of the first and second page buffers is
A bit line selection and bias circuit including a high voltage component located in a high voltage region, selecting one bit line of a corresponding bit line pair to connect the selected bit line to a sense line;
A sensing and latch circuit that senses cell data via the bit line pair and includes a low voltage component located in a low voltage region coupled to the bit line pair;
A switch transistor connected to the bit line selection and bias circuit and the sense and latch circuit and connected to the sense line;
A column gate circuit for selecting at least one of the first and second page buffers and connecting the selected page buffer to a data bus;
The flash memory according to claim 1, wherein the adjacent sensing lines of the first and second page buffers are arranged in a staircase pattern so as not to overlap with the bit lines.  The flash memory according to claim 24, wherein the semiconductor device is a flash memory. A memory cell array including a plurality of cell strings electrically connected to the corresponding bit line, in which two adjacent bit lines form a bit line pair between the corresponding bit lines;
Including a first page buffer and a second page buffer coupled to a bit line pair;
Each of the first and second page buffers is
A high voltage circuit for selecting one bit line of a corresponding bit line pair and connecting the selected bit line to a sense line;
A low voltage connected to the bit line pair by sensing a cell data through the bit line pair and including a latch circuit, a first switch transistor for connecting the selected bit line to the sense line, and a precharge transistor; Including the circuit,
Adjacent sensing lines of the first and second page buffers are arranged in a staircase pattern so as not to overlap with the bit lines,
A control signal is applied to the gate of the first switch transistor,
The flash memory according to claim 1, wherein the precharge transistor is connected to the sensing line so that the sensing line is precharged to a predetermined voltage level.  27. The flash memory of claim 26, wherein the control signal has different voltages in a bit line precharge period, a sensing period, and a latch period.  27. The flash memory of claim 26, wherein the low voltage circuit further includes a second switch transistor.  29. The flash memory of claim 28, wherein the second switch transistor connects the sensing line to a node of the latch circuit.  29. The flash memory of claim 28, wherein the second switch transistor connects the sensing line to a node of the latch circuit.  29. The flash memory of claim 28, wherein the second switch transistor is turned on during a page buffer reset period. A memory cell array including a plurality of cell strings electrically connected to the corresponding bit line, in which two adjacent bit lines form a bit line pair between the corresponding bit lines;
A number of page buffers coupled to corresponding bit line pairs;
Each of the multiple page buffers is
A bit line selection and bias circuit that selects one bit line of a corresponding bit line pair and connects the selected bit line to a sense line;
Sensing and latching circuit for sensing cell data via the bit line pair, coupled to the bit line pair and including at least one latch unit;
A first switch transistor connecting the bit line selection and bias circuit and the sense line;
A second switch transistor connecting the sense line to the node of the latch unit;
And a precharge transistor connected to the sense line to precharge the sense line to a predetermined voltage level.  The flash memory of claim 32, wherein the first switch transistor is controlled by at least three voltage levels.  The flash memory of claim 32, wherein the second switch transistor is turned on during a page buffer reset period. A memory cell array including a plurality of cell strings electrically connected to the corresponding bit line, in which two adjacent bit lines form a bit line pair between the corresponding bit lines;
A number of page buffers coupled to corresponding bit line pairs;
Each of the multiple page buffers is
A bit line selection and bias circuit that selects one bit line of a corresponding bit line pair and connects the selected bit line to a sense line;
Sensing and latching circuit for sensing cell data via the bit line pair and including at least one latch unit coupled to the bit line pair;
A first switch transistor connecting the bit line selection and bias circuit and the sense line;
A second switch transistor coupling the bit line select and bias circuit to the latch unit;
And a precharge transistor connected to the sense line to precharge the sense line to a predetermined voltage level.  36. The flash memory of claim 35, wherein the first switch transistor is controlled by at least three voltage levels.  36. The flash memory of claim 35, wherein the second switch transistor is turned on during a page buffer reset period. In the page buffer of flash memory,
The page buffer is
A bit line selection and bias circuit that selects one bit line of a corresponding bit line pair and connects the selected bit line to a sense line;
A first switch transistor connecting the bit line selection and bias circuit and the sense line;
Sensing and latching circuit for sensing cell data via the bit line pair, coupled to the bit line pair and including at least one latch unit;
A second switch transistor coupling the bit line select and bias circuit to the latch unit;
And a precharge transistor connected to the sense line to precharge the sense line to a predetermined voltage level. In a circuit for a flash memory, the circuit is
A first switch transistor coupled to the sense node;
At least one latch unit for latching cell data;
A second switch transistor connecting the first switch transistor to a node of the at least one latch unit;
And a precharge transistor connected to the sense line to precharge the sense line to a predetermined voltage level.

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