CN100567739C

CN100567739C - A kind of proportional amplifier that is used for the compound control of variable displacement pump

Info

Publication number: CN100567739C
Application number: CNB2008100363688A
Authority: CN
Inventors: 邢科礼; 姚磊; 金侠杰
Original assignee: University of Shanghai for Science and Technology
Current assignee: University of Shanghai for Science and Technology
Priority date: 2008-04-21
Filing date: 2008-04-21
Publication date: 2009-12-09
Anticipated expiration: 2028-04-21
Also published as: CN101265901A

Abstract

The present invention relates to a kind of proportional amplifier that is used for the compound control of variable displacement pump, comprise a variable displacement pump, there is a signal conditioning circuit that has setting pressure signal input, setting flux signal inlet opening and setting power signal input to be connected a FPGA unit with an A/D converter, the serial port circuit in described FPGA unit connects a upper-position unit, a FLASH connects described FPGA unit, the delivery outlet of described FPGA unit connects described variable displacement pump through a power driving circuit again through a D/A converter; Described variable displacement pump connects three sensors respectively, and the delivery outlet of described three sensors is connected to described FPGA unit through another signal conditioning circuit and another A/D converter; Because the present invention is integrated in functions such as communication, control and realizes in the programmable system on chip, adopt flush bonding processor Nios II to finish software control algorithm, make it simple in structure, can reduce development cost.

Description

A kind of proportional amplifier that is used for the compound control of variable displacement pump

Technical field

The present invention relates to a kind of proportional amplifier that is used for the compound control of variable displacement pump, be applicable to the compound control system of variable displacement pump.

Background technique

Oil hydraulic pump is converted to the hydraulic pressure energy with mechanical energy, is the power source of hydraulic system.In electric-hydraulic proportion control, oil hydraulic pump is a variable displacement pump of realizing different control functions.The compound control pump of electric-hydraulic proportion can better adapt to the complex working condition of equipment, simplifies hydraulic system.The proportional amplifier that is used for the compound control of variable displacement pump is mainly finished the desired various control functions of compound control pump.

At present, the permanent power and variable pump of domestic production adopts the complex spring control type mostly, and its degree of regulation is very low, and is difficult to obtain the power regulating range of broad; The external main compound control pump of electric-hydraulic proportion that adopts electricity feedback and digital control technology to combine, giving proportional amplifier the control function finishes, pressure is given in detection, displacement transducer is finished, and basic pump still the basic pump with common hand adjustment variable displacement pump is identical, its common problem be design complicated, cost an arm and a leg.

Summary of the invention

The present invention is directed to the defective that exists in the prior art, propose a kind of proportional amplifier that is used for the compound control of variable displacement pump, it is simple in structure, can lower development cost.

For achieving the above object, the present invention adopts following technical proposals: a kind of proportional amplifier that is used for the compound control of variable displacement pump, comprise a variable displacement pump, it is characterized in that: have one to have the setting pressure signal input, the signal conditioning circuit of setting flux signal inlet opening and setting power signal input is connected a FPGA unit with an A/D converter, the serial port circuit in described FPGA unit connects a upper-position unit, a FLASH connects described FPGA unit, the delivery outlet of described FPGA unit connects described variable displacement pump through a power driving circuit again through a D/A converter; Described variable displacement pump connects three sensors respectively, and the delivery outlet of described three sensors is connected to described FPGA unit through another signal conditioning circuit and another A/D converter.

Described two signal conditioning circuits constitute by the adder circuit of OP-07 operational amplifier U1 and some resistance composition, input signal is handled, to adapt to the range requirement of A/D chip, Placement is: V-in is an input voltage signal, and output terminal is V-out; Described two A/D converters all select for use AD1812 modulus conversion chip U4 to realize, convert the analog amount of input to digital quantity, Placement is: signal V-out inserts 2 pin of U4 through resistance R 13, model provides voltage for the U5 of TLC431 for U4,16 terminations of U4+5V power supply,

8,9,10,11,12,13,14, the 15 output digital quantities of U4, the corresponding I/O mouth of access fpga chip; Described FPGA unit selection fpga chip; Described serial port circuit is made up of MAX3232 electrical level transferring chip U3 and some devices, connect upper-position unit, Placement is: 1 of U3,3 ends connect through

capacitor C

3,4,5 ends connect through

capacitor C

4,11 ends are through resistance R 10, diode DS2 connects+3.3V, and receive the I/O mouth of fpga chip, 12 ends are through resistance R 9, diode DS1 connects+3.3V, and receive the I/O mouth of fpga chip, 10 ends are through resistance R 11, diode DS3 connects+3.3V, and receives the I/O mouth of fpga chip, and 9 ends are through resistance R 12, diode DS4 connection+3.3V, and connect the I/O mouth of fpga chip, 7 ends and 14 terminations are gone into JP3, and 13 ends and 5 terminations are gone into JP4, JP3, JP4 inserts 2 ends and 3 ends of JP5,2 ends are through

capacitor C

6,6 ends are through

capacitor C

7,15 end ground connection, 16 terminations+3.3V level; Described FLASH selects for use chip AMD29LV160DB to realize, the storage data processed result; Described D/A converter selects for use DAC0808 analog-digital chip U5 to realize, convert the digital quantity of output to analog amount, Placement is: 13 terminations of U5+12V, 3 terminations-12V, 5, the corresponding output end of 6,7,8,9,10,11,12 termination fpga chips, 14 ends connect reference voltage by R15, and 15 ends are by R16 ground connection, 16 ends connect-12V by

capacitor C

10, and 4 ends are through a subtractor output signal end V-o who is made up of U6; Described power driving circuit selects for use LMD18200 direct current generator driving chip U2 to realize, output signal is carried out power amplification, and Placement is: V-o inserts 5 ends, and 3,4,8 respectively by resistance R 5, R6, R7 ground connection, 1,2,10,11 external socket JP, JP connects variable displacement pump; Described upper-position unit is a PC; Described three sensors are respectively a pressure transmitter and two displacement transducers; Described variable displacement pump is plunger variable pump or blade variable displacement pump.

In above-mentioned fpga chip, comprise main control module, communication interface, communication interface control module and two-port RAM, Placement is: input signal through A/D converter after the main control module connects D/A converter, two-port RAM connects main control module and communication interface control module respectively, the communication interface control module connects communication interface, and communication interface connects serial port circuit.Above-mentioned main control module and communication interface control module are made up of two flush bonding processor Nios II in the above-mentioned fpga chip respectively, described Nios II is the soft nuclear of a kind of 32-bit microprocessor, need configuration Avalon T tristate bus line bridge, two-port RAM and some PIO, SPI, Placement is: Nios II is by Avalon on-chip bus and ram in slice, ROM in the sheet, clock, house dog, two-port RAM, Avalon T tristate bus line bridge, PIO, SPI, UART links to each other, UART connects above-mentioned upper-position unit, SPI connects above-mentioned A/D converter, PIO connects above-mentioned D/A converter, Avalon T tristate bus line bridge joint Avalon tristate bus line.

Compared with prior art, beneficial effect of the present invention is embodied in: the present invention is integrated in functions such as communication, control and realizes in the programmable system on chip, adopt flush bonding processor Nios II to finish software control algorithm, make it simple in structure, can reduce development cost.

Description of drawings

Fig. 1 is the general structure of the embodiment of the invention;

Fig. 2 is the signal conditioning circuit schematic diagram of Fig. 1 example;

Fig. 3 is the A/D converter circuit theory diagrams of Fig. 1 example;

Fig. 4 is the serial port circuit schematic diagram of Fig. 1 example;

Fig. 5 is the D/A converter circuit theory diagrams of Fig. 1 example;

Fig. 6 is the power driving circuit schematic diagram of Fig. 1 example;

Fig. 7 is the fpga chip functional block diagram and the interface specification of Fig. 1 example;

Fig. 8 is the flush bonding processor Nios II structural drawing of Fig. 1 example;

Fig. 9 is the main program flow chart of Fig. 1 example.

Below pass through embodiment, and the invention will be further described in conjunction with the accompanying drawings.

Embodiment

Details are as follows in conjunction with the accompanying drawings for a preferred embodiment of the present invention:

Referring to Fig. 1, the controlling object of present embodiment is a variable displacement pump, and upper-position unit 9,

sensor

13,14,15 and variable displacement pump 12 do not belong in the present invention among the figure.A kind of proportional amplifier that is used for the compound control of variable displacement pump, comprise a variable displacement pump 12, it is characterized in that: have a signal conditioning circuit 4 that has setting pressure signal input 1, setting flux signal inlet opening 2 and setting power signal input 3 to be connected a FPGA unit 6 with an A/D converter 5, described FPGA unit 6 connects a upper-position unit 9 through a serial port circuit 8, a FLASH 7 connects described FPGA unit 6, the delivery outlet of described FPGA unit 6 connects described variable displacement pump 12 through a power driving circuit 11 again through a D/A converter 10; Described variable displacement pump 12 connects three

sensors

13,14,15 respectively, and the delivery outlet of described three

sensors

13,14,15 is connected to described FPGA unit 6 through another signal conditioning circuit 16 and another A/D converter 17.Above-mentioned setting input signal can be produced by potentiometer, program controller or computer, can accept the variable displacement pump outlet pressure signal by the pressure transmitter detection, compares with the pressure given signal, constitutes the pressure control to compound control pump; Can accept variable oil hydraulic cylinder discharge capacity signal, compare, constitute flow control compound control pump with the given signal of flow by the displacement transducer detection; Can accept spool travel signal, compare, constitute position regulation, stablize the ratio current of electromagnet spool with front computing output signal by the displacement transducer detection; Also can realize power control to compound control pump.

Described two

signal conditioning circuits

4,16 are formed by OP-07 operational amplifier U1 and some resistance, input signal is handled, and to adapt to the range requirement of A/D chip, V-in is an input voltage signal, output terminal is V-out, and its circuit theory diagrams as shown in Figure 2.

Described two A/

D converters

5,17 all select for use AD1812 modulus conversion chip U4 to realize, convert the analog amount of input to digital quantity, signal V-out inserts 2 pin of U4 through resistance R 13, model provides voltage for the U5 of TLC431 for U4,16 terminations of U4+5V power supply,

8,9,10,11,12,13,14, the 15 output digital quantities of U4, the corresponding I/O mouth of access fpga chip, its circuit diagram is as shown in Figure 3.

Described serial port circuit 8 is made up of MAX3232 electrical level transferring chip U3 and some devices, connect upper-position unit 9, Placement is: 11 ends of U3 are through resistance R 10, diode DS2 connects+3.3V, and receive the I/O mouth of fpga chip, 12 ends are through resistance R 9, diode DS1 connects+3.3V, and receive the I/O mouth of fpga chip, 10 ends are through resistance R 11, diode DS3 connects+3.3V, and receive the I/O mouth of fpga chip, 9 ends are through resistance R 12, diode DS4 connection+3.3V, and connect the I/O mouth of fpga chip, and 7 ends and 14 terminations are gone into JP3, and 13 ends and 5 terminations are gone into JP4, JP3, JP4 inserts 2 ends and 3 ends of JP5,2 ends are through

capacitor C

6,6 ends are through

capacitor C

7,15 end ground connection, 16 terminations+3.3V level, its circuit diagram is as shown in Figure 4.

Described D/A converter 10 selects for use DAC0808 analog-digital chip U5 to realize, convert the digital quantity of output to analog amount, Placement is: the corresponding output end of 5,6,7,8,9,10,11, the 12 termination fpga chips of U5,14 ends connect reference voltage by R15,15 ends are by R16 ground connection, 16 ends connect-12V by

capacitor C

10, and 4 ends are through a subtractor output signal end V-o who is made up of U6, and its circuit diagram as shown in Figure 5.

Described power driving circuit 11 selects for use LMD18200 direct current generator driving chip U2 to realize, output signal is carried out power amplification, and V-o connects 5 ends, 3,4,8 respectively by resistance R 5, R6, R7 ground connection, 1,2,10,11 external socket JP, JP connects variable displacement pump, and its circuit diagram is as shown in Figure 6.

Described upper-position unit 9 is a PC; Described three

sensors

13,14,15 are respectively a pressure transmitter and two displacement transducers; Described variable displacement pump 12 is plunger variable pump or blade variable displacement pump.

Referring to Fig. 7, in above-mentioned fpga chip, comprise main control module 18, communication interface 20, communication interface control module 21 and two-port RAM 19, when described main control module 18 arrives at each control cycle, obtain the current state information of above-mentioned variable displacement pump 12 by the

sensor

13,14,15, adopt suitable control algorithm compute control amount, export control signals by above-mentioned power driving circuit 11, and the status information of above-mentioned variable displacement pump 12 is write above-mentioned two-port RAM 19; The flush bonding processor Nios II that constitutes communication interface control module 21 is two different processors with the flush bonding processor Nios II that constitutes main control module 18, these two Nios II kernels are integrated in the Nios II system, by above-mentioned two-port RAM 19 Data transmission.

Referring to Fig. 8, the control core Nios II of present embodiment is a user configurable 32 the general RISC flush bonding processors of altera corp at its FPGA exploitation, as the central processing unit (CPU) of realizing control, one of characteristics are exactly the Avalon bus, it is a kind of simple bus protocol that connects on-chip processor and other IP modules, has stipulated master unit and from port that connects between the parts and the sequential of communicating by letter.The Avalon bus is a kind of simple relatively bus structure, is mainly used in connecting sheet inner treater and peripheral hardware, to constitute programing system SOPC on the sheet.In the Quatus II development platform that altera corp provides, carry out the system design of FPGA inside, in SOPC Builder, for processor Nios II add-on system clock, as the cycle timer and the WatchDog Timer of described processor; Design a universal asynchronous serial interface UART, realize data interaction with above-mentioned upper-position unit 9; Some PIO, SPI are set, and wherein PIO is used to send the D/A data and controls the D/A chip selection signal, and SPI gathers

input setting signal

1,2,3 and the

sensor

13,14,15 testing signals; Add outside FLASH interface in addition, software program is stored in after compiling is finished among the outside FLASH, and after FPGA powered on, software program will be by operation in the above-mentioned two-port RAM 19 of videoing among the described FLASH 7.After the customization interpolation is finished, the automatic allocation base of system tool address and interruption and generation system module.In generative process, SOPC Builder is created as a symbol with Nios II system module to be added in the BDF document, and it is interconnected with logic to connect up.After finishing these, project file is compiled.After the compiling, Quartus II generates one or more programming files, and is able to programme or dispose a device, downloads among the above-mentioned FLASH 7, will generate a circuit that comprise soft nuclear of Nios II and relevant Peripheral Interface in that above-mentioned FPGA is inner.

The task of Nios II is exactly in the control cycle of regulation in the above-mentioned main control module 18, obtain control task and the Control Parameter that upper-position unit 9 sends by communication interface 20, accept

sensor

13,14, the 15 detected feedback signals that variable displacement pump 12 connects, the control signal that obtains exporting after suitable algorithm in CPU calculates, realize the compound control of above-mentioned variable displacement pump 12, carry out the work such as editor, debugging, compiling and download of software in the software IDE Nios of altera corp II IDE, its main program flow chart as shown in Figure 9.

Claims

1. proportional amplifier that is used for the compound control of variable displacement pump, comprise a variable displacement pump (12), it is characterized in that: have one to have setting pressure signal input (1), the signal conditioning circuit (4) of setting flux signal inlet opening (2) and setting power signal input (3) is connected a FPGA unit (6) with an A/D converter (5), described FPGA unit (6) connects a upper-position unit (9) through a serial port circuit (8), a FLASH (7) connects described FPGA unit (6), the delivery outlet of described FPGA unit (6) connects described variable displacement pump (12) through a power driving circuit (11) again through a D/A converter (10); Described variable displacement pump (12) connects three sensors (13,14,15) respectively, and the delivery outlet of described three sensors (13,14,15) is connected to described FPGA unit (6) through another signal conditioning circuit (16) and another A/D converter (17).

2. a kind of proportional amplifier that is used for the compound control of variable displacement pump according to claim 1, it is characterized in that: described two signal conditioning circuits (4,16) constitute by the adder circuit of OP-07 operational amplifier U1 and some resistance composition, input signal is handled, to adapt to the range requirement of A/D chip, Placement is: V-in is an input voltage signal, and output terminal is V-out; Described two A/D converters (5,17) all select for use AD1812 modulus conversion chip U4 to realize, convert the analog amount of input to digital quantity, Placement is: signal V-out inserts 2 pin of U4 through resistance R 13, model provides voltage for the U5 of TLC431 for U4,16 terminations of U4+5V power supply, pin 8,9,10,11,12,13,14, the 15 output digital quantities of U4, the corresponding I/O mouth of access fpga chip; Fpga chip is chosen in described FPGA unit (6); Described serial port circuit (8) is made up of MAX3232 electrical level transferring chip U3 and some devices, connect upper-position unit (9), Placement is: 1 of U3,3 ends connect through capacitor C 3,4,5 ends connect through capacitor C 4,11 ends are through resistance R 10, diode DS2 connects+3.3V, and receive the I/O mouth of fpga chip, 12 ends are through resistance R 9, diode DS1 connects+3.3V, and receive the I/O mouth of fpga chip, 10 ends are through resistance R 11, diode DS3 connects+3.3V, and receives the I/O mouth of fpga chip, and 9 ends are through resistance R 12, diode DS4 connection+3.3V, and connect the I/O mouth of fpga chip, 7 ends and 14 terminations are gone into JP3, and 13 ends and 5 terminations are gone into JP4, JP3, JP4 inserts 2 ends and 3 ends of JP5,2 ends are through capacitor C 6,6 ends are through capacitor C 7,15 end ground connection, 16 terminations+3.3V level; Described FLASH (7) selects for use chip AMD29LV160DB to realize, the storage data processed result; Described D/A converter (10) selects for use DAC0808 analog-digital chip U5 to realize, convert the digital quantity of output to analog amount, Placement is: 13 terminations of U5+12V, 3 terminations-12V, 5, the corresponding output end of 6,7,8,9,10,11,12 termination fpga chips, 14 ends connect reference voltage by R15, and 15 ends are by R16 ground connection, 16 ends connect-12V by capacitor C 10, and 4 ends are through a subtractor output signal end V-o who is made up of U6; Described power driving circuit (11) selects for use LMD18200 direct current generator driving chip U2 to realize, output signal is carried out power amplification, and Placement is: V-o connects 5 ends, and 3,4,8 respectively by resistance R 5, R6, R7 ground connection, 1,2,10,11 external socket JP, JP connects variable displacement pump; Described upper-position unit (9) is a PC; Described three sensors (13,14,15) are respectively a pressure transmitter and two displacement transducers; Described variable displacement pump (12) is plunger variable pump or blade variable displacement pump.

3. a kind of proportional amplifier that is used for the compound control of variable displacement pump according to claim 2, it is characterized in that: in above-mentioned fpga chip, comprise main control module (18), communication interface (20), communication interface control module (21) and two-port RAM (19), Placement is: input signal is through A/D converter (5,17) after main control module (18) connects D/A converter (10), two-port RAM (19) connects main control module (18) and communication interface control module (21) respectively, communication interface control module (21) connects communication interface (20), and communication interface (20) connects serial port circuit (8).

4. a kind of proportional amplifier that is used for the compound control of variable displacement pump according to claim 3, it is characterized in that: above-mentioned main control module (18) and communication interface control module (21) are made up of two flush bonding processor NiosII in the above-mentioned fpga chip respectively, described Nios II is the soft nuclear of a kind of 32-bit microprocessor, need configuration Avalon T tristate bus line bridge, two-port RAM and some PIO, SPI, Placement is: NiosII is by Avalon on-chip bus and ram in slice, ROM in the sheet, clock, house dog, two-port RAM, Avalon T tristate bus line bridge, PIO, SPI, UART links to each other, UART connects above-mentioned upper-position unit (9), SPI connects above-mentioned A/D converter (5,17), PIO connects above-mentioned D/A converter (10), Avalon T tristate bus line bridge joint Avalon tristate bus line.