CN100563748C - A kind of high-purity implanting planar array microelectrode and manufacture method - Google Patents
A kind of high-purity implanting planar array microelectrode and manufacture method Download PDFInfo
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- CN100563748C CN100563748C CNB2007100408307A CN200710040830A CN100563748C CN 100563748 C CN100563748 C CN 100563748C CN B2007100408307 A CNB2007100408307 A CN B2007100408307A CN 200710040830 A CN200710040830 A CN 200710040830A CN 100563748 C CN100563748 C CN 100563748C
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Abstract
The invention discloses a kind of high-purity implanting planar array microelectrode and preparation method thereof, it is characterized in that described array microelectrode utilizes polymer as insulating layer material, design by the interlayer wiring, with electrode stimulating site or record site and its connection arrangement of conductors between different insulating barriers, and on isolated insulation layer, make through-hole structure, form metal connecting structure by electroplating technology in through hole, realizing being positioned at the isolated insulation layer upper/lower electrode stimulates site or record site to be connected the connection of lead with it; Wherein behind the electroplating technology, adopt the method for chemical polishing that upper surface is polished, guarantee plated metal post and good being electrically connected of upper strata splash-proofing sputtering metal layer.Manufacture method provided by the invention can be made on unit are than the more highdensity array microelectrode of conventional monolayer wires design, realizes implanted array microelectrode more high selectivity stimulation or record.
Description
Technical field
The present invention relates to a kind of manufacture method of high-purity implanting planar array microelectrode, can be applicable to fields such as neuropathy treatment, neurobiology basic research, belong to the implantation micro-electrode having field.
Background technology
Neural engineering system is that such as brain-computer interface, problems such as nerve prosthesis receive increasing concern when previous very active and develop research field rapidly.In neural engineering system, the part of basic key is nerve-electrical interface, i.e. electrode.Different according to effective object and application target, people have researched and developed the implantation micro-electrode having of various ways successively, comprise four kinds of hoop shape microelectrode, aciculiform array microelectrode, planar array microelectrode and sieve shape microelectrodes.Wherein the planar array microelectrode is a kind of microelectrode form of difficulty of processing minimum, and application is very widely being arranged aspect neurobiology basic research and the neural rehabilitation.Because neural complexity and neurocyte number are numerous and the dense distribution of regional area, therefore the density of implanted plane microelectrode becomes influences significant effects factor of its performance, the quality of electricity irritation and the nerve signal record that directly affects the nerves.Such as, implant the patient that the retina prosthese carries out recovery of vision for adopting, want to recover vision preferably, a very important problem is exactly that the planar array microelectrode that is used as the retina prosthese has good selectivity, that is to say to have higher electrode stimulating dot density.
Usually adopt at present the planar array microelectrode of (metal level is clipped between the polymer) of polymeric material sandwich form in the world.Its processing technique is simple, and cost is low, and fabrication cycle is short, the process conditions maturation.But the problem of its existence is, when making high-density microelectrode array, electrode area will be at double increase, chief reason is the increase of counting out along with the microelectrode array internal stimulus, the number of conductors that connects stimulation point constantly rises, how on the basis that keeps original electrode area, increase the density of microelectrode array, wiring problem becomes a difficult point.Someone proposes by making the method control electrode that organic field-effect tube (organicfield effect transistor) adopts matrix addressing, the microelectrode matrix that M * N is distributed only needs M+N bar lead rather than M * N bar lead just can control [Dara Feili, et al. " Flexible organic field effect transistors for biomedical microimplants usingpolyimide and parylene C as substrate and insulator layers ", J.Micromech.Microeng., 2006,16:1555-1561], though this method has reduced the number of connecting line, but complex manufacturing technology realizes comparatively difficulty.
Summary of the invention
The purpose of this invention is to provide a kind of technology high-purity implanting planar array microelectrode simple, with low cost and preparation method thereof, make the metal level syndeton that is connected the insulating barrier upper and lower surface by through-hole structure, electroplating technology and chemical polishing technology, realize that electrode stimulating site or record site are connected the interlayer distribution of lead with it, improve planar array microelectrode stimulation point or measuring point density, improve the selectivity that the planar array microelectrode stimulates or writes down.
A kind of high-purity implanting planar array microelectrode provided by the invention is characterized in that: described implantation micro-electrode having comprises one deck electrode stimulating site or record site layer, one deck through hole articulamentum and is connected conductor layer with one deck at least; Electrode stimulating site or record site layer are connected with it on different aspects that conductor layer is in one or more layers isolated insulation layer respectively; Electrode stimulating site or record site layer are connected conductor layer and connect by the via metal microtrabeculae structure on the isolated insulation layer with it.Wherein via metal microtrabeculae syndeton is made by electroplating technology, and the material surface after utilizing the chemical polishing PROCESS FOR TREATMENT to electroplate, make the upper surface that connects the metal microtrabeculae in the same plane, assurance plated metal post and good being electrically connected of upper strata splash-proofing sputtering metal layer with the upper surface of isolated insulation layer.
Planar array microelectrode of the present invention utilizes polymer as insulating layer material, design by the interlayer wiring, with electrode stimulating site or record site and its connection arrangement of conductors between different insulating barriers, and on isolated insulation layer, make through-hole structure, form metal connecting structure by electroplating technology in through hole, realizing being positioned at the isolated insulation layer upper/lower electrode stimulates site or record site to be connected the connection of lead with it; Wherein behind the electroplating technology, adopt the method for chemical polishing that upper surface is polished, make plated metal post and good being electrically connected of upper strata splash-proofing sputtering metal layer.
Particularly, at first on the silicon chip that evaporates preparation aluminum film by sputter with peel off (Lift-off) technology and make the electrode stimulating site or write down the site metal level, electrode stimulating site or record site metal layer material can be gold, platinum or iridium, and metal layer thickness can be between 100 dusts to 100 micron; Make isolated insulation layer by spin coating or vapour deposition then, the isolated insulation layer material can be silicon dioxide, silicon nitride, polyimides or Parylene, and thickness of insulating layer can be between 100 dusts to 50 micron; And on the insulating barrier of electrode stimulating site or record site, make through hole by photoetching and reactive ion etching, the area of via metal microtrabeculae should be less than electrode stimulating site or record site area; By electroplating at insulating barrier through hole growth making metal column, exceed the insulating barrier upper surface until the metal column upper surface, electroplating metal material can be nickel, copper or gold; Utilize the material surface after the chemical polishing PROCESS FOR TREATMENT is electroplated, make metal column upper surface and insulating barrier upper surface be in same plane; Make electrode by sputter and Lift-off technology and is connected the lead metal level, the connection metal layer material can be titanium, chromium, copper, aluminum, gold or platinum, and metal layer thickness can be between 100 dusts to 50 micron; Afterwards, make upper insulation layer by spin coating or vapour deposition, and by photoetching and the reactive ion etching exposure solder joint of windowing, insulating layer material can be silicon dioxide, silicon nitride, polyimides or Parylene, thickness can be between 100 dusts to 50 micron; At last, discharge electrode by acid corrosion or electrochemical corrosion sacrifice layer, sacrificial layer material can be aluminum, copper or silicon dioxide.
The manufacture method of high-purity implanting planar array microelectrode provided by the invention is compared with single-layer metal layer method for making its electrode commonly used at present, can on unit are, make more highdensity array microelectrode, realize implanted array microelectrode more high selectivity stimulation or record, improve the stimulation or the record effect of electrode.And whole processing technology is simple, ripe, is easy to the batch process of high-purity implanting planar array microelectrode.
Description of drawings
Fig. 1 is embodiment of the invention evaporation aluminum film production releasing sacrificial layer sketch map
Fig. 2 utilizes sputter, Lift-off technology for the embodiment of the invention and makes the sketch map of electrode stimulating site or record site metal level
Fig. 3 utilizes polyimides photoetching making isolated insulation layer sketch map for the embodiment of the invention
Fig. 4 utilizes electroplating technology for the embodiment of the invention and forms metal column syndeton sketch map
Fig. 5 utilizes the chemical polishing PROCESS FOR TREATMENT for the embodiment of the invention and electroplates back isolated insulation layer upper surface sketch map
Fig. 6 utilizes sputter for the embodiment of the invention and makes the sketch map that electrode connects the lead metal level in conjunction with Lift-off technology
Fig. 7 utilizes polyimides photoetching making external insulation layer sketch map for the embodiment of the invention
Fig. 8 utilizes structural representation after the electrochemical corrosion sacrifice layer discharges electrode for the embodiment of the invention
The specific embodiment
Further specify the concrete characteristics of high-purity implanting planar array microelectrode manufacture method provided by the invention below in conjunction with accompanying drawing:
1) utilizes conventional semiconductor technology cleaning method cleaning silicon chip 1, and prepare about 1 micron thickness aluminum film 2, as the sacrifice layer (Fig. 1) of plated conductive structure and release in surface evaporation;
2) 120 ℃ of baking silicon chips 20 minutes get rid of on the aluminum membranous layer of silicon chip and are coated with 6809 photoresists (3000 rev/mins, 30 seconds), and baking is 20 minutes before 80 ℃;
3) photoetching, sputtered with Ti/Pt/Ti (2500
), in conjunction with Lift-off technology, form electrode stimulating site or record site metal level 3 (Fig. 2);
4) spin coating photo-sensistive polyimide Durimide 7510 (3000 rev/mins, 30 seconds) makes isolated insulation layer 4, and photoetching forms the full solidification (Fig. 3) of implementation structure in 5,350 ℃ of nitrogen environments of through-hole structure;
5) electroplated Ni forms and connects little metal column 6, is higher than polyimide layer upper surface (Fig. 4) until the metal column plane;
6) chemical polishing forms smooth planar surface (Fig. 5);
7) surface after the polishing is got rid of and is coated with 6809 photoresists (3000 rev/mins, 30 seconds), and baking is 20 minutes before 80 ℃;
8) photoetching, sputtered with Ti/Pt (2000
), in conjunction with Lift-off technology, form electrode and connect lead metal level 7 (Fig. 6);
9) spin coating photo-sensistive polyimide Durimide 7510 (3000 rev/mins, 30 seconds) makes external insulation layer 8, and the full solidification (Fig. 7) of implementation structure in 9, the 350 ℃ of nitrogen environments in exposure welding site is windowed in photoetching;
10) electrochemical corrosion aluminum film discharges electrode (Fig. 8).
Claims (6)
1, a kind of high-purity implanting planar array microelectrode is characterized in that described planar array microelectrode structure is connected conductor layer by one deck electrode stimulating site or record site layer, one deck through hole articulamentum and one deck at least and forms; Described electrode stimulating site or record site layer are connected with it on different aspects that lead is in one or more layers insulating barrier respectively; Described electrode stimulating site or record site layer are connected lead with it insulating barrier connects by the via metal microtrabeculae structure on the isolated insulation layer; Wherein via metal microtrabeculae syndeton is made by electroplating technology, and the surface that utilizes the chemical polishing PROCESS FOR TREATMENT to electroplate the back material makes the upper surface of the upper surface that connects the metal microtrabeculae and isolated insulation layer in the same plane, guarantee plated metal post and good being electrically connected of upper strata splash-proofing sputtering metal layer, via metal microtrabeculae area is less than electrode stimulating site or record site area.
2, make the method for high-purity implanting planar array microelectrode as claimed in claim 1, it is characterized in that described array microelectrode utilizes polymer as insulating layer material, design by the interlayer wiring, with electrode stimulating site or record site and its connection arrangement of conductors between different insulating barriers, and on isolated insulation layer, make through-hole structure, form metal connecting structure by electroplating technology in through hole, realizing being positioned at the isolated insulation layer upper/lower electrode stimulates site or record site to be connected the connection of lead with it; Wherein behind the electroplating technology, adopt the method for chemical polishing that upper surface is polished, make plated metal post and good being electrically connected of upper strata splash-proofing sputtering metal layer; Utilize conventional semiconductor technology cleaning method cleaning silicon chip, and prepare 1 micron thickness aluminum film, as the sacrifice layer of plated conductive structure and release in surface evaporation; Concrete making step is:
1) on base material, makes electrode stimulating site or record site metal level by sputter and stripping technology;
2) by photoetching making isolated insulation layer and connecting through hole;
3) utilize plating to make and connect metal level by through hole;
4) chemical polishing forms smooth planar surface;
5) making is connected the lead metal level with stripping technology by sputter;
6) by photoetching making upper insulation layer and pad window;
7) the corrosion sacrifice layer discharges electrode.
3, the manufacture method of high-purity implanting planar array microelectrode according to claim 2, it is characterized in that described isolated insulation layer is by spin coating or vapour deposition making isolated insulation layer, insulating layer material is polyimides or vapour deposition silicon dioxide, silicon nitride or Parylene, and its thickness is between 100 dusts to 500 micron.
4, the manufacture method of high-purity implanting planar array microelectrode according to claim 2, it is characterized in that connecting metal level is titanium, chromium, copper, aluminum, gold or platinum, thickness is 100 dusts to 50 micron.
5, the manufacture method of high-purity implanting planar array microelectrode according to claim 2 is characterized in that electrode stimulating point or record site metal material are gold, platinum or iridium, and metal layer thickness is 100 dusts to 100 micron.
6, by the manufacture method of the described high-purity implanting planar array microelectrode of claim 2, it is characterized in that discharging electrode by acid corrosion or electrochemical corrosion sacrifice layer, sacrificial layer material is aluminum, copper or silicon dioxide.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101240435B (en) * | 2008-03-06 | 2011-02-09 | 复旦大学 | Plating self-welding method for three-dimensional micro-electrode array |
| CN101870452B (en) * | 2010-07-09 | 2012-09-19 | 上海交通大学 | Preparation method of MEMS (Micro Electro Mechanical Systems) metal wire biological microelectrode |
| CN101950741B (en) * | 2010-08-13 | 2012-08-22 | 上海交通大学 | Method for producing chip electrode multilevel interconnection structure |
| CN102321536B (en) * | 2011-09-30 | 2013-04-03 | 岭南大学校产学协力团 | High-flux cell electrofusion device based on microporous array film |
| DE102014014943A1 (en) * | 2014-10-07 | 2016-04-07 | Neuroloop GmbH | Implantable electrode arrangement |
| CN105169554B (en) * | 2015-09-14 | 2017-12-15 | 上海交通大学 | A kind of preparation method of vision prosthesis flexible nervus pad |
| CN106646048B (en) * | 2016-12-23 | 2019-11-12 | 深圳市中科先见医疗科技有限公司 | A kind of preparation method of microelectrode array |
| CN109350846A (en) * | 2018-11-29 | 2019-02-19 | 深圳先进技术研究院 | A kind of functionalization wide cut implantation micro-electrode array and the preparation method and application thereof |
| CN110327544B (en) * | 2019-06-20 | 2020-10-02 | 上海交通大学 | Implanted high-density electrode point flexible probe electrode and preparation method thereof |
| CN112657053B (en) * | 2020-03-31 | 2024-03-29 | 深圳硅基仿生科技股份有限公司 | Implanted double-sided electrode and preparation method thereof |
| CN112631425B (en) * | 2020-12-21 | 2022-03-22 | 上海交通大学 | Microneedle array type brain-computer interface device and preparation method thereof |
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| CN1820799A (en) * | 2006-03-30 | 2006-08-23 | 上海交通大学 | Implantable sheet type optic nerve micro stimulating electrode |
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