CN101950741B - Method for producing chip electrode multilevel interconnection structure - Google Patents
Method for producing chip electrode multilevel interconnection structure Download PDFInfo
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- CN101950741B CN101950741B CN2010102524234A CN201010252423A CN101950741B CN 101950741 B CN101950741 B CN 101950741B CN 2010102524234 A CN2010102524234 A CN 2010102524234A CN 201010252423 A CN201010252423 A CN 201010252423A CN 101950741 B CN101950741 B CN 101950741B
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Abstract
The invention relates to a method for producing a chip electrode multilevel interconnection structure in the technical field of biomedicine. The method has the following steps: imaging photo resist on a substrate to determine the position of a chip; placing the chip on the substrate and then depositing a layer of thin polymer film on the surface of the chip by chemical vapor deposition to fix the chip; pouring a polymer layer with a thickness of 500 mu m outside the position of the chip on the substrate, carrying out curing process on the polymer layer, stripping off the substrate to cause the chip to be coated by the polymer layer; and afterwards, carrying out the following steps repeatedly by n numbered times in sequence on the whole surface of the polymer layer: sputtering and imaging the metal layer, depositing the thin polymer film with a thickness of 6-8 mu m by chemical vapor deposition and imaging the thin polymer film to realize multilevel chip electrode interconnection, wherein n is a constant which is equal to or more than 3.The structure of the invention can greatly increase interconnection of the chip and electrodes per unit area, enhances the effect of electrode stimulation and collection and can be conveniently used in artificial prosthesis devices.
Description
Technical field
What the present invention relates to is a kind of method of biomedical engineering field, specifically is a kind of preparation method of chip electrode multilayer interconnect structure.
Background technology
Artificial prosthesis is used to treat and recover certain human body organ of loss of function, can help patient to recover eyesight like vision prosthesis, and the artificial cochlea can help patient to recover hearing etc.Artificial prosthesis generally is made up of control chip and electrode as a system that is implanted in the human body.The direct interconnection of chip and electrode not only can reduce the volume of whole system, also can make system more convenient when implanting, and reduces the wound to human body.The single layer of chips electrode interconnection, the number of electrodes that chip connects on unit are is limited.The multilayer chiop electrode interconnection can be on unit are, and the number of electrodes that makes chip connect is the several times of single layer of interconnects, and multiple depends on the interconnection number of plies.The multilayer chiop electrode interconnection helps on unit are, to increase the quantity of chip connection electrode, helps electrode stimulating and collection effect.
Retrieval through to the prior art document finds that DAMIEN C.RODGER and YU-CHONG TAI are at IEEE Eng Med Biol Mag.2005Sep-Oct; 24 (5): 52-7. is last to be write articles " Microelectronic Packaging for Retinal Prostheses ".(" microelectronics Packaging that is used for vision prosthesis " medical science and bioengineering magazine).Chip of mentioning in this article and electrode interconnection are single layer of interconnects, and the limited amount that chip is connected with electrode on unit are is unfavorable for improving the effect of electrode stimulating and collection.And this technology uses silicon to be substrate, and the technology cost is higher.
Summary of the invention
The present invention is directed to the above-mentioned deficiency that prior art exists; A kind of preparation method of chip electrode multilayer interconnect structure is provided; The structure for preparing makes that the interconnection quantity of chip and electrode increases greatly on the unit are; The effect that helps electrode stimulating and collection can conveniently be applied in the artificial prosthesis device.
The present invention realizes through following technical scheme; At first graphical photoresist is confirmed chip position on substrate; Chip is placed after the substrate at chip surface chemical meteorology deposition one layer of polymeric film with fixed chip; And the chip position of substrate is poured into a mould polymeric layer that a layer thickness is 500 μ m and cured with exterior portions after, substrate is peeled off; Chip is wrapped up by polymeric layer, repeat n time on whole polymeric layer surface successively then and carry out: sputter and graphical metal level, chemical meteorology deposition thin polymer film 6～8 μ m and graphical thin polymer film are realized the interconnection of multilayer chiop electrode, and wherein n is the natural constant more than 3 or 3.
Described graphical photoresist confirms that chip position is meant: at first on substrate with 1900 rev/mins speed spin coating AZ 4903 photoresists 60 seconds, adopt 150 seconds definite chip positions of AZ-400K developing liquid developing then;
Described deposition first thin polymer film is meant: adopt chemical Meteorological Act to deposit the Parylene that a layer thickness is 2～4 μ m at chip surface,
Described polymeric layer is a dimethyl silicone polymer.
Described cured is meant: place baking oven with 80 ℃ of bakings 3 hours first polymeric layer.
Described metal level is gold, titanium or platinum.
Compared with prior art; The present invention prepares the chip electrode interconnection structure of gained; On unit are, can increase the interconnection quantity of chip and electrode greatly; The effect that helps electrode stimulating and collection, and be that substrate avoided with silicon with the polymer be that substrate need be used the higher equipment of technology cost, greatly reduce the technology cost.
Description of drawings
Fig. 1 is embodiment 1 sketch map.
Fig. 2 is embodiment 2 sketch mapes.
Fig. 3 is embodiment 3 sketch mapes.
Embodiment
Elaborate in the face of embodiments of the invention down, present embodiment provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment being to implement under the prerequisite with technical scheme of the present invention.
Embodiment 1
As shown in Figure 1, present embodiment prepares through following steps:
The first step, on silicon chip the spin coating photoresist, and graphical photoresist;
Described spin coating photoresist is meant with 1900 rev/mins speed spin coating AZ 4903 photoresists 60 seconds.
After described graphical photoresist is meant exposure, adopted the AZ-400K developing liquid developing 150 seconds.
Second step, chip is placed on the silicon chip position of confirming, and deposited polymer film fixed chip;
Described deposited polymer is meant the chemical meteorology deposition Parylene.
Described polymer thin film thickness is 2～4 μ m.
The 3rd step, at the silicon chip top-pour polymer injection of having fixed chip as substrate, and cure polymer.
Described polymer is a dimethyl silicone polymer.
Described cure polymer is with 80 ℃ of bakings 3 hours in baking oven.
The 4th goes on foot, peels off chip location silicon chip, and chip is stayed in the polymeric substrates.
The 5th goes on foot, carries out for 3 times in the surface repetition of whole polymeric layer: sputter and graphical metal level, the also graphical thin polymer film of chemical meteorology deposition thin polymer film.
Described metal is a gold.
Described graphical metal is a graphically gold of stripping technology.
Described polymer is a Parylene.
Described polymer thin film thickness is 6～8 μ m.
Described graphical thin polymer film is for the photoresist being mask use reactive ion etching Parylene.
The 6th step, releasing chips and electrode.
Described release is peeled off chip electrode on the ground from polymer-matrix after being meant the suprabasil metal of etch polymers.
Embodiment 2
As shown in Figure 2, present embodiment prepares through following steps:
The first step, on silicon chip the spin coating photoresist, and graphical photoresist;
Described spin coating photoresist is meant with 1900 rev/mins speed spin coating AZ 4903 photoresists 60 seconds.
After described graphical photoresist is meant exposure, adopted the AZ-400K developing liquid developing 150 seconds.
Second step, chip is placed on the silicon chip position of confirming, and deposited polymer film fixed chip;
Described deposited polymer is meant the chemical meteorology deposition Parylene.
Described polymer thin film thickness is 2～4 μ m.
The 3rd step, at the silicon chip top-pour polymer injection of having fixed chip as substrate, and cure polymer.
Described polymer is a dimethyl silicone polymer.
Described cure polymer is with 80 ℃ of bakings 3 hours in baking oven.
The 4th goes on foot, peels off chip location silicon chip, and chip is stayed in the polymeric substrates.
The 5th goes on foot, carries out for 4 times in the surface repetition of whole polymeric layer: sputter and graphical metal level, the also graphical thin polymer film of chemical meteorology deposition thin polymer film.
Described metal is a titanium.
Described graphical metal is the graphical titanium of stripping technology.
Described polymer is a Parylene.
Described polymer thin film thickness is 6～8 μ m.
Described graphical thin polymer film is for the photoresist being mask use reactive ion etching Parylene.
The 6th step, releasing chips and electrode.
Described release is peeled off chip electrode on the ground from polymer-matrix after being meant the suprabasil metal of etch polymers.
Embodiment 3
As shown in Figure 3, present embodiment prepares through following steps:
The first step, on silicon chip the spin coating photoresist, and graphical photoresist;
Described spin coating photoresist is meant with 1900 rev/mins speed spin coating AZ 4903 photoresists 60 seconds.
After described graphical photoresist is meant exposure, adopted the AZ-400K developing liquid developing 150 seconds.
Second step, chip is placed on the silicon chip position of confirming, and deposited polymer film fixed chip;
Described deposited polymer is meant the chemical meteorology deposition Parylene.
Described polymer thin film thickness is 2～4 μ m.
The 3rd step, at the silicon chip top-pour polymer injection of having fixed chip as substrate, and cure polymer.
Described polymer is a dimethyl silicone polymer.
Described cure polymer is with 80 ℃ of bakings 3 hours in baking oven.
The 4th goes on foot, peels off chip location silicon chip, and chip is stayed in the polymeric substrates.
The 5th goes on foot, carries out for 5 times in the surface repetition of whole polymeric layer: sputter and graphical metal level, the also graphical thin polymer film of chemical meteorology deposition thin polymer film.Described metal is a platinum.
Described graphical metal is the graphical platinum of stripping technology.
Described polymer is a Parylene.
Described polymer thin film thickness is 6～8 μ m.
Described graphical thin polymer film is for the photoresist being mask use reactive ion etching Parylene.
The 6th step, releasing chips and electrode.
Described release is peeled off chip electrode on the ground from polymer-matrix after being meant the suprabasil metal of etch polymers.The technology of the foregoing description simply, not only can reduce the technology cost greatly and on unit are, can increase the quantity of chip and electrode interconnection, helps electrode stimulating and collection effect.
Claims (5)
1. the preparation method of a chip electrode multilayer interconnect structure; It is characterized in that: at first graphical photoresist is confirmed chip position on substrate; Chip is placed after the substrate at chip surface chemical vapour deposition (CVD) one layer of polymeric film with fixed chip; And the chip position of substrate is poured into a mould polymeric layer that a layer thickness is 500 μ m and cured with exterior portions after, substrate is peeled off; Chip is wrapped up by polymeric layer, repeat n time on whole polymeric layer surface successively then and carry out: sputter and graphical metal level, chemical vapor deposition polymerization thing film 6～8 μ m and graphical thin polymer film are realized the interconnection of multilayer chiop electrode, and wherein n is the natural constant more than 3; Said thin polymer film is a Parylene, and said polymeric layer is a dimethyl silicone polymer.
2. the preparation method of chip electrode multilayer interconnect structure according to claim 1; It is characterized in that; Described graphical photoresist confirms that chip position is meant: at first on substrate with 1900 rev/mins speed spin coating AZ 4903 photoresists 60 seconds, adopt 150 seconds definite chip positions of AZ-400K developing liquid developing then.
3. the preparation method of chip electrode multilayer interconnect structure according to claim 1 is characterized in that, described chemical vapour deposition (CVD) one layer of polymeric film is meant: adopt chemical gas-phase method to deposit the Parylene that a layer thickness is 2～4 μ m at chip surface.
4. the preparation method of chip electrode multilayer interconnect structure according to claim 1 is characterized in that, described cured is meant: will pour into a mould polymeric layer and place baking oven with 80 ℃ of bakings 3 hours.
5. the preparation method of chip electrode multilayer interconnect structure according to claim 1 is characterized in that, described metal level is gold, titanium or platinum.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102569107B (en) * | 2011-12-15 | 2014-04-30 | 上海交通大学 | Preparation method of elastic contact interconnection structure of chip and electrode |
| CN107705971A (en) * | 2017-08-30 | 2018-02-16 | 歌尔股份有限公司 | A kind of manufacture method of coil, coil, electronic equipment |
| CN110143569A (en) * | 2019-05-29 | 2019-08-20 | 京东方科技集团股份有限公司 | The preparation method of microelectrode diaphragm |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6862805B1 (en) * | 1998-08-26 | 2005-03-08 | Advanced Bionics Corporation | Method of making a cochlear electrode array having current-focusing and tissue-treating features |
| CN101073687A (en) * | 2007-05-18 | 2007-11-21 | 中国科学院上海微系统与信息技术研究所 | High-purity implanting planar array microelectrode and its production |
| CN101172185A (en) * | 2007-09-21 | 2008-05-07 | 中国科学院上海微系统与信息技术研究所 | Process for producing implantation type two-sided flexible tiny array electrode |
| CN101583309A (en) * | 2005-10-07 | 2009-11-18 | 神经连结科技公司 | Modular multichannel microelectrode array and methods of making same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6862805B1 (en) * | 1998-08-26 | 2005-03-08 | Advanced Bionics Corporation | Method of making a cochlear electrode array having current-focusing and tissue-treating features |
| CN101583309A (en) * | 2005-10-07 | 2009-11-18 | 神经连结科技公司 | Modular multichannel microelectrode array and methods of making same |
| CN101073687A (en) * | 2007-05-18 | 2007-11-21 | 中国科学院上海微系统与信息技术研究所 | High-purity implanting planar array microelectrode and its production |
| CN101172185A (en) * | 2007-09-21 | 2008-05-07 | 中国科学院上海微系统与信息技术研究所 | Process for producing implantation type two-sided flexible tiny array electrode |
Non-Patent Citations (1)
| Title |
|---|
| Damien C.Rodger,Yu-Chong Tai.Microelectronic Packaging for Retinal Prostheses.《IEEE Engineering in Medicine and Biology Magazine》.2005,第24卷(第5期),第52-57页. * |
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