CN100563142C - Utilize pointer leakage to solve the apparatus and method of signal dithering problem - Google Patents
Utilize pointer leakage to solve the apparatus and method of signal dithering problem Download PDFInfo
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- CN100563142C CN100563142C CNB2005101326659A CN200510132665A CN100563142C CN 100563142 C CN100563142 C CN 100563142C CN B2005101326659 A CNB2005101326659 A CN B2005101326659A CN 200510132665 A CN200510132665 A CN 200510132665A CN 100563142 C CN100563142 C CN 100563142C
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Abstract
The invention discloses a kind of device that utilizes pointer leakage to solve signal dithering problem, this device comprises: adjust the bit statistic unit; Leveling factor unit, be used for the neutral condition parameter of synchronous fifo fifo unit is carried out filtering, with neutral condition parameter the bit number to be leaked that comes self-adjusting bit statistic unit is revised, and will be sent to the bit leaking unit through the bit number of revising to be leaked through filtering; The bit leaking unit.The invention also discloses a kind of method of utilizing pointer leakage to solve signal dithering problem.Among the present invention, carry out filtering by neutral condition parameter in leveling factor unit to cell fifo, and treat the leakage bit number according to the neutral condition parameter of process filtering and revise, even it is rapider that the FIFO center line changes, when correction is waited to leak bit number according to filtered neutral condition parameter, can not cause yet and wait to leak the bigger transient change of bit number, improve professional jitter performance, thereby improve leakage effect yet.
Description
Technical field
The present invention relates to the communication system signal transmission technique field, be meant a kind of device and a kind of method of utilizing pointer leakage to solve signal dithering problem of utilizing pointer leakage to solve signal dithering problem especially.
Background technology
In communication system, the main cause that signal produces is owing to mapping is conciliate in multiplexing, demultiplexing, mapping, and the regeneration of signal recovers transmission etc.In Synchronous Digital Hierarchy SDH system, DS3, E3 business often are mapped among the VC3, further are multiplexed in the higher rate business and transmit; Separate when mapping accordingly, from VC3, reducing DS3, E3 business.When shining upon the reconciliation mapping, need carry out the pointer adjustment.Because a pointer adjustment can cause the increase and decrease of the payload of DS3, E3 business, these increases and decreases are exactly the main source that produces shake.If this increase and decrease is not controlled, will produce bigger burst shake, have a strong impact on the quality of signal transmission.
In order to control the increase and decrease of above-mentioned bit, suppress shake, improve signal transmission quality, adopt the method for bit leaking to reduce usually because the shake that the pointer adjustment causes.
In the prior art, utilize specific implementation that pointer leakage solves above-mentioned jitter problem method as shown in Figure 1, mainly may further comprise the steps:
Because the once corresponding byte of pointer adjustment, and corresponding 8 bits (bit) of each byte, so the conversion factor value is 8, bit number then to be leaked equals pointer adjustment number of times and multiply by 8.
For DS3, the bit number in every frame is 5592, and for E3, the bit number in every frame is 4296.The structure of VC3 is 9 row, 85 row, and the quantity of DS3 bit is 621 or 622 in every row, and the bit number of E3 is 477 or 478.Every row provides and once leaks chance in VC3, when leakage enables, this row leaks a bit, and every row of the DS3 correspondence after then leaking may be 620,621,622 or 623 bits, and every row of the E3 correspondence after leaking may be 476,477,478 or 479 bits.When generating the breach clock, the bit number of corresponding every row, system need generate eight kinds of breach clocks.
In the above-mentioned prior art, directly the neutral condition of FIFO is revised the bit leak rate as correction factor, because when pointer is adjusted, the FIFO center line changes rapider, the bit leaking rate can cause bigger transient change because of the rapid variation of FIFO center line, the traffic affecting jitter performance, thus leakage effect also influenced.
In addition, the conversion factor value is 8 in the above-mentioned prior art, because after in VC3 that DS3 is packed into, need to increase expense and the filling bit of VC3, when carrying out bit leaking, the bit of leakage may be expense or the filling bit of VC3, and it is inaccurate so just to have caused the bit leaking rate to be calculated, deviation is big, has influenced leakage effect.
And in above-mentioned prior art, for DS3, E3, because the structure according to VC3 generates the breach clock, so the data that need eight kinds of breach clock pulse of generation to read among the FIFO altogether realize leaking, need the breach clock pulse kind of generation many, increase system complexity, improved design difficulty, also influenced the stability of system.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of device and a kind of method of utilizing pointer leakage to solve signal dithering problem of utilizing pointer leakage to solve signal dithering problem, can improve leakage effect.
Be first aspect that achieves the above object, the invention provides a kind of device that utilizes pointer leakage to solve signal dithering problem, this device comprises:
Adjust the bit statistic unit, be used for statistical indicator adjustment number of times in the time of setting, determine bit number to be leaked according to conversion factor and pointer adjustment number of times, and the bit number to be leaked that will determine sends to leveling factor unit;
Leveling factor unit, be used for the neutral condition parameter of synchronous fifo fifo unit is carried out filtering, with neutral condition parameter the bit number to be leaked that comes self-adjusting bit statistic unit is revised, and will be sent to the bit leaking unit through the bit number of revising to be leaked through filtering;
The bit leaking unit be used for adjusting the breach clock according to the time of leaking bit number and described setting of waiting through revising from leveling factor unit, and the data of using adjusted breach clock to read in the synchronization fifo unit is realized leaking;
The synchronization fifo unit is used to store data, and provides synchronization fifo neutral condition related data to leveling factor unit.
Preferably, described leveling factor unit comprises:
FIFO departs from center line bit statistic unit, be used to generate synchronization fifo and depart from the neutral condition parameter, and the described state parameter that will generate sends to filter unit;
Filter unit is used for the state parameter value that departs from center line bit statistic unit from FIFO is carried out filtering, and filtered state parameter value is outputed to correction factor conversion unit;
Correction factor conversion unit, be used for and be converted to correction factor from the state parameter value of filter unit, and use correction factor that the bit number to be leaked that comes self-adjusting bit statistic unit is revised, and will send to the bit leaking unit through the bit number of revising to be leaked.
Preferably, described filter unit is the infinite impulse response iir filter.
Preferably, described bit leaking unit comprises:
Leakage enables generation unit, be used for generating the leakage enable signal according to the time of leaking bit number and described setting of waiting from leveling factor unit, and the leakage enable signal that will generate sends to the breach clock generating unit;
The breach clock generating unit is used for adjusting a breach clock according to enable the polarity that the leakage enable signal of generation unit and pointer adjust from leakage, and uses adjusted breach clock to read data in the synchronization fifo unit.
Preferably, described leakage enables generation unit and is: the type that adds up numerically-controlled oscillator (DCO).
Preferably, comprise in the described synchronization fifo unit: width is the random access storage device RAM of 1 bit.
Preferably, the described RAM degree of depth is 512 bits.
By such scheme as can be seen, device of the present invention carries out filtering by the neutral condition parameter to the synchronization fifo unit in leveling factor unit, and treat the leakage bit number with the neutral condition parameter of process filtering and revise, it is rapider thereby even the FIFO center line changes, after waiting to leak bit number with the correction of filtered neutral condition parameter, just can not cause and wait to leak the bigger transient change of bit number, improve professional jitter performance, thereby improved leakage effect yet;
In addition, in apparatus of the present invention, by realize the control to leak rate with the type DCO that adds up, because the type DCO precise control that adds up, cost is low, realize simple, thereby make among the present invention very accurately to the control of leaking, also reduced cost.
Be second aspect that achieves the above object, the invention provides a kind of method of utilizing pointer leakage to solve signal dithering problem, this method comprises:
A, the pointer in statistics a period of time are adjusted number of times, and utilize pointer to adjust number of times and conversion factor calculating bit number to be leaked;
B, with through filtered FIFO neutral condition parameter as correction factor, treat and leak bit number and revise, and with interior frame number of described a period of time divided by described revised bit number to be leaked, calculate the bit leaking rate;
C, according to the bit leaking rate, when leakage enables, adjust a pulse on the breach clock basis in present frame and generate the breach clock, and use the breach clock that generates to read the data that are temporarily stored among the FIFO.
Preferably, a period of time described in the steps A is: 2
iMulti-frame, wherein i is an integer, span is 1 to 32.
Preferably, described i is 16.
Preferably, the frame number described in the step B is basic frame number, and described present frame is current basic frame, comprises 4 basic frames in the then described multi-frame.
Preferably, the conversion factor described in the steps A is 5 for the DS3 business, is 7 for the E3 business.
Preferably, described being filtered into: at first deduct FIFO with half x of the RAM degree of depth among the FIFO and depart from center line bit number m, promptly x-m obtains difference n, then resulting poor n is carried out filtering;
Then described correction factor is:
Preferably, the breach clock of the generation described in the step C is the clock that generates 179 pulses in the time of 125 μ s/24 for the E3 business, is the clock that generates 233 pulses in the time of 125 μ s/24 for the DS3 business.
By such scheme as can be seen, in the inventive method, with the correction factor of the filtered FIFO neutral condition of process as bit leaking, treating the leakage bit number revises, be rapider, owing to, can not cause and wait to leak the bigger transient change of bit number according to filtered neutral condition parameter correction bit number to be leaked thereby even the FIFO center line changes, improve professional jitter performance, thereby also improved leakage effect;
In addition, adopted more rational conversion factor that pointer is adjusted number conversion in the inventive method and be bit number to be leaked, the leakage of realization is more steady, has improved leakage effect;
And then, in the inventive method, because for the E3 business is the clock that generates 179 pulses in the time of 125 μ s/24, for the DS3 business is the clock that generates 233 pulses in the time of 125 μ s/24, in leakage process, only needs six kinds of breach clocks in the system, reduced the kind of breach clock, reduce system complexity, reduced design difficulty, also improved the stability of system.
Description of drawings
Fig. 1 is the flow chart of prior art;
Fig. 2 is the structure chart of apparatus of the present invention specific embodiment;
Fig. 3 is the flow chart of the inventive method specific embodiment.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Main thought of the present invention is, with the correction factor of the filtered FIFO neutral condition of process as bit leaking, treating the leakage bit number revises, it is rapider thereby even the FIFO center line changes, because according to filtered neutral condition parameter correction bit number to be leaked, can not cause and wait to leak the bigger transient change of bit number, improve professional jitter performance, thereby improve leakage effect yet.
Also when adjusting number calculating bit leaking rate according to pointer, adopt more reasonably conversion factor among the present invention in addition, when the bit leak rate is revised, also adopt more reasonably correction factor.
Also further provide among the present invention and reduced the implementation of breach clock kind, thereby improved leakage effect greatly, reduced design difficulty, improved stability.
The present invention is described in detail below by specific embodiment.
As shown in Figure 2, be the device composition diagram of present embodiment, comprise and adjust bit statistic unit 21, leveling factor unit 22, bit leaking unit 23 and synchronization fifo unit 24.Wherein, adjust bit statistic unit 21 and be used for statistical indicator adjustment number of times in the time of setting, determine bit number to be leaked according to conversion factor and pointer adjustment number of times, and the bit number to be leaked that will determine sends to leveling factor unit; Leveling factor unit 22 is used for the neutral condition parameter of synchronous fifo fifo unit is carried out filtering, with neutral condition parameter the bit number to be leaked that comes self-adjusting bit statistic unit is revised, and will be sent to the bit leaking unit through the bit number of revising to be leaked through filtering; Bit leaking unit 23 be used for adjusting the breach clock according to the time of leaking bit number and described setting of waiting from leveling factor unit, and the data of using adjusted breach clock to read in the synchronization fifo unit is realized leaking; Synchronization fifo unit 24 is used to store data, and provides synchronization fifo neutral condition related data to leveling factor unit.
Adjust and comprise specifically in the bit statistic unit 21 that time reference unit 201, pointer are adjusted statistic unit 202 and coefficient is converted unit 203; Comprise specifically in the leveling factor unit 22 that FIFO departs from center line bit statistic unit 204, filter unit 205, correction factor conversion unit 206 and multiplier 207; Specifically comprise again in the bit leaking unit 23 leaking and enable generation unit 208 and breach clock generating unit 209.
Wherein, time reference unit 201 is used for the generation time benchmark, pointer is adjusted statistic unit control.Time reference gets 2 in the present embodiment
iMulti-frame, then time reference unit 201 specifically can adopt the counter of i position to realize as timer, and wherein, i can get the positive integer value between 1 to 32.For example, the i value was got 16 o'clock, and the time reference unit can adopt the sixteen bit counter as timer, every header signal of a multi-frame, and counter is once counted, through adjusting signal of statistic unit output to pointer behind 65536 multi-frames.
Pointer is adjusted statistic unit 202 and is used for pointer adjustment index signal is counted, do when pointer positive justification signal is effective and subtract a counting, do when pointer negative justification signal is effective and add a counting, behind the signal that receives from the time reference unit, recording gauge numerical value, count value is adjusted sum (ptrsum) as pointer export to coefficient conversion unit 203, and restart counting.Pointer is adjusted statistic unit 202 and can be adopted forward-backward counter to realize, behind the signal that receives from the time reference unit, latch the ptrsum that forward-backward counter calculates, statistical value is outputed to coefficient conversion unit 203, and the forward-backward counter that resets is to initial condition.
The ptrsum that coefficient conversion unit 203 is used for adjusting statistic unit 202 from pointer is converted to bit number to be leaked (bitlksum), and the bitlksum that is converted to is outputed to leveling factor unit 204.Coefficient conversion unit 203 can be realized by multiplier.In the present embodiment, according to the business configuration value, for the E3 business, when converting, conversion factor gets 5, and for the DS3 business, conversion factor gets 7.This be because, after DS3 was loaded among the VC3, the DS3 bit number was 7: 8 with the bit number ratio of VC3 in the frame of every 125us, the pointer adjustment mainly is a byte number of adjusting VC3, adjusts 1 byte=8 bits at every turn, so bit number 7/8 * 8=7 of DS3 is adjusted in equivalence; After E3 was loaded among the VC3, the bit number of the E3 of every frame was 5: 8 with the bit number of VC3 ratio, and then the bit number of equivalence adjustment E3 is 5.
Leveling factor unit 22 is used for the bitlksum from coefficient conversion unit 203 is revised according to the neutral condition of synchronization fifo.Wherein, FIFO departs from center line bit statistic unit 204 and is used to add up the bit rate m that synchronization fifo departs from center line, and with the bit rate m that adds up, or other values relevant with m, as x-m etc., neutral condition parameter as FIFO sends to filter unit 205, and x wherein can be half of FIFO length; 205 pairs of filter units carry out filtering from the FIFO neutral condition parameter that FIFO departs from center line bit statistic unit 204, and filtered FIFO neutral condition parameter outputed to correction factor conversion unit 206, filter unit 205 can adopt infinite impulse response (IIR) filter to come specific implementation; Correction factor conversion unit 206 will be converted to correction factor β from the FIFO neutral condition parameter of filter unit, β can for
And the correction factor β that changes out sent to multiplier 207; Multiplier 207 obtains the revised bit number bitlksum_co that waits to leak after being used for multiplying each other from the bitlksum of coefficient conversion unit 203 and correction factor β from correction factor conversion unit 206, and bitlksum_co outputed to leak enables generation unit 208.
Leakage enables generation unit 208 and is used for generating the leakage enable signal according to the bitlksum_co from leveling factor unit, and the leakage enable signal that will generate sends to breach clock generating unit 209.In the present embodiment, leakage enables generation unit and can adopt the type numerically-controlled oscillator (DCO) that adds up to realize.Suppose that time reference gets 65536 multi-frames, promptly 32.768 seconds, correction factor
Bit number then revised to be leaked
Expression needs the leak rate of the frame number of a bit of leakage
In multi-frame of 4 expressions wherein four frames are arranged.With bitlksum_co substitution leak rate formula, finally obtain:
If 256-m=n,
Then in the type numerically-controlled oscillator that adds up, with the add up stepping of bitlksum as the type digital controlled oscillator that adds up, when the header signal of a basic frame arrives, make one-accumulate, n * 2048 are as the thresholding that overflows of accumulator, adding up, a leakage of generation enable signal outputs to breach clock generating unit 209 when overflowing, and has so just realized every process
Individual basic frame produces into one and leaks enable signal.
Breach clock generating unit 209 is used for producing the breach clock according to the polarity of leakage enable signal that enables generation unit 208 from leakage and pointer adjustment at current line, when pointer is done positive justification, the breach clock pulses number that produces subtracts one on former umber of pulse basis, when pointer is done negative justification, the breach clock pulses number that produces adds one on former umber of pulse basis, and reads less or mutiread goes out a bit in the synchronization fifo unit 24 by breach clock control correspondence.In addition, breach clock generating unit 209 can also be adjusted index signal according to the bit of separating when mapping and directly generate the breach clock.Here, the breach clock generating unit is nominal E3, DS3 breach clock generator, utilizes the notched nominal breach of radio frequency system clock generating clock, and no longer generates clock pulse according to the structure of VC3.For the professional nominal breach of E3 clock is 34.368MHz, and the E3 frame of each 125 μ s is divided into 24, and every generates 179 pulses in the time of 125 μ s/24, form the breach clock, can read 179 bits in the time of 125 μ s/24; For the professional nominal breach of DS3 clock is 44.736MHz, and the DS3 frame of each 125 μ s has been divided into 24, and every generates 233 pulses in the time of 125 μ s/24, form the breach clock, can read 233 bits in the time of 125 μ s/24.Like this, when producing the breach clock, only need generation 178,179,180 and 232,233,234 6 kind of clock pulse to get final product, reduced by two kinds of clock kinds, reduced the complexity of system, improved stability than prior art according to the leakage enable signal.
Synchronization fifo unit 24 is that a degree of depth is 512 bits, width is that the RAM of 1 bit adds read/write address unit composition, be used for being write one by one the data bit after E3 or DS3 business are separated mapping, promptly treat data in synchronization, and depart from center line bit statistic unit 204 to FIFO and provide data to be used for the data of its statistics FIFO neutral condition.
In the mode of flow process the method for utilizing pointer leakage to solve jitter problem in the present embodiment is described in detail again below.As shown in Figure 3, the flow process of pointer leakage may further comprise the steps:
In this step, a period of time is time reference, can get 2
iThe value of multi-frame, wherein the i value is a positive integer, and span is 1 to 32, and preferred values is 16.According to the business configuration value, for the E3 business, when converting, conversion factor gets 5, and for the DS3 business, conversion factor gets 7.
A multi-frame has four basic frames, so the frame number here is four times as the multi-frame number of time reference.When calculating correction factor, at first add up the bit rate m that synchronization fifo departs from center line, and to the bit rate m of statistics, or other values relevant with m, carry out filtering as x-m etc., x wherein can be half of FIFO length; Filtered bit rate is converted to correction factor β, and correction factor β that changes out and the bit leaking rate bitlksum that calculates are multiplied each other, obtain the revised bit number bitlksum_co that waits to leak.
Suppose that time reference gets 2
16=65536 multi-frames, promptly 32.768 seconds, the degree of depth of FIFO was 512bit, correction factor
Bit number then revised to be leaked
Expression needs the leak rate of the frame number of a bit of leakage
In multi-frame of 4 expressions wherein four frames are arranged.With bitlksum_co substitution leak rate formula, finally obtain:
If 256-m=n, then
The bit leaking rate that calculates in step 302 is
Then in this step in the type numerically-controlled oscillator that adds up, with the add up stepping of bitlksum, when the header signal of basic frame arrives as the type digital controlled oscillator that adds up, make one-accumulate, n*2048 is as the thresholding that overflows of accumulator, and adding up produces a leakage enable signal when overflowing, and it is right just to have realized
The counting of frame.After producing the leakage enable signal, polarity according to the pointer adjustment reduces or increases a pulse on original breach clock basis, on a breach clock basis of this base frame, generate the breach clock, and reading data in the synchronization fifo, thereby just leaking or negatively leaking a bit with the breach clock that generates.Here original breach clock is the breach clock that generates 179 pulse shapings in the time of 125 μ s/24 for the E3 business, is the breach clock that generates 233 pulse shapings in the time of 125 μ s/24 for the DS3 business.Like this, when leaking enable signal and produce the breach clock, only need in the time of 125 μ s/24, generate 178,179,180 and 232,233,234 6 kind of clock pulse get final product, and reduced by two kinds of clock kinds than prior art, reduce the complexity of system, improved stability.
More than be explanation, in concrete implementation process, can carry out suitable improvement, to adapt to the concrete needs of concrete condition method of the present invention to the specific embodiment of the invention.Therefore be appreciated that according to the specific embodiment of the present invention just to play an exemplary role, not in order to restriction protection scope of the present invention.
Claims (14)
1, a kind of device that utilizes pointer leakage to solve signal dithering problem is characterized in that this device comprises:
Adjust the bit statistic unit, be used for statistical indicator adjustment number of times in the time of setting, determine bit number to be leaked according to conversion factor and pointer adjustment number of times, and the bit number to be leaked that will determine sends to leveling factor unit;
Leveling factor unit, be used for the neutral condition parameter of synchronous fifo fifo unit is carried out filtering, with neutral condition parameter the bit number to be leaked that comes self-adjusting bit statistic unit is revised, and will be sent to the bit leaking unit through the bit number of revising to be leaked through filtering;
The bit leaking unit be used for adjusting the breach clock according to the time of leaking bit number and described setting of waiting through revising from leveling factor unit, and the data of using adjusted breach clock to read in the synchronization fifo unit is realized leaking;
The synchronization fifo unit is used to store data, and provides synchronization fifo neutral condition related data to leveling factor unit.
2, device according to claim 1 is characterized in that, described leveling factor unit comprises:
FIFO departs from center line bit statistic unit, be used to generate synchronization fifo and depart from the neutral condition parameter, and the described state parameter that will generate sends to filter unit;
Filter unit is used for the state parameter value that departs from center line bit statistic unit from FIFO is carried out filtering, and filtered state parameter value is outputed to correction factor conversion unit;
Correction factor conversion unit, be used for and be converted to correction factor from the state parameter value of filter unit, and use correction factor that the bit number to be leaked that comes self-adjusting bit statistic unit is revised, and will send to the bit leaking unit through the bit number of revising to be leaked.
3, device according to claim 2 is characterized in that, described filter unit is the infinite impulse response iir filter.
According to arbitrary described device in the claim 1 to 3, it is characterized in that 4, described bit leaking unit comprises:
Leakage enables generation unit, be used for generating the leakage enable signal according to the time of leaking bit number and described setting of waiting from leveling factor unit, and the leakage enable signal that will generate sends to the breach clock generating unit;
The breach clock generating unit is used for adjusting a breach clock according to enable the polarity that the leakage enable signal of generation unit and pointer adjust from leakage, and uses adjusted breach clock to read data in the synchronization fifo unit.
5, device according to claim 4 is characterized in that, described leakage enables generation unit and is: the type that adds up numerically-controlled oscillator DCO.
According to arbitrary described device in the claim 1 to 3, it is characterized in that 6, described synchronization fifo comprises in the unit: width is the random access storage device RAM of 1 bit.
7, device according to claim 6 is characterized in that, the described RAM degree of depth is 512 bits.
8, a kind of method of utilizing pointer leakage to solve signal dithering problem is characterized in that this method comprises:
A, the pointer in statistics a period of time are adjusted number of times, and utilize pointer to adjust number of times and conversion factor calculating bit number to be leaked;
B, with through filtered FIFO neutral condition parameter as correction factor, treat and leak bit number and revise, and with interior frame number of described a period of time divided by described revised bit number to be leaked, calculate the bit leaking rate;
C, according to the bit leaking rate, when leakage enables, adjust a pulse on the breach clock basis in present frame and generate the breach clock, and use the breach clock that generates to read the data that are temporarily stored among the FIFO.
9, method according to claim 8 is characterized in that, a period of time described in the steps A is: 2
iMulti-frame, wherein i is an integer, span is 1 to 32.
10, method according to claim 9 is characterized in that, described i is 16.
11, method according to claim 9 is characterized in that, the frame number described in the step B is basic frame number, and described present frame is current basic frame, comprises 4 basic frames in the then described multi-frame.
12, method according to claim 8 is characterized in that, the conversion factor described in the steps A is 5 for the DS3 business, is 7 for the E3 business.
13, method according to claim 12 is characterized in that, described being filtered into: at first deduct FIFO with half x of the RAM degree of depth among the FIFO and depart from center line bit number m, promptly x-m obtains difference n, then resulting poor n is carried out filtering;
Then described correction factor is:
14, according to Claim 8 to 13 described methods, it is characterized in that, the breach clock of the generation described in the step C is the clock that generates 179 pulses in the time of 125 μ s/24 for the E3 business, is the clock that generates 233 pulses in the time of 125 μ s/24 for the DS3 business.
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