CN100557708C - Non-integral bit system - Google Patents
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- CN100557708C CN100557708C CNB2005100599146A CN200510059914A CN100557708C CN 100557708 C CN100557708 C CN 100557708C CN B2005100599146 A CNB2005100599146 A CN B2005100599146A CN 200510059914 A CN200510059914 A CN 200510059914A CN 100557708 C CN100557708 C CN 100557708C
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Abstract
The present invention abandons when product renewal b (identical element position) being added 1, and this is that N (identical element status number) is added 1 (or more).Because N no longer is 2 integer power, b is a non-integer, so this N system system is called as non-integral bit system.Non-integral bit system is that unit is deciphered with the word.Wide by regulating word, can improve the efficient of non-integral bit system.
Description
Technical field
The present invention relates to integrated electronic system, or rather, relate to data storage and transmission system.
Background technology
Adopt multilayer storage element (multi-level cell) to help improving storage density.A multilayer storage element (as N layer quickflashing unit) can have N (identical element status number, N＞2) kind state, is worth as N Vt (threshold voltage).The b (identical element position) of routine strata flash unit is an integer, so industry member has got started the research and development of 3 quickflashing units (b=3) and 4 quickflashing units (b=4) after successfully 2 quickflashing units (b=2) being introduced to the market.Though from 12 more or less freely (it is 2 that N is increased to the 4-increment from 2) of regenerating, from 2 to 3 again to 4 difficulties very with b, this is because after b=2, and each b increases by 1 and can cause N to increase greatly: work as b=3, N becomes 2
3(=8, bigger by 4) than b=2; Work as b=4, N becomes 2
4(=16, bigger by 8) than b=3.Because Vt window (total Vt window, i.e. TVW) is limited, the very big increase of N can greatly reduce the dispersion of distribution and the interval of each Vt layer: work as b=2, the Vt dispersion of distribution is 0.5V, and Vt can arrive 1.0V (Figure 1A) greatly at interval; Work as b=3, the Vt dispersion of distribution is 0.2V, and Vt only is 0.4V (Figure 1B) at interval; Work as b=4, the Vt dispersion of distribution only is 0.1V, and Vt only is 0.2V (Fig. 1 C) at interval.Reach these indexs, need to drop into a large amount of research and development expenses and incur loss through delay the market cut-in timing.The present invention proposes a kind of non-integral bit storage system, it abandoned conventional, when product renewal, b added 1 method, and just N is added 1 (or more).This notion can be generalized to other data storage and transmission system at an easy rate.
The full name of abridging among the present invention
N-identical element status number (states-per-cell), promptly the status number that has of an identical element is a positive integer;
The m-word is wide, and promptly the identical element number that contains of a word is a positive integer;
Maximum number of bits of n-m N system identical element representative are a positive integer;
B-identical element position (bits-per-cell), maximum number of bits of the first representative of promptly average per unit can be non-integers;
The efficient of β-N system non-integral bit system.
Goal of the invention
Fundamental purpose of the present invention is to improve the storage density of data-storage system.
Another object of the present invention is further to optimize the storage density of non-integral bit system.
Another object of the present invention is to improve the transmission bandwidth of data transmission system.
According to these and other purpose, the invention provides multiple non-integral bit system.
Summary of the invention
In N system system, each identical element can have N kind state (N-identical element status number is a positive integer).Can be used for representing the physical features of state to comprise: threshold voltage, electric charge, electric current, voltage, resistance, optical transmittance or reflectivity, pyroconductivity, electric field, magnetic field etc.Common N system system comprises N system storer (comprising semiconductor memory, disk drive etc.) and N system data transmission system.N system storer is also referred to as multilayer storer (as multi-level flash memory) or multivalued storage, and its identical element is also referred to as storage element; In N system data transmission system, identical element is the input signal in the clock cycle.
The present invention recognizes: when product (as multi-level flash memory) was regenerated, conventional 1 method that b (b-identical element position) is added was no longer practical; Have only to allow the increment of b, just can make production development planning more real, reduce research and development expense and shortening R﹠D cycle less than 1.Correspondingly, the present invention abandons when product renewal b being added 1, and just N is added 1 (or more): as afterwards at b=2 (N=4), the product of research and development of future generation no longer is b=3 (N=8), but N=5,6,7... are because N no longer is 2 integer power, b is a non-integer, so this N system system is called as non-integral bit system.According to the discussion in " background technology ", non-integral bit system is obvious especially in b＞2 o'clock advantage.
Routine integer-bit system is that unit is deciphered with the position, promptly each identical element is deciphered separately.As adopt this decoded mode, the efficient of non-integral bit system lower (Fig. 4 A).Therefore, non-integral bit system is that unit is deciphered with the word, and each word contains m N system identical element (the m-word is wide, m 〉=2 and be a positive integer).Decode procedure is binary process with a N system number conversion in fact exactly.At first, the readout of identical element is sent to an identical element scrambler and converts the binary code of a j position to.Because the status number (2 of this j position binary code representative
j) greater than the status number (N) of identical element, so it is called as like binary code.Comprise thermometer-code (Fig. 6 A-6C, Fig. 9 AB) and accurate binary code (Fig. 7 A-7B, Fig. 9 BB) like binary code.Then, the readout of m identical element is converted to the i bit by a N system-binary decoder together, wherein,
i≤INT[log
2(N
m)]
(INT[x] refer to maximum integer) less than x, its maximal value n is:
n＝i
max＝INT[log
2(N
m)]
(Fig. 2 C).Correspondingly, identical element position b, the number of bits of promptly average each identical element representative,
b≡n/m＝INT[log
2(N
m)]/m，
Be a non-integer (Fig. 3).
Because a N system-binary decoder must occupy certain chip area, it preferably can be shared by a plurality of words.This can realize by an address decoder (or MUX).A N system-binary decoder can be shared in same unit array, also can be shared by a plurality of units array, can also be shared by a plurality of chips.It can be formed on the chip, outside the chip, or part is on chip, part is outside chip.N system-binary decoder can also be programmable.A kind of N system-binary decoder able to programme contains a general processor and program, it can with other parts (as the controller of flash memory or disk drive) shared processing device of system, thereby reduce system cost.
For a given N, identical element position b changes with the wide m of word: as for N=6, and when m=1, b=2, promptly per 2 identical elements are represented 4; When m=2, b=2.5, promptly per 2 identical elements are represented 5 (Fig. 3).As being that word is wide with m=2, storage density is bigger than m=1, so the efficient of m=2 is higher.Correspondingly, the efficient of N system system is defined as b and theoretical limit b thereof
LimitThe ratio:
β≡b/b
limit＝{INT[log
2(N
m)]/m}/{log
2(N
m)/m}
＝INT[log
2(N
m)]/log
2(N
m)。
For a non-integral bit system,, be not that all N system states all are utilized (as last 4 row among the table 3A) in N system-binary decoding process, so β can not reach 100% (Fig. 4 A) because N is not 2 integer power.In order to guarantee β 〉=90%, m need satisfy certain condition, as: work as N=5, m 〉=4; Work as N=6, m 〉=2; Work as N=7, m 〉=3... (Fig. 4 A, Fig. 4 B).On the other hand, can also select the m value to make β reach local maximum, as work as N=7, m preferably gets one of following value: 5,10,15,20,25,31 etc. (Fig. 4 A, Fig. 4 B).
The non-integral bit storer can be applied in the different storage systems, as semiconductor memory, comprising: flash memory, EPROM, EEPROM, MRAM, FeRAM, DRAM, SRAM, resistance variable memory such as covert storer and Ovonyx storage and uniform device (OUM), mask-programmable memory, diode memory, anti-fuse memory etc.; Disk drive (disc drive) comprises optical disc drive (as CD, VCD and DVD) and disc driver (as HDD etc.); Or the like.Similarly notion can also be generalized in the data transmission system at an easy rate.
Description of drawings
Figure 1A-1C is respectively the Vt distribution plan (conventional art) of 4 systems (b=2), 8 systems (b=3), 16 systems (b=4);
Fig. 2 A represents a kind of N system non-integral bit input system that walks abreast; Fig. 2 B represents a kind of N system non-integral bit serial input system; Fig. 2 C lists maximum number of bits n that m N system identical element can be represented;
Fig. 3 represents for a plurality of N values, the relation of identical element position b and the wide m of word;
Fig. 4 A represents for a plurality of N values, the relation of efficient β and the wide m of word; Fig. 4 B lists the m value that meets the following conditions: A) β 〉=90%; B) β reaches local maximum;
Fig. 5 represents a specific embodiment of the parallel input system of N system non-integral bit;
Fig. 6 A is a symbol of thermometer encoder; Fig. 6 B is first embodiment of thermometer encoder; Fig. 6 C is second embodiment of thermometer encoder;
Fig. 7 A represents a kind of accurate binary coder; Fig. 7 B represents a kind of thermometer-code-accurate binary code converter;
Fig. 8 represents a specific embodiment of N system non-integral bit serial input system;
Fig. 9 AA is first embodiment of 6 * 2-2 * 5 code translators; Fig. 9 AB is the truth table of this embodiment; Fig. 9 BA is second embodiment of 6 * 2-2 * 5 code translators; Fig. 9 BB is the truth table of this embodiment; Fig. 9 C represents a kind of N system-binary decoder able to programme;
Figure 10 represents a kind of unit array of the N of containing system non-integral bit identical element.
Embodiment
Fig. 2 A represents a kind of N system non-integral bit input system that walks abreast.In a parallel input system, a plurality of identical elements are visited simultaneously.Typical parallel input system comprises semiconductor memory, as flash memory, EPROM, EEPROM, MRAM, FeRAM, DRAM, SRAM, resistance variable memory such as covert storer and Ovonyx storage and uniform device (OUM), mask-programmable memory, diode memory, anti-fuse memory etc.Semiconductor memory is generally based on storage array, thereby concurrent access can be provided.The parallel input system of N system non-integral bit among Fig. 2 A contains a word 10 and a N system-binary decoder 100.Word 10 contains m N system identical element 10a, 10b...10m, and each identical element has N kind state (expression formula N * m represents m N system identical element or signal).Can be used for representing the physical features of state to comprise: threshold voltage, electric charge, electric current, voltage, resistance, optical transmittance or reflectivity, pyroconductivity, electric field, magnetic field etc.Readout 12a, the 12b...12m of these identical elements is by parallel 18 (the comprising 18a, 18b...18i) of scale-of-two output of delivering to N system-binary decoder 100 and being converted to an i (i is a positive integer) position.
Fig. 2 B represents a kind of N system non-integral bit serial input system.In a serial input system, identical element is visited successively.Typical serial input system comprises disk drive, as CD drive (CD, VCD, DVD etc.) and disc driver (hard disk etc.), and data transmission system.N system non-integral bit serial input system among Fig. 2 B contains one a serial-parallel converters 30 and a N system-binary decoder 100.Input V in each clock period
In31 have N kind state.Input V from m identical element
In31 are collected and convert to m parallel signal 32a, 32b...32m by serial-to-parallel converter 30, these signals are formed a word 32, and are sent to N system-binary decoder 100 to convert 38 (the comprising 38a, 38b...38i) of scale-of-two output of an i position to.Certainly, one contains electronic system parallel and the serial input and can realize by the design in conjunction with Fig. 2 A and Fig. 2 B.
The actual functional capability of N system-binary decoder is a binary number with the number conversion of a N system exactly.Based on N system logic, the number of bits i of m N system identical element representative is,
i≤INT[log
2(N
m)]
(INT[x] refer to maximum integer) less than x, its maximal value n is:
n＝i
max＝INT[log
2(N
m)]。
In this case, the N system-binary decoder 100 among Fig. 2 A and Fig. 2 B is one N * m-2 * n code translator, and it is converted to n binary digit with m N hex value.Fig. 2 C lists the relation of n and N, m, (is N=6, m=4) represents n=10 as 46 system identical elements.Compare therewith, in existing 2 quickflashing units (b=2), 44 system identical elements (are N=4, m=4) represent n=8, so the storage density of 6 system identical elements is high by 25%.
When product renewal, the present invention abandons b is added 1, and just N is added 1 (or more): as at b=2 (N=4) afterwards, the product of research and development of future generation is not b=3 (N=8), but N=5,6,7....Can make production development planning more real like this, reduce the research and development expense and shorten the R﹠D cycle.This method is obvious especially in b＞2 o'clock advantage.Because N no longer is 2 integer power, identical element position b, the number of bits of promptly average each identical element representative,
b≡n/m＝INT[log
2(N
m)]/m，
It is a non-integer.Fig. 3 represents for a plurality of N values, the relation of b and m.
For a given N, identical element position b changes with the wide m of word.As for N=6, when m=1, b=2, promptly per 2 identical elements are represented 4; When m=2, b=2.5, promptly per 2 identical elements are represented 5 (Fig. 3).So with m=2 is the wide unit of word, storage density is bigger than m=1, and promptly the efficient of m=2 is higher.Correspondingly, the efficient of a N system system is defined as b and theoretical limit b thereof
LimitThe ratio:
β≡b/b
limit＝{INT[log
2(N
m)]/m}/{log
2(N
m)/m}
＝INT[log
2(N
m)]/log
2(N
m)。
Fig. 4 A represents for a plurality of N values, the relation of β and m.As can be seen from Figure 4A, for m=1, the β of most of N is lower, so conventional, be that the decoded mode of unit (m=1) is not suitable for the non-integer system with the position.For a non-integral bit system,, be not that all N system states all are utilized (as last 4 row among Fig. 9 AB) in N system-binary decoding process, so β can not reach 100% (Fig. 4 A) because N is not 2 integer power.In order to guarantee β 〉=90%, m need satisfy certain condition, as: work as N=5, m 〉=4; Work as N=6, m 〉=2; Work as N=7, m 〉=3... (Fig. 4 B).On the other hand, can also select the m value to make β reach local maximum, as work as N=7, m preferably gets one of following value: 5,10,15,20,25,31 etc. (Fig. 4 B).
Fig. 5 represents a specific embodiment of the parallel input system of N system non-integral bit.Each N system identical element (as 10a) links to each other with an identical element scrambler (as 14a), and the output of this identical element scrambler 14a contains j position binary code 12a.Because the status number (2 of this j position binary code 12a representative
j) greater than the status number (N) of identical element 10a, so it is called as like binary code.Comprise thermometer-code (Fig. 9 AB) and accurate binary code (Fig. 9 BB) like binary code.Thermometer-code and accurate binary code are used j=N-1 and j=k={INT[log respectively
2(N)]+1} position binary code represents N kind state.
Fig. 6 A is a symbol of thermometer encoder, and its input 11a is the readout of identical element 10a; Output is thermometer-code 12a.Fig. 6 B is first embodiment of thermometer encoder 14a, and it contains a sensor amplifier 13a and N-1 latch 16a1,16a2...16a (N-1).In this embodiment, identical element 10a one has N Vt value (as V
T, 1＜V
T, 2＜V
T, 3＜...＜V
T, N) quickflashing unit, its state can be read in N-1 read cycle.In each read cycle, read voltage V for one
RBe added on the word line 11x: if it is greater than Vt, bit line 11a electromotive force is dragged down, and sensor amplifier 13a is output as " 0 "; If less than Vt, bit line 11a electromotive force continues as height, and sensor amplifier 13a is output as " 1 ".V
RBe added on the word line 11x with following order: V
R, (N-1)... V
R, 2, V
R, 1(note V
T, N＞V
R, (N-1)＞V
T, N-1＞...＞V
T, 3＞V
R, 2＞V
T, 2＞V
R, 1＞V
T, 1).Latch 16a1,16a2...16a (N-1) form a shift register, and by read cycle signals 17 controls.After N-1 read cycle, the output 12a of these latchs (comprising 12a1,12a2...12a (N-1)) forms a thermometer-code.For example, work as N=5, if the Vt=V of identical element
T, 3, output 12a then is: 0 (12a4), 0 (12a3), 1 (12a2), 1 (12a1); If Vt=V
T, 5, output 12a then is: 1 (12a4), 1 (12a3), 1 (12a2), 1 (12a1) (Fig. 9 AB).Because these output 12a looks like the mercury slug in the thermometer, promptly mercury slug only rises to suitable temperature, does not have mercury more than the temperature at this, so it is called as thermometer-code.
Fig. 6 C is second embodiment of thermometer encoder 14a.It continues to use the framework of quickflashing simulation-number conversion (flash ADC), promptly is made up of N-1 comparer 15a1,15a2...15a (N-1).In this embodiment, identical element 10a is regarded as a resistive element when reading, and this resistance has N resistance value, so its bit-line voltage 19 can have N value (as V
B, 1＜V
B, 2＜V
B, 3＜...＜V
B, N).The reference voltage V of comparer
Ref, 1, V
Ref, 2... V
Ref, (N-1)Satisfy following relation: V
B, 1＜V
Ref, 1＜V
B, 2＜V
Ref, 2＜V
B, 3...＜V
B, (N-1)＜V
Ref, (N-1)＜V
B, NWhen reading, bit-line voltage 19 and all reference voltage V
Ref, 1, V
Ref, 2... V
Ref, (N-1)Relatively, gained output 12a also is a thermometer-code.
Except thermometer-code, identical element scrambler 14a also can use accurate binary code.To same N system number, the value of accurate binary code identical with the normal binary sign indicating number (Fig. 9 BB).Compare with thermometer-code, the position that it needs is less.Fig. 7 A represents a kind of accurate binary coder 14a.It contains a thermometer encoder 21 (Fig. 6 A-6C) and a thermometer-code-accurate binary code converter 23.This converter 23 converts thermometer-code 25a (N-1 position) to accurate binary code 12a (k position).Fig. 7 B represents its embodiment, and it is 1
k-k priority encoder 25 (priority encoder).This priority encoder is widely used in quickflashing ADC.Because 2
k＞N, only the input 25a (2 of some priority encoder 25
k) link to each other with the output (N-1) of thermometer encoder 21.
Fig. 8 represents a specific embodiment of N system non-integral bit serial input system.Compare with Fig. 2 B, between input 31 and serial-to-parallel converter 30, also contain an identical element scrambler 34.This identical element scrambler 14a will import V
In31 N kind state is converted into the seemingly binary code 33 of a j position.For thermometer-code, j=N-1; For accurate binary code, j=k={INT[log
2(N)]+1}.In addition, serial-to-parallel converter 30 can adopt the serial-to-parallel shift register.
Fig. 9 AA-Fig. 9 C represents the embodiment of several N system-binary decoders.Fig. 9 AA is first embodiment of 6 * 2-2 * 5 code translators, and it converts 26 system inputs 12a (being A), 12b (being B) to one 5 binary code 18 (being C).Its input A, B adopt thermometer-code, (=6-1) individual signal (12a1,12a2...12a5, i.e. A1, the A2...A5 that promptly use 5; Or 12b1,12b2...12b5, i.e. B1, B2...B5) represent one 6 system number.Fig. 9 AB is the truth table of this embodiment, and as for A=1, B=4, its thermometer-code is " 00001 " and " 01111 "; Output C=14
6=10=01010
2(subscript " 6 " expression one 6 system numbers; As not marking, then be 10 systems).Notice, because 26 system numbers can represent 6
2(=36) kind state, and 5 bits can only represent 2
5(=32) kind state, this code translator have 4 not use state (last 4 row of Fig. 9 AB).
Fig. 9 BA is second embodiment of 6 * 2-2 * 5 code translators, and its input A, B adopt accurate binary code, promptly use 3 (=INT[log
2(6)]+1) individual signal (12a1,12a2,12a3, i.e. A1, A2, A3; Or 12b1,12b2,12b3, i.e. B1, B2, B3) represent one 6 system number.Fig. 9 BB is the truth table of this embodiment: as for A=1, B=4, accurate binary code is " 001 " and " 100 "; Output C=14
6=10=01010
2
N system-binary decoder of Fig. 9 AA and Fig. 9 BA is the customization code translator, and it generally is applicable to fixing N, and this method is called as hard decoding.On the other hand, soft decoding uses the method for software to realize decoding.For realizing soft decoding, the present invention proposes a kind of N system-binary decoder 102 able to programme, and it contains a general processor 104 and a program 106 (Fig. 9 C).Under this program 106 (can be software or firmware) control, this processor 104 can be realized the truth table among Fig. 9 AB (or Fig. 9 BB).For different N values, distinct program 106 is uploaded in the processor 104, with the different N system-binary decoding of reality.N system-binary decoder 102 able to programme can be positioned on the chip or chip outer (promptly decipher at system level and realize); It can with other parts (as the controller of flash memory or disk drive) shared processing device of system, thereby reduce system cost.
Figure 10 represents a kind of unit array 50 of the N of containing system identical element.Its bit line is divided into a plurality of word 52A, 52B...52X (each word contains the m bit lines), and column address decoder 51 is selected required word 54S by column address 53 from these words.This selected word 54S is sent to identical element scrambler 14a, 14b...14m earlier, is sent to N system-binary decoder 100 then to be converted into scale-of-two output 18 (n positions).Because N system-binary decoder 100 is positioned at after the column address decoder 51, it can be shared by a plurality of words in this unit array 50, thereby helps to reduce chip area.In fact, N system-binary decoder 100 can also be shared by different units array or different chips are shared.It can be positioned on the chip, chip is outer or a part on chip, a part is outside chip.
Though above instructions has specifically described examples more of the present invention, those skilled in the art should understand, under prerequisite not away from the spirit and scope of the present invention, can change form of the present invention and details, this does not hinder them to use spirit of the present invention.Therefore, except the spirit according to additional claims, the present invention should not be subjected to any restriction.
Claims (10)
1. non-integral bit system is characterized in that containing:
First word and second word, described first word and second word all contain m N system identical element, and each N system identical element has N kind state, and wherein, m, N are positive integer;
A word is selected in one system of selection, this system of selection from described first and second words;
One N system-binary decoder, this N system-binary decoder is converted into i position binary code with described selecteed word, and wherein, i is a positive integer, its maximal value n=INT[log
2(N
m)], INT[x] expression is less than the maximum positive integer of x;
Wherein, the average figure place b of the binary code of storing in each N system identical element is a non-integer, and greater than 2.
2. non-integral bit system according to claim 1, its feature also is: described two words are positioned at same unit array or different units array or different chip.
3. non-integral bit system according to claim 1, it is characterized in that also containing: a plurality of identical element scramblers, each identical element scrambler converts the readout of an identical element to just like binary code, and the input of described N system-binary decoder comprises a plurality of like binary code.
4. non-integral bit system according to claim 3, its feature also is: described is thermometer-code or accurate binary code like binary code.
5. non-integral bit system according to claim 1, its feature also is: can select m to make efficient β=INT[log
2(N
m)]/log
2(N
m) 〉=90%.
6. non-integral bit system according to claim 6, its feature also is:
A) when N=5, m 〉=4;
B) work as N=7,11,15 o'clock, m 〉=3;
C) work as N=6,12,13,14 o'clock, m 〉=2; Or
D) work as N=9,10 o'clock, m 〉=1.
7. non-integral bit system according to claim 1, its feature also is: can select m to make efficient β=INT[log
2(N
m)]/log
2(N
m) reach local maximum.
8. non-integral bit system according to claim 7, its feature also is:
A) when N=5, m=4,7,10,13,16,19,22,25,28 or 32;
B) when N=6, m=2,4,7,9,12,14,16,19,21,24,26,28 or 31;
C) when N=7, m=5,10,15,20,25 or 31;
D) when N=9, m=6,12,18,24 or 30;
E) when N=10, m=4,7,10,13,16,19,22,25 or 28;
F) when N=11, m=3,5,7,9,11,14,16,18,20,22,24,27,29 or 31;
G) when N=12, m=2,4,7,9,12,14,16,19,21,24,26,28 or 31;
H) when N=13, m=3,6,10,13,16,20,23,26 or 30;
I) when N=14, m=5,10,15,20,25 or 31; Or
J) when N=15, m=10,21 or 32.
9. non-integral bit system according to claim 1, its feature also is: described non-integral bit system is a parallel input system, a serial input system, semiconductor storer, a video disc driver or a data transmission system.
10. non-integral bit system according to claim 1, its feature also is: described code translator is positioned at same chip or different chip with described word.
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|---|---|---|---|
| US55968304P | 2004-04-04 | 2004-04-04 | |
| US60/559,683 | 2004-04-04 | ||
| US60/594,141 | 2005-03-14 |
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