CN100556228C - Printed circuit board (PCB) - Google Patents
Printed circuit board (PCB) Download PDFInfo
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- CN100556228C CN100556228C CNB2005800433365A CN200580043336A CN100556228C CN 100556228 C CN100556228 C CN 100556228C CN B2005800433365 A CNB2005800433365 A CN B2005800433365A CN 200580043336 A CN200580043336 A CN 200580043336A CN 100556228 C CN100556228 C CN 100556228C
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Abstract
The invention provides a kind of printed circuit board (PCB), alternately laminated insulating barrier and conductor circuit form, each conductor circuit has the square-section, wherein, the conductor circuit upside in the interval between the adjacent conductor circuit is made as W1 at interval, when the conductor circuit lower face side is made as W2 at interval, these at interval with the relation of conductor circuit thickness T satisfy 0.10T≤| W1-W2|≤0.73T.According to such formation, even carried, also can suppress cross-talk and signal delay by the IC of high-speed driving, prevent the misoperation of IC.
Description
Technical field
Even the present invention relates to a kind of printed circuit board (PCB) that the IC that has carried high-speed driving also can not produce the fine Wiring structure of the misoperation that is caused by cross-talk, signal transferring lag etc. that has.
Background technology
The lamination type printed circuit board (PCB) is the example as the printed circuit board (PCB) that is formed by fill insulant between conductor circuit.Such printed circuit board (PCB) is for example to replace laminated conductor circuit and interlayer resin insulating layers on core substrate, and the conductor circuit that is positioned at lower floor is electrically connected by so-called via with the conductor circuit that is positioned at the upper strata.This via makes the interlayer resin insulating layers opening and at its opening plated film is set and forms (reference Japanese publication communique 11-176985 number or Japanese publication communique 11-243279 number).
In such printed circuit board (PCB), be filled with the interlayer insulating film that constitutes by dielectric in the gap between the wiring pattern that constitutes each conductor circuit, it is essentially rectangular that each wiring pattern forms its cross sectional shape.
But, in the high-speed drivingization of IC with carry in the process that the fine cloth linearize of the printed circuit board (PCB) of such IC develops simultaneously, can there be the situation that causes IC generation misoperation because of cross-talk, signal delay in the printed circuit board (PCB) with the following fine wiring pattern of minimum conductor width L/ minimum interval S=15/15 μ m.
Summary of the invention
The objective of the invention is to solve the problems referred to above point of conventional art, even a kind of printed circuit board (PCB) that minimum conductor width L/ minimum interval S miniaturization also can be suppressed cross-talk, signal delay is provided.
The inventor has carried out research with keen determination for achieving the above object and repeatedly, and it is the invention of main composition that the result has finished with following content.
Promptly, printed circuit board (PCB) of the present invention, be that fill insulant forms between conductor circuit, it is characterized in that, the cross sectional shape of above-mentioned conductor circuit is essentially trapezoidal, with in the interval between the adjacent conductor circuit, the conductor circuit upper surface side is made as W1 at interval, when the conductor circuit lower face side is made as W2 at interval, these satisfy the requirement of following formula at interval with the relation of the thickness T of conductor circuit:
0.10T≤|W1-W2|≤0.73T......(1)。
Adopt such structure, when the thickness with conductor circuit is made as T, at the absolute value of conductor circuit upside interval W 1 with the difference of conductor circuit downside interval W2 | W1-W2| is under the situation of 0.10T～0.73T, because the relative sidewall of adjacent conductor circuit is not parallel mutually, therefore can reduce the capacitance between the adjacent conductor circuit.Therefore, also can suppress cross-talk, signal delay even carried the IC of high-speed driving.
In addition, in the present invention, the meaning of " cross sectional shape of conductor circuit is essentially trapezoidal " is meant, do not think just that the bight of conductor circuit upside is geometric acute angle or obtuse angle, also comprise the situation that has circular shape a little, or the hypotenuse of conductor circuit is not straight line and some situations of curve a little, or in the whole situation that has circular shape a little of the upper surface of conductor circuit, or on the upper surface of conductor circuit and/or inclined-plane, be formed with situation by the irregular concavo-convex roughening face that constitutes, be that the cross sectional shape of visually regarding as conductor circuit is not rectangle but wholely is the trapezoidal meaning.
In the present invention, conductor circuit preferably forms by additive process (full additive method, semi-additive process), also can wait by evaporation and form conductor circuit.
At this, for example Japanese kokai publication hei 06-57453 communique is disclosed like that, on substrate, formed the resist layer that resin molding by fluidity against corrosion etc. constitutes, and by exposure, develop and formed after the desired corrosion-resisting pattern, the metal level part on the position that does not form resist layer is removed in dissolving, peel off resist layer again, thereby obtain being in metal level part under the resist layer as the conductor circuit of desired pattern, wherein, aforesaid substrate is to form by formed the metal level that is made of the coat of metal or metal forming on the surface of basis material, and the present invention does not comprise by such metal covering etch, the conductor circuit (with reference to Fig. 1 of Japanese kokai publication hei 06-57453 communique) that indentation (tenting) method etc. forms.The conductor circuit that forms by such method is to remove the metal level that exposes in the part that does not form resist layer by etching to form, but since just with the direction of the Surface Vertical of basis material on, also etched in the horizontal direction, so the sectional area of conductor circuit diminishes.As a result, compare with the conductor circuit that forms by additive process, it is big that conductor resistance becomes.
Above-mentioned " the conductor circuit upside is W1 at interval " is meant, when the bight of conductor circuit upside is considered to geometric acute angle or obtuse angle, it is defined as the distance between the adjacent conductor circuit upper end, and " the conductor circuit downside is spaced apart W2 " is defined in the distance between the bottom of 2 relative on the vertical cross-section of conductor circuit adjacent each other hypotenuses.
In addition, in above-mentioned bight is to have a little under the situation of circular shape, above-mentioned W1 is defined as: on the vertical cross-section of conductor circuit adjacent each other, and the distance between the extended line of the straight line portion of 2 relative hypotenuses and the extended line of top line part intersect 2; Have a little under the circular situation in that the upper surface of above-mentioned conductor circuit is whole, above-mentioned W1 is defined as: on the vertical cross-section of conductor circuit adjacent each other, the extended line separately of 2 relative hypotenuses with and the tangent and parallel straight line in circular summit intersect 2 with circuit board between distance.
In addition, under the situation that has formed the roughening face on the upper surface of above-mentioned conductor circuit and/or the inclined-plane, the concavo-convex ummit line that becomes the roughening face can be considered as the top of conductor circuit and/or hypotenuse and above-mentioned W1 and W2 are carried out approximate calculation.
In the present invention, for | W1-W2|, its preferable range is 0.10T～0.35T, and more preferably scope is 0.35T～0.73T.In addition, conductor circuit lower face side W2 at interval is preferably below the 15 μ m, | the standard deviation of W1-W2| is preferably below (0.04T+2).
And, in the present invention, the roughening layer is set on the surface of conductor circuit preferably.
Description of drawings
Fig. 1 (a)～(e) is the figure of a part of the operation of the expression multilayer board of making embodiments of the invention 1.
Fig. 2 (a)～(d) is the figure of a part of the operation of the same expression multilayer board of making embodiments of the invention 1.
Fig. 3 (a)～(c) is the figure of a part of the operation of the same expression multilayer board of making embodiments of the invention 1.
Fig. 4 (a)～(c) is the figure of a part of the operation of the same expression multilayer board of making embodiments of the invention 1.
Fig. 5 (a)～(d) is the figure of a part of the operation of the same expression multilayer board of making embodiments of the invention 1.
Fig. 6 (a)～(d) is the figure of a part of the operation of the same expression multilayer board of making embodiments of the invention 1.
Fig. 7 (a)～(d) is the figure of a part of the operation of the same expression multilayer board of making embodiments of the invention 1.
Fig. 8 is the figure of the multilayer board of expression embodiments of the invention 1.
Fig. 9 is illustrated in the figure that the state of IC chip has been installed on the multilayer board of embodiments of the invention 1.
Figure 10 is the skeleton diagram that is used to illustrate the cross sectional shape of the conductor circuit on the printed circuit board (PCB) of the present invention.
Figure 11 is used to illustrate the skeleton diagram of preferred embodiment of the cross sectional shape of the conductor circuit that is formed by additive process.
Embodiment
As shown in Figure 1, printed circuit board (PCB) of the present invention is a fill insulant between conductor circuit, and each conductor circuit has, and the trapezoidal cross-sectional shape of being essentially forms, it is characterized in that, be made as W1 at interval at conductor circuit upside with the interval between the adjacent conductor circuit, when the conductor circuit lower face side is made as W2 at interval, these at interval with the relation of the thickness T of conductor circuit satisfy 0.10T≤| W1-W2|≤0.73T.
Why such the thickness T that comprises conductor circuit in the relational expression be because the thickness T of conductor circuit exerts an influence to the capacitance between the adjacent conductor circuit.Not parallel and with the state that tilts under the relative situation at the relative sidewall of adjacent conductor circuit, with relative sidewall is that parallel situation is compared, capacitance between the conductor circuit reduces, but if | W1-W2| is in the scope of 0.10T～0.73T, also is difficult to produce misoperation even then carried the above IC of 2.6GHz.
On the other hand, | during W1-W2| deficiency 0.10T,, be unfavorable for that then high speed signal transmits because the electric capacity quantitative change between the adjacent conductor circuit is big, | when W1-W2| surpasses 0.73T, be easy to generate signal delay.Tracing it to its cause, is that result, the resistance value of conductor circuit become big and be unfavorable for that high speed signal transmits because along with trapezoidalization of the cross sectional shape of conductor circuit, the conductor volume reduces.
| the more preferably scope of W1-W2| is 0.35T～0.73T, and optimum range is 0.10T～0.35T.When being in this scope, also can guarantee sufficient conductor volume even have the following conductor circuit of L/S=12.5/12.5 μ m.In addition, the capacitance between the conductor circuit also can diminish.
In the present invention, on the big more this point of capacitance (static capacity) between the thin more conductor circuit of the L/S of conductor circuit, have, but the L/S of conductor circuit preferably is in the scope of 5/5 μ m～15/15 μ m than significant meaning.
Its reason is because under the situation of L/S less than 5 μ m/5 μ m, and the conductor volume is too small and the resistance value of conductor circuit is risen, and the result can produce signal delay.On the other hand, when L/S surpasses 15/15 μ m,, therefore be difficult to produce the cross-talk noise because the static capacity that the space between the holding wire becomes between the big and adjacent conductor circuit diminishes.
In the present invention, the thickness of conductor circuit is preferably 5～25 μ m.Its reason is because under the situation of thickness less than 5 μ m, it is big that the resistance value of conductor circuit becomes, on the other hand, when thickness surpasses 25 μ m, because the electric capacity quantitative change is big, therefore be unfavorable for that high speed signal transmits, when having carried the IC chip more than the 2.6GHz, be easy to generate misoperation.
Usually, printed circuit board (PCB) comprises a plurality of products, constitute by the sheet that for example is of a size of 340 * 510mm, in the present invention, in 1 goods | the standard deviation of W1-W2| (by 1 goods is divided into 4 parts, and randomly draws the standard deviation that the data (section after cutting apart respectively extracts 2 data) at 8 positions calculate each section after this is cut apart and represent) is preferably (below 0.04 * T+2) with the relation of the thickness T of conductor circuit.
In the time of within this scope, because the transfer rate of each holding wire is constant, it is poor therefore can not to produce transfer rate between each holding wire.On the other hand, surpass in | the standard deviation of W1-W2| that (0.04 * T+2) time, the transfer rate difference on each holding wire becomes big and is easy to generate misoperation.
In addition, preferably on the sidewall at least of conductor circuit, be formed with the roughening face in the present invention.When having the roughening face, the surface area of conductor circuit sidewall enlarges markedly.Because it is the capacitance between the conductor circuit also increases thereupon, therefore better to the printed circuit board applications effect when of the present invention that has the roughening face at the conductor circuit sidewall.The roughening face is not special to be limited, and can pass through formation such as etch processes such as melanism, built-in inserted plate, Cz processing.
In addition, shown in Figure 11 summary, in the present invention, for the conductor circuit that forms by additive process, 4 summit A, B on the cross section that will link conductor circuit, the trapezoidal area of C, D are made as S
0, the sectional area of conductor circuit is made as S
1The time, also 0.8≤S preferably
1/ S
0≤ 1.2.Its reason is because if be in this scope, then make conductor circuit remain low resistance and also can make conductor circuit broad at interval.
Below, describe multilayer board of the present invention and manufacture method thereof in detail based on embodiment.
(A) contain the making of the mixing thing of flakey particle
In the mixed solvent of 20g butanone (below be called " MEK ") and 80g dimethylbenzene, add 15g flakey particle (ホ of Co., Ltd. one ジ ユ Application (HOJUN) society system, trade name " エ ス ベ Application C ", the asperratio when disperseing :～500, crystal size :～0.5 μ m), and carry out mixing and make the mixing thing that contains the flakey particle with three rollers.
(B) contain the making of the solution of epoxy resin
In the mixed solvent of 6.8gM EK and 27.2g dimethylbenzene, add mixing 85g solid epoxy resin (ジ ヤ パ Application エ Port キ シ レ ジ Application (JAPANEPOXYRESIN) society system, trade name " エ ピ コ one ト 1007 ") and make the solution that contains epoxy resin.
(C) the interlayer insulating film making of resin molding
With the mixing thing that contain flakey particle of three rollers in above-mentioned (A), producing, the solution of in above-mentioned (B), producing that contains epoxy resin, dicyandiamide (PVC イ テ イ ア イ ジ ヤ パ Application (BTA JAPAN) society's system as curing agent, trade name " CG-1200 ", amount with respect to the solid epoxy resin of every 100g is 3.3g), (four countries change into society's system to curing catalysts, trade name " キ ユ ア ゾ one Le 2E4HZ ", amount with respect to the solid epoxy resin of every 100g is 3.3g) carry out the mixing adhesive solution that obtains.
Use glue spreader (サ one マ ト ロ ニ Network ス (CERMATRO NICS) trade society system) that this adhesive solution is coated on the sheet of PETG, afterwards, heat drying 5 minutes under 160 ℃ condition and remove and to desolvate, thus produce the insulating film that thickness is 40 μ m.
When using Clairvoyant type electron microscope (50,000～100,000 times) to observe the flakey particle that this dielectric film contains, because the minimum crystal size (any less side in the minimum widith of particle or the minimum length) when disperseing is 0.1 μ m, so the asperratio of the flakey particle in the present embodiment is 100～500.
(D) manufacturing of multilayer board
Manufacture method with reference to Fig. 1～Fig. 8 explanation multilayer board as shown in Figure 9.
(1) forms the core metal layer
At first, on being the metallic plate 10 of 50～400 μ m, the thickness shown in Fig. 1 (a) is provided with the opening 12 (Fig. 1 (b)) at the perforation table back side.The material of this metallic plate can adopt alloy of metals such as copper, nickel, zinc, aluminium, iron or these metals etc.At this,, therefore can reduce thermal stress owing to when adopting 36 lower alloys of thermal coefficient of expansion or 42 alloys, can make the thermal coefficient of expansion of the thermal coefficient of expansion of core substrate near IC.
Utilize punching, etching, boring, laser etc. to wear above-mentioned opening 12, on the whole plane of the metal level 10 that comprises this opening 12, make core metal layer (Fig. 1 (c)) by covering metal films 13 such as metallide, electroless plating, displacement plating, sputters.
In addition, metallic plate 10 can be an individual layer, also can be the multilayer more than 2 layers.
In addition, preferably implement chamfer machining, make this bight become curved surface in the bight of being located at the opening 12 on the metallic plate 10.Thus, do not crack owing to not having the concentrated point of stress, therefore can being suppressed on the corner periphery.
(2) insulating barrier and the conductor layer of formation internal layer
Form to cover whole metal level 10 and bury the such resin insulating barrier 14 of opening 12, and on this resin insulating barrier 14, form conductor layer 15.On this metal level 10, be provided with above-mentioned opening 12.
As the material that forms this insulating barrier, can adopt heat-curing resin such as polyimide resin, epoxy resin, phenolic resins, BT resin or use the pre-soaked resin sheet etc. on the B rank that this heat-curing resin that infiltrated forms in cores such as glass fabric, aromatic polyamide nonwoven fabrics.
Specifically, to infiltrate at glass fabric, epoxy resin forms, thickness be pre-soaked resin sheet about 30～200 μ m with the state configuration that covers metal film 13 on the two sides of metallic plate 10, and after the stacked thickness in the outside of this pre-soaked resin sheet is the metal formings such as copper of 12～275 μ m, carry out heating and pressurizing from this metal forming, thereby the resin that makes the pre-soaked resin sheet is filled in the opening 12, and pre-soaked resin sheet and metal forming are crimped under the state on the two sides of covered metal plate 10 and form one, have formed the insulating barrier 14 and the conductor layer 15 (Fig. 1 (d)) of internal layer thus.
The method that the insulating barrier 14 of above-mentioned internal layer also can come filling opening 12 by application of resin liquid on the two sides of metal level 10, or on the basis of application of resin liquid is further carried out heating and pressurizing to resin molding and is made its crimping and form on the two sides of metal level 10.
The conductor layer 15 that is located on the insulating barrier 14 of above-mentioned internal layer is formed by metal forming, but also can increase thickness and formed by the metal level more than 2 layers by metallide or electroless plating etc.
(3) form the inner conductor circuit
Above-mentioned inner conductor layer 15 is implemented to adopt the etch processes of indentation method, and formed the conductor circuit 16 (Fig. 1 (e)) of the internal layer that constitutes by bus plane 16P and ground plane 16E.
The thickness of these inner conductor circuit 16 preferably is in the scope of 10～250 μ m, more preferably is in the scope of 30～100 μ m.Its reason be because, under the situation of thickness less than 10 μ m, the resistance of conductor is excessive, can not instantaneous supply power when the voltage of IC descends, the driving voltage that promptly can not instantaneous time returns to IC, on the other hand, when thickness surpasses 250 μ m, owing to position that forms the loop and the concavo-convex influence that does not form the position in loop make the in uneven thickness of interlayer insulating film.In addition, because therefore circuit board thickness thickening can not reduce loop inductance.
In this embodiment, the thickness with the inner conductor circuit is made as 60 μ m.
In addition, when the power supply that is electrically connected at the power supply with electronic unit such as IC runs through ground plane 16E with through hole, preferably do not have from power supply with the extended wiring pattern of through hole.Equally, when the earthy through hole that is electrically connected with the earth connection of the electronic unit of IC etc. runs through bus plane 16P, preferably do not have from the extended wiring pattern of earthy through hole.
Can dwindle through-hole spacing by making such structure.In addition, owing to the interval that can dwindle between through hole and the inner conductor circuit, therefore can reduce mutual mutual inductance.
In addition, the conductor circuit of internal layer forms by etch processes, but also can form by additive process.
(4) form outer field insulating barrier and conductor circuit
Identical with above-mentioned (2), be formed for the resin insulating barrier 18 that covers the conductor circuit of internal layer and bury the slit between this loop, and on this resin insulating barrier 18, formed outer field conductor circuit 20.
Specifically, to form at the glass fabric epoxy resin that infiltrated, thickness is that the pre-soaked resin sheet about 30～200 μ m is configured on the two sides of the substrate that forms in above-mentioned (1)～(3), and after the stacked thickness in the outside of this pre-soaked resin sheet is the metal formings such as copper of 12～275 μ m, carry out heating and pressurizing from this metal forming, thereby the resin that makes the pre-soaked resin sheet is filled between the conductor circuit, and pre-soaked resin sheet and metal forming are crimped under the state on the two sides that covers conductor circuit 16 and form one, have formed outer field insulating barrier 18 and outer field conductor circuit 20 (Fig. 2 (a)) thus.
Identical with the insulating barrier 14 of internal layer, above-mentioned outer field insulating barrier 18 also can by cover the inner conductor circuit at application of resin liquid on the two sides of substrate and to conductor circuit between the method for filling, or on the basis of application of resin liquid, further resin molding is carried out heating and pressurizing and make its crimping and form.In addition, in the method for such heating and pressurizing, can make surface of insulating layer smooth.
In addition, in the present embodiment, be insulating barrier 14 and the conductor circuit that metallic plate 10 is formed internal layer as core body on its two sides, and further form outer field insulating barrier 18 and outer field conductor circuit 20, but might not also can form core substrate with metallic plate 10 as core body by the stacked member that has formed the loop on the single or double copper clad laminate.
(5) form the electroplating ventilating hole through hole
Form to connect formation in above-mentioned (4) core substrate, opening diameter is the through hole 21 (Fig. 2 (b)) of 50～400 μ m.This through hole 21 be located at metallic plate 10 on the corresponding formation in position of opening 12, by boring processing or laser processing or use laser processing simultaneously and boring processing forms.The shape of this through hole preferably has the structure of linearity sidewall, also can do tapered as required.
(6) form electroplating ventilating hole
In order to apply conductivity on the sidewall to the through hole 21 of formation in above-mentioned (5), on sidewall, form plated film 22 and make (Fig. 2 (c)) after the surface roughening of this plated film 22, potting resin packing material 24 in through hole, thus electroplating ventilating hole 26 (Fig. 2 (d)) formed.
For the resin filling materials 24 that is filled in this through hole 21, preferably after interim drying with it, remove attached to the unnecessary resin filling materials on the plated film 22 of substrate surface by grinding, and further under 150 ℃ condition dry 1 hour, thereby make its full solidification.
Form above-mentioned plated film 22 by metallide or electroless plating, distribution panelboard plating (electroless plating and metallide) etc., this plated metal has adopted the metal that contains copper, nickel, cobalt, phosphorus etc.
In addition, the thickness of plated film 22 is preferably the scope of 5～30 μ m.
As above-mentioned resin filling materials 24, adopt and for example in resin material, to contain the insulative resin material of curing agent, particle etc., or in resin material, contain any material in the electroconductive resin material of metallics such as gold, copper, curing agent etc.
As the resin of above-mentioned insulative resin material, for example adopted the heat-curing resin of epoxy resin such as bisphenol-type epoxy resin, novolac epoxy resin, bisphenol resin etc., had photosensitive ultraviolet curable resin or thermoplastic resin etc.These resin materials can adopt the resin of single kind, or the material that also can adopt multiple these resins compound and form.
As above-mentioned particle, metallics such as inorganic particulates such as silicon dioxide, aluminium oxide, gold, silver, copper or resin particle etc. have been adopted.These particles can adopt the particle of single kind, perhaps also can adopt and mix the material that multiple these particles form.
The particle diameter of above-mentioned particle preferably is in the scope of 0.1～5 μ m, can adopt the particle of same diameter or mix the material of the different particle of particle diameter.
As above-mentioned curing agent, can adopt imidazoles is that curing agent, amine are curing agent etc.In addition also can contain and solidify stabilizer, reaction stabilizer, particle etc.
In addition, as above-mentioned electroconductive resin material, adopted and in resinous principle, contained the conductive paste that metallic, curing agent etc. form.
In addition, also can replace conductive paste and electroplate filling through hole 21.When electroplating filling,, can on the top layer, not form recess along with cure shrinkage as conductive paste.
(7) the outer contact layer and the conductor circuit of formation core substrate
In above-mentioned (6), formed to cover on whole of two sides of substrate of electroplating ventilating hole 26 and formed plated film (Fig. 3 (a)) afterwards, the etch processes of indentation method has been adopted in enforcement, and above electroplating ventilating hole 26 and with it, closely form and cover coating 28, and formed the outer contact circuit 30 (Fig. 3 (b)) that constitutes by bus plane 30P and ground plane 30E.
The thickness of these outer contact circuit 30 preferably is in the scope of 10～75 μ m, more preferably is in the scope of 20～40 μ m.Its reason be because, under the situation of thickness less than 10 μ m, conductor resistance is bigger, when thickness surpassed 75 μ m, it was smooth to be difficult to make the interlayer insulating film that is formed on the core substrate to flatten, or substrate can thickening.In this embodiment, the thickness with outer contact circuit 30 is made as 35 μ m.
By the operation of above-mentioned (1)～(7), formed by electroplating ventilating hole 26 and the outer contact circuit 30 on substrate two sides is electrically connected mutually and also carries out the multilayer core substrate 32 that is electrically connected between inner conductor circuit 16 and the outer contact circuit 30 by electroplating ventilating hole 26.
(8) on outer conductor circuit, form the roughening layer
Carry out on the two sides of above-mentioned multilayer core substrate 32 that melanism is handled and reduction is handled, formed roughening layer 34 (Fig. 3 (c)) at the side and the upper surface (the terminal pad surface that comprises through hole) of outer field conductor circuit 30.
(9) potting resin packing material
Above-mentioned multilayer core substrate 32 outer field do not form conductor circuit the position, be to have filled resin filling materials 36 (Fig. 4 (a)) in the gap between the outer field conductor circuit.This resin filling materials can adopt and resin filling materials 24 identical materials that are filled in the operation of above-mentioned (6) in the through hole 21.
(10) grind outer contact circuit upper surface
Grind by the single face to the substrate having finished above-mentioned resin and fill such as belt mill, remove roughening layer in the roughening face 34 of the side of being located at outer contact circuit 30 and upper surface, that be located at upper surface, and make on the outer edge of conductor circuit 30 not cull packing material 36, then, in order to remove the scar that causes by above-mentioned grinding, further grind with the upper surface to outer conductor circuit 30 such as polishing wheel again.Another side to substrate carries out so a series of grinding similarly and makes it level and smooth.Then, carry out in heating 1 hour under 100 ℃ the condition, under 150 ℃ condition, heat 1 hour heat treated, make resin filling materials 36 solidify (Fig. 4 (b)).
In addition, can omit the step of the gap-filled resin packing material between outer conductor circuit as required, in this case, also can carry out the formation of interlayer insulating film simultaneously by the resin bed that is laminated in the interlayer insulating film on the multilayer core substrate and to the filling in gap between the outer conductor circuit.
(11) form the roughening layer at outer conductor circuit upper surface
With injector with etching solution spray to smoothing in above-mentioned (10) operation the surface (terminal pad that comprises through hole) of outer contact circuit 30P, 30E, thereby formed roughening layer 38 (Fig. 4 (c)) at the upper surface of outer conductor circuit.
(12) form interlayer resin insulating layers
On having formed the outer field conductor circuit surface of above-mentioned roughening layer 38, be positioned in the resin molding 40 that forms in above-mentioned (C), and it is carried out interim crimping come after the severing, adopt vacuum lamination apparatus that it is pasted again and pay to substrate surface, thereby formed interlayer resin insulating layers 42 (Fig. 5 (a)).
(13) form via formation opening
Then, on interlayer resin insulating layers across being formed with the mask that thickness is the through hole of 1.2mm, to use wavelength be the carbon dioxide laser of 10.4 μ m and be under the illuminate condition of through hole diameter as Φ 1.0～2.2mm, emission 1～3 time of 10～25 μ seconds, mask as 4.0mm, recessed cap head mould formula, pulse duration at beam diameter, and the via that has formed diameter and be 30～70 μ m on interlayer resin insulating layers 42 is with opening 44 (Fig. 5 (b)).
(14) form the roughening layer
To be provided with after the substrate 32 of above-mentioned via with opening 44 be immersed in the swelling liquid and it is washed, be immersed in 80 ℃ the solution of the permanganic acid that contains 60g/l 10 minutes, thereby the flakey particle in the cured resin that is scattered in interlayer resin insulating layers 42 is come off on the interlayer resin insulating layers surface, and formed roughening layer 46 (Fig. 5 (c)) on the surface of via with the interlayer resin insulating layers 42 of the inwall of opening 44 comprising.The roughness of this roughening layer 46 is 0.01～2 μ m.
(15) apply catalyst core
Then, impregnated in neutralization solution (シ プ レ イ (Shipley) society system) back at the substrate 32 that will finish above-mentioned processing washes it.Afterwards, also can pass through O
2Plasma or CF
4Implement to remove the decontamination of the residue of the resin that remains on the via bottom or particle handles Deng physical methods such as particles.
And, on the surface of this substrate that has passed through the asperities processing, apply palladium catalyst, catalyst core is used on the internal face of opening 44 attached to the surface and the via of interlayer resin insulating layers 42.
(16) form the electroless plating copper film
Then, the substrate 32 that will apply catalyst in the operation of above-mentioned (15) impregnated in following such electroless plating copper liquor of forming, and form thickness on the whole surface of roughening layer 46 is the electroless plating copper film 48 of 0.6～3.0 μ m, thereby has obtained the substrate (Fig. 5 (d)) that is formed with conductor layer on the surface of via with the interlayer resin insulating layers 42 of the inwall of opening 44 comprising.
(electroless plating copper solution)
Copper sulphate: 0.03mol/l
EDTA： 0.200mol/l
HCHO： 0.18g/l
NaOH： 0.100mol/l
α, α '-di-is given a tongue-lashing pyridine: 100mg/l
Polyethylene glycol: 0.10g/l
(plating condition)
Flooded 40 minutes with 34 ℃ fluid temperatures
(17) the photonasty alkali type etching ink of the liquid type of selling on coating market on the substrate that is formed with electroless plating copper film 48 (for example, sun printing ink society system, PER-20 series), make after its interim drying, on substrate the mounting mask and expose, development treatment, thereby be provided with the resistance coating 50 that thickness is 7.5～30 μ m (Fig. 6 (a)).In addition, the part that becomes holding wire afterwards forms L/S=5/5 μ m.
As resistance coating, the trade name that also can adopt for example ニ チ go one モ one ト Application (Nichigo-Morton) the society system except that above-mentioned is the photosensitive resin composition that " NIT225 " or " NIT215 " or Japanese publication communique 2004-317874 are put down in writing.
(18) then, substrate 32 is implemented metallide, having formed thickness at the position that does not form resistance coating 50 is the electrolytic copper plating film 52 (Fig. 6 (b)) of 7.5～17.5 μ m.In addition, carry out with following electroplate liquid and condition specifically, thereby obtained the electrolytic copper plating film of 7.5 μ m.
(electrolytic copper plating liquor)
Sulfuric acid: 2.24mol/l
Copper sulphate: 0.26mol/l
Additive: 19.5ml/l
(ア ト テ Star Network ジ ヤ パ Application (ATOTECH JAPAN) society's system, trade name: カ パ ラ シ De GL)
(metallide condition)
Current density: 1A/dm
2
Time: 35 ± 5 minutes
Temperature: 22 ± 2 ℃
(19) and, peel off removed resistance coating after, remove electroless plating film below this resistance coating with the dissolving of following engraving method, and made independent conductors circuit 54 and via 56 (Fig. 6 (c)).
In addition, signal routing is made L/S=5/5 μ m (L, S are the intervals on the interlayer insulating film), and make 5 holding wires in it form almost parallel, made the 1st, 3,5 signal routing and be connected, and the 2nd, 4 signal routing is not connected with IC and as measuring with wiring (test that is equivalent to be adopted in evaluation test 1 described later is with connecting up) with IC.
(engraving method)
The use in printed circuit board substrate is moved in the etch processes zone, and adopted and to have the conveyer belt carried in the etch processes zone and the level carrying Etaching device of injection nozzle carries out etching.The etching solution of from the above-mentioned injection nozzle that can adjust a plurality of spraying pressure, spraying out up and down from the use in printed circuit board circuit board.
In the present embodiment, for the shape that makes conductor circuit becomes trapezoidally,, the head of the straight moving type injection nozzle of gap nozzle etc. carries out etching while being shaken.
(etching condition)
Nozzle and workpiece interval: 50mm
Spraying pressure: 0.05MPa～0.3MPa
The kind of etching solution: copper chloride
Etch temperature: 45 ℃
Etching period: 10～60 seconds
For the adjustment of the cross sectional shape that forms by such etching condition, be to be undertaken by changing atomisation pressure or adjust etching period, only use arbitrary nozzle of being located at the nozzle on Etaching device top or being located in the nozzle of bottom.
In this embodiment, adopt gap nozzle, with etching period be made as 10 seconds, make etched facing up, only adopt the nozzle of being located at Etaching device top to carry out etching.Afterwards, be adjusted to below the 5 μ m (T) by the thickness with conductor circuit such as surface grinding.
(20) then, carrying out surface roughening (for example handles, handle by roughened or melanism that the etching of adopting メ Star Network (MEC) Co., Ltd. system, trade name " メ Star Network エ Star チ ボ Application De Cz-8100 " is carried out), thus roughening face 58 (Fig. 6 (d)) on the surface (comprising the side) of conductor circuit 54 and via 56, formed.
Afterwards, produce 1 identical substrate, and measure by correspondences such as punchings according to the operation of above-mentioned (1)～(20) | boring a hole in the position of W1-W2|, and makes test sample.
The conductor circuit and the vertical cross-section between the conductor circuit of this test sample are ground to form the degree that can observe, with 100～3500 times this means of abrasion is carried out SEM and taken pictures after observing, used scale to measure width W 1 (the conductor upper side at interval) and W2 (the conductor lower side at interval) between line after finishing.
The result, as shown in table 1, the data at 8 positions as described above (calculating the value at the identical position of the data of σ) with above-mentioned being used for | the value of W1-W2| is 0.5 μ m (minimum values of 8 data)～1.75 μ m (8 maximum in data), has satisfied the relation of (0.10 * conductor circuit thickness T)～(0.35 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.23 μ m.
(21) substrate that has formed roughening face 58 in above-mentioned (20) is repeated the operation of above-mentioned (12)～(20), formed the 2nd layer by layer between resin insulating barrier 60, and on this interlayer resin insulating layers 60, further form top conductor circuit 62 and via 64, thereby obtained multilayer circuit board (Fig. 7 (a)).
(22) form solder mask layer
Then, applied the solder resist constituent of selling on the market of 12～30 μ m thickness on the two sides of the multilayer circuit board that in above-mentioned (21), obtains, and heat 30 minutes conditions of 20 minutes, 70 ℃ heating with 70 ℃ and carry out dried, and formed solder mask layer 66 (Fig. 7 (b)).Afterwards, the thickness that makes the pattern of drawing the solder resist peristome is that the photomask of 5mm is close on the solder mask layer 66, and with 1000mJ/cm
2Ultraviolet ray expose, in DMTG solution, carry out development treatment, be 200 μ m openings 68 (Fig. 7 (c)) thereby formed diameter.
Then, carry out heat treated respectively and solder mask layer 66 is solidified with 3 hours conditions of 1 hour, 150 ℃ heating of 1 hour, 120 ℃ heating of 1 hour, 100 ℃ heating of 80 ℃ of heating again, formed that to have the surperficial such opening 68, the thickness that have exposed top conductor circuit 62 be the solder resist pattern of 10～25 μ m.
(23) form nickel-Jin layer
Then, the substrate that has formed the solder resist pattern is immersed in the electroless nickel plating solution, having formed thickness on the surface of the top conductor circuit 62 that exposes from opening 68 is the nickel coating of 5 μ m, again this circuit board be impregnated in the electroless gold plating solution, having formed thickness on nickel coating is the Gold plated Layer of 0.03 μ m, forms nickel-Jin layer 70 (Fig. 7 (d)).Except this nickel-Jin layer, also can form the tin or noble metal (gold, silver, palladium, the platinum etc.) layer of individual layer.
(24) form the soldering projection
Afterwards, the surface printing of the top conductor circuit 62 that exposes at the opening 68 from above-mentioned solder mask layer 66 of the one side side (IC chip installation side) of foregoing circuit plate contains the tinol of tin-lead, and same printing contains after the tinol of tin-antimony on the another side side, carry out Reflow Soldering and formed outside terminal with 200 ℃, thereby produce multilayer board (Fig. 8) with soldering projection 72.
By soldering projection 72 IC chip 74 is installed on above-mentioned multilayer board, and then chip capacitor 76 is installed.
Then, the multilayer board that IC chip 74 and chip capacitor 76 will be installed by outside terminal 78 is installed in (Fig. 9) on the motherboard 80.
Embodiment 2
The pattern that changes resistance coating forms uses mask, and changing the thickness of electrolytic copper plating condition and the adjusted conductor circuit of thickness and making the L/S of holding wire is that 7.5 μ m/7.5 μ m, conductor circuit thickness T are 7.5 μ m, in addition produces multilayer board in the same manner with embodiment 1.
In this embodiment, | the value of W1-W2| is 0.675 μ m～2.775 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.35 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.33 μ m.
Embodiment 3
The pattern that changes resistance coating forms uses mask, and changing the thickness of electrolytic copper plating condition and the adjusted conductor circuit of thickness and making the L/S of holding wire is that 10.0 μ m/10.0 μ m, conductor circuit thickness T are 10.0 μ m, in addition produces multilayer board in the same manner with embodiment 1.
In this embodiment, | the value of W1-W2| is 0.9 μ m～3.6 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.35 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.27 μ m.
Embodiment 4
The pattern that changes resistance coating forms uses mask, and changing the thickness of electrolytic copper plating condition and the adjusted conductor circuit of thickness and making the L/S of holding wire is that 12.5 μ m/12.5 μ m, conductor circuit thickness T are 12.5 μ m, in addition produces multilayer board in the same manner with embodiment 1.
In the present embodiment, | the value of W1-W2| is 1.25 μ m～4.375 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.35 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.34 μ m.
Embodiment 5
The pattern that changes resistance coating forms uses mask, and changing the thickness of electrolytic copper plating condition and the adjusted conductor circuit of thickness and making the L/S of holding wire is that 15.0 μ m/15.0 μ m, conductor circuit thickness T are 15.0 μ m, in addition produces multilayer board in the same manner with embodiment 1.
In the present embodiment, | the value of W1-W2| is 1.35 μ m～5.25 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.35 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.35 μ m.
Embodiment 6
Except etching period being changed to 30 seconds, all the other and embodiment 1 produce multilayer board in the same manner.
In the present embodiment, | the value of W1-W2| is 1.7 μ m～3.7 μ m, satisfies the relation of (0.35 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.77 μ m.
Embodiment 7
Except etching period being changed to 30 seconds, all the other and embodiment 2 produce multilayer board in the same manner.
In the present embodiment, | the value of W1-W2| is 2.475 μ m～5.475 μ m, satisfies the relation of (0.35 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.76 μ m.
Embodiment 8
Except etching period being changed to 30 seconds, all the other and embodiment 3 produce multilayer board in the same manner.
In the present embodiment, | the value of W1-W2| is 3.5 μ m～7.3 μ m, satisfies the relation of (0.35 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.78 μ m.
Embodiment 9
Except etching period being changed to 30 seconds, all the other and embodiment 4 produce multilayer board in the same manner.
In the present embodiment, | the value of W1-W2| is 4.25 μ m～9.25 μ m, satisfies the relation of (0.35 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.65 μ m.
Except etching period being changed to 30 seconds, all the other and embodiment 5 produce multilayer board in the same manner.
In the present embodiment, | the value of W1-W2| is 5.25 μ m～10.95 μ m, satisfies the relation of (0.35 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 1.72 μ m.
Embodiment 11
Except as change the engraving method followingly, all the other and embodiment 1 produce multilayer board in the same manner.
Different with embodiment 1, carried out 2 etchings.The 1st etching is identical with embodiment 1.Afterwards, in 4 zones (4 zones that are divided into for image data) that the quilt of 1 goods is partitioned into, wait 2 zones of covering with Kapton Tape (kapton tape).And, while being shaken the head, gap nozzle only unlapped part is carried out the etching in 20 seconds, peel off Kapton Tape etc. afterwards.In addition, the nozzle of use with etched towards identical with embodiment 1.
In the present embodiment, | the value of W1-W2| is 0.5 μ m～3.65 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 2.01 μ m.
Except engraving method being changed to the engraving method identical with embodiment 11, all the other and embodiment 2 produce multilayer board in the same manner.
In the present embodiment, | the value of W1-W2| is 0.675 μ m～5.625 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 2.13 μ m.
Except engraving method being changed to the engraving method identical with embodiment 11, all the other and embodiment 3 produce multilayer board in the same manner.
In the present embodiment, | the value of W1-W2| is 0.9 μ m～7.6 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 2.2 μ m.
Except engraving method being changed to the engraving method identical with embodiment 11, all the other and embodiment 4 produce multilayer board in the same manner.
In the present embodiment, | the value of W1-W2| is 1.25 μ m～9.25 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 2.45 μ m.
Except engraving method being changed to the engraving method identical with embodiment 11, all the other and embodiment 5 produce multilayer board in the same manner.
In the present embodiment, | the value of W1-W2| is 1.5 μ m～10.95 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.And, | the standard deviation of W1-W2| is 2.58 μ m.
Embodiment 16
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 1 produce multilayer board in the same manner.
In addition, after conductor circuit forms, W1 and W2 are measured.
Embodiment 17
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 2 produce multilayer board in the same manner.
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 3 produce multilayer board in the same manner.
Embodiment 19
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 4 produce multilayer board in the same manner.
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 5 produce multilayer board in the same manner.
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 6 produce multilayer board in the same manner.
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 7 produce multilayer board in the same manner.
Embodiment 23
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 8 produce multilayer board in the same manner.
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 9 produce multilayer board in the same manner.
Embodiment 25
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 10 produce multilayer board in the same manner.
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 11 produce multilayer board in the same manner.
Embodiment 27
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 12 produce multilayer board in the same manner.
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 13 produce multilayer board in the same manner.
Embodiment 29
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 14 produce multilayer board in the same manner.
Except not forming the roughening face 58 on the surface of conductor circuit 54 and via 56, all the other and embodiment 15 produce multilayer board in the same manner.
Reference example 1
Except the 2nd etching is not the etching of being undertaken by gap nozzle, but with etching solution that the 1st time etching is identical in outside the dipping 1 minute, all the other and embodiment 14 produce multilayer board in the same manner.
In this reference example, | the value of W1-W2| is 1.25 μ m～9.25 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.But in the present embodiment, owing to adopted the immobilising dipping etching of etching solution simultaneously, so etching speed has than big-difference with the position is different, the result, and loop shape of each wiring differs bigger, therefore | the standard deviation of W1-W2| is 2.58 μ m.
Reference example 2
Except not forming the roughening face after conductor circuit forms, all the other and reference example 1 produce multilayer board in the same manner.
Comparative example 1
Except not making gap nozzle shakes the head, all the other and embodiment 16 produce multilayer board in the same manner.
As a result, the cross sectional shape of conductor circuit becomes rectangle.
Comparative example 2
Except not making gap nozzle shakes the head, all the other and embodiment 17 produce multilayer board in the same manner.
As a result, the cross sectional shape of conductor circuit becomes rectangle.
Comparative example 3
Except not making gap nozzle shakes the head, all the other and embodiment 18 produce multilayer board in the same manner.
As a result, the cross sectional shape of conductor circuit becomes rectangle.
Comparative example 4
Except not making gap nozzle shakes the head, all the other and embodiment 19 produce multilayer board in the same manner.
As a result, the cross sectional shape of conductor circuit becomes rectangle.
Comparative example 5
Except not making gap nozzle shakes the head, all the other and embodiment 20 produce multilayer board in the same manner.
As a result, the cross sectional shape of conductor circuit becomes rectangle.
Comparative example 6
Except etching period was changed to 50 seconds from 30 seconds, all the other and embodiment 16 produce multilayer board in the same manner.
In this comparative example, | the value of W1-W2| is 3.9 μ m～4.3 μ m, is equivalent to 0.78T～0.86T with the relation of conductor circuit thickness T.And, | the standard deviation of W1-W2| is 1.58 μ m.
Comparative example 7
Except etching period was changed to 50 seconds from 30 seconds, all the other and embodiment 17 produce multilayer board in the same manner.
In this comparative example, | the value of W1-W2| is 6.075 μ m～6.6 μ m, is equivalent to 0.81T～0.88T with the relation of conductor circuit thickness T.And, | the standard deviation of W1-W2| is 1.78 μ m.
Comparative example 8
Except etching period was changed to 50 seconds from 30 seconds, all the other and embodiment 18 produce multilayer board in the same manner.
In this comparative example, | the value of W1-W2| is 7.7 μ m～8.6 μ m, is equivalent to 0.77T～0.86T with the relation of conductor circuit thickness T.And, | the standard deviation of W1-W2| is 1.62 μ m.
Comparative example 9
Except etching period was changed to 50 seconds from 30 seconds, all the other and embodiment 19 produce multilayer board in the same manner.
In this comparative example, | the value of W1-W2| is 9.625 μ m～10.875 μ m, is equivalent to 0.77T～0.87T with the relation of conductor circuit thickness T.And, | the standard deviation of W1-W2| is 1.73 μ m.
Comparative example 10
Except etching period was changed to 50 seconds from 30 seconds, all the other and embodiment 20 produce multilayer board in the same manner.
In this comparative example, | the value of W1-W2| is 12 μ m～12.75 μ m, is equivalent to 0.8T～0.85T with the relation of conductor circuit thickness T.And, | W1-W2
| standard deviation be 1.88 μ m.
Comparative example 11
Except making etching period is 5 seconds, and all the other and embodiment 16 produce multilayer board in the same manner.
Comparative example 12
Except making etching period is 5 seconds, and all the other and embodiment 17 produce multilayer board in the same manner.
Comparative example 13
Except making etching period is 5 seconds, and all the other and embodiment 18 produce multilayer board in the same manner.
Comparative example 14
Except making etching period is 5 seconds, and all the other and embodiment 19 produce multilayer board in the same manner.
Comparative example 15
Except making etching period is 5 seconds, and all the other and embodiment 20 produce multilayer board in the same manner.
Reference example 3
Except forming on the surface of conductor circuit the roughening face, all the other and comparative example 11 produce multilayer board in the same manner.
Reference example 4
In embodiment 1, the pattern that changes resistance coating forms use mask, and to change the electrolytic copper plating condition and grind the thickness of conductor circuit afterwards and make the L/S of holding wire be that 20.0 μ m/20.0 μ m, conductor circuit thickness T are 20.0 μ m.In addition, gap nozzle is shaken the head.As a result, the cross sectional shape of conductor circuit becomes rectangle.
Reference example 5
In embodiment 16, the pattern that changes resistance coating forms use mask, and to change the electrolytic copper plating condition and grind the thickness of conductor circuit afterwards and make the L/S of holding wire be that 20.0 μ m/20.0 μ m, conductor circuit thickness T are 20.0 μ m.In addition, gap nozzle is shaken the head.As a result, the cross sectional shape of conductor circuit becomes rectangle.
Reference example 6
In embodiment 1, the pattern that changes resistance coating forms use mask, and to change the electrolytic copper plating condition and grind the thickness of conductor circuit afterwards and make the L/S of holding wire be that 20.0 μ m/20.0 μ m, conductor circuit thickness T are 20.0 μ m.Etching period was changed to 50 seconds from 30 seconds.As a result, | the value of W1-W2| is 15.4 μ m～17.2 μ m, is equivalent to 0.77T～0.86T with the relation of conductor circuit thickness T.And, | the standard deviation of W1-W2| is 1.58 μ m.
Reference example 7
In embodiment 16, the pattern that changes resistance coating forms use mask, and to change the electrolytic copper plating condition and grind the thickness of conductor circuit afterwards and make the L/S of holding wire be that 20.0 μ m/20.0 μ m, conductor circuit thickness T are 20.0 μ m.And, etching period was changed to 50 seconds from 30 seconds.As a result, | the value of W1-W2| is 15.6 μ m～17.0 μ m, is equivalent to 0.78T～0.85T with the relation of conductor circuit thickness T.And, | the standard deviation of W1-W2| is 1.77 μ m.
Reference example 8
In embodiment 11, except gap nozzle is not used in the 2nd etching, but with etching solution that the 1st time etching is identical in dipping carried out outside the etching in 1 minute, all the other and embodiment 11 produce multilayer board in the same manner.
In this reference example, | the value of W1-W2| is 0.5 μ m～3.65 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.
But in this reference example, owing to adopted the immobilising infiltration etching of etching solution simultaneously, so etching speed has than big-difference with the position is different, the result, and loop shape of each wiring differs bigger, therefore | the standard deviation of W1-W2| is 2.43 μ m.
Reference example 9
Except not forming the roughening face on this conductor circuit surface after conductor circuit forms, all the other and reference example 8 produce multilayer board in the same manner.
Reference example 10
In embodiment 12, except gap nozzle is not used in the 2nd etching, but with etching solution that the 1st time etching is identical in dipping carried out outside the etching in 1 minute, all the other and embodiment 12 produce multilayer board in the same manner.
In this reference example, | the value of W1-W2| is 0.75 μ m～5.475 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.
But in this reference example, owing to adopted the immobilising dipping etching of etching solution simultaneously, so etching speed has than big-difference with the position is different, the result, and loop shape of each wiring differs bigger, therefore | the standard deviation of W1-W2| is 2.34 μ m.
Reference example 11
Except not forming the roughening face on this conductor circuit surface after conductor circuit forms, all the other and reference example 10 produce multilayer board in the same manner.
Reference example 12
In embodiment 13, except gap nozzle is not used in the 2nd etching, but with etching solution that the 1st time etching is identical in dipping carried out outside the etching in 1 minute, all the other and embodiment 13 produce multilayer board in the same manner.
In this reference example, | the value of W1-W2| is 1.0 μ m～7.3 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.
But in this reference example, owing to adopted the immobilising dipping etching of etching solution simultaneously, so etching speed has than big-difference with the difference at position, the result, and loop shape of each wiring differs bigger, therefore | the standard deviation of W1-W2| is 2.45 μ m.
Reference example 13
Except not forming the roughening face on the conductor circuit surface after conductor circuit forms, all the other and reference example 12 produce multilayer board in the same manner.
Reference example 14
In embodiment 15, except gap nozzle is not used in the 2nd etching, but with etching solution that the 1st time etching is identical in dipping carried out outside the etching in 1 minute, all the other and embodiment 15 produce multilayer board in the same manner.
In this reference example, | the value of W1-W2| is 1.50 μ m～10.95 μ m, satisfies the relation of (0.10 * conductor circuit thickness T)～(0.73 * conductor circuit thickness T) substantially.
But in this reference example, owing to adopted the immobilising dipping etching of etching solution simultaneously, so etching speed has than big-difference with the difference at position, the result, and loop shape of each wiring differs bigger, therefore | the standard deviation of W1-W2| is 2.62 μ m.
Reference example 15
Except not forming the roughening face on the conductor circuit surface after conductor circuit forms, all the other and reference example 14 produce multilayer board in the same manner.
The multilayer board that embodiment 1～30, reference example 1～15, comparative example 1～15 according to above explanation are produced carries out following evaluation test.
Between the minimum conductor circuit width L (μ m) of the conductor circuit on each multilayer board that produces in addition,, the minimum conductor circuit apart from S (μ m), conductor circuit thickness T (μ m), | the minimum value (min) of W1-W2| (μ m), maximum (max), | the relation of the minimum value of W1-W2| (min) and thickness T, | the relation of the maximum of W1-W2| (max) and thickness T, | having or not of the standard deviation of W1-W2| (μ m) and roughening face is shown in table 1-1 and table 1-2.
In addition, table 1-1 and table omitted among the 1-2 L, S, T, | the unit of W1-W2| and σ.
Table 1-1
| Conductor minimum widith L/ minimum interval S | Conductor thickness T | min |W1-W2| | Max |W1-W2| | The relation of min|W1-W2| and T | The relation of Max|W1-W2| and T | σ | (* notes) | Have or not the roughening face | |
| Embodiment 1 | 5.0/5.0 | 5.0 | 0.5 | 1.75 | 0.1T | 0.35T | 1.23 | ○ | Have |
| Embodiment 2 | 7.5/7.5 | 7.5 | 0.675 | 2.775 | 0.09T | 0.37T | 1.33 | ○ | Have |
| Embodiment 3 | 10.0/10.0 | 10.0 | 0.9 | 3.6 | 0.09T | 0.36T | 1.27 | ○ | Have |
| Embodiment 4 | 12.5/12.5 | 12.5 | 1.25 | 4.375 | 0.1T | 0.35T | 1.34 | ○ | Have |
| Embodiment 5 | 15.0/15.0 | 15.0 | 1.35 | 5.25 | 0.09T | 0.35T | 1.35 | ○ | Have |
| Embodiment 6 | 5.0/5.0 | 5.0 | 1.7 | 3.7 | 0.34T | 0.74T | 1.77 | ○ | Have |
| Embodiment 7 | 7.5/7.5 | 7.5 | 2.475 | 5.475 | 0.33T | 0.73T | 1.76 | ○ | Have |
| Embodiment 8 | 10.0/10.0 | 10.0 | 3.5 | 7.3 | 0.35T | 0.73T | 1.78 | ○ | Have |
| Embodiment 9 | 12.5/12.5 | 12.5 | 4.25 | 9.25 | 0.34T | 0.74T | 1.65 | ○ | Have |
| Embodiment 10 | 15.0/15.0 | 15.0 | 5.25 | 10.95 | 0.35T | 0.73T | 1.72 | ○ | Have |
| Embodiment 11 | 5.0/5.0 | 5.0 | 0.5 | 3.65 | 0.1T | 0.73T | 2.01 | ○ | Have |
| Embodiment 12 | 7.5/7.5 | 7.5 | 0.675 | 5.625 | 0.09T | 0.75T | 2.13 | ○ | Have |
| Embodiment 13 | 10.0/10.0 | 10.0 | 0.9 | 7.6 | 0.09T | 0.76T | 2.20 | ○ | Have |
| Embodiment 14 | 12.5/12.5 | 12.5 | 1.25 | 9.25 | 0.1T | 0.74T | 2.45 | ○ | Have |
| Embodiment 15 | 15.0/15.0 | 15.0 | 1.5 | 10.95 | 0.1T | 0.73T | 2.58 | ○ | Have |
| Embodiment 16 | 5.0/5.0 | 5.0 | 0.5 | 1.8 | 0.1T | 0.36T | 1.23 | ○ | Do not have |
| Embodiment 17 | 7.5/7.5 | 7.5 | 0.75 | 2.625 | 0.1T | 0.35T | 1.38 | ○ | Do not have |
| Embodiment 18 | 10.0/10.0 | 10.0 | 1.0 | 3.6 | 0.1T | 0.36T | 1.22 | ○ | Do not have |
| Embodiment 19 | 12.5/12.5 | 12.5 | 1.125 | 4.625 | 0.09T | 0.37T | 1.34 | ○ | Do not have |
| Embodiment 20 | 15.0/15.0 | 15.0 | 1.35 | 5.25 | 0.09T | 0.35T | 1.34 | ○ | Do not have |
| Embodiment 21 | 5.0/5.0 | 5.0 | 1.65 | 3.75 | 0.33T | 0.75T | 1.65 | ○ | Do not have |
| Embodiment 22 | 7.5/7.5 | 7.5 | 2.625 | 5.475 | 0.35T | 0.73T | 1.71 | ○ | Do not have |
| Embodiment 23 | 10.0/10.0 | 10.0 | 3.5 | 7.3 | 0.35T | 0.73T | 1.58 | ○ | Do not have |
| Embodiment 24 | 12.5/12.5 | 12.5 | 4.125 | 9.375 | 0.33T | 0.75T | 1.66 | ○ | Do not have |
| Embodiment 25 | 15.0/15.0 | 15.0 | 4.95 | 10.95 | 0.33T | 0.73T | 1.71 | ○ | Do not have |
| Embodiment 26 | 5.0/5.0 | 5.0 | 0.45 | 3.65 | 0.09T | 0.73T | 2.11 | ○ | Do not have |
| Embodiment 27 | 7.5/7.5 | 7.5 | 0.75 | 5.475 | 0.1T | 0.73T | 2.11 | ○ | Do not have |
| Embodiment 28 | 10.0/10.0 | 10.0 | 1.0 | 7.5 | 0.1T | 0.75T | 2.33 | ○ | Do not have |
| Embodiment 29 | 12.5/12.5 | 12.5 | 1.125 | 9.25 | 0.09T | 0.74T | 2.45 | ○ | Do not have |
| Embodiment 30 | 15.0/15.0 | 15.0 | 1.5 | 10.95 | 0.1T | 0.73T | 2.55 | ○ | Do not have |
| Reference example 1 | 12.5/12.5 | 12.5 | 1.25 | 9.25 | 0.1T | 0.74T | 2.58 | × | Have |
| Reference example 2 | 12.5/12.5 | 12.5 | 1.125 | 9.125 | 0.09T | 0.73T | 2.53 | × | Do not have |
| Reference example 3 | 5.0/5.0 | 5.0 | 0.15 | 0.35 | 0.03T | 0.07T | 0.89 | ○ | Have |
| Reference example 4 | 20.0/20.0 | 20.0 | - | - | - | - | - | - | Have |
| Reference example 5 | 20.0/20.0 | 20.0 | - | - | - | - | - | - | Do not have |
| Reference example 6 | 20.0/20.0 | 20.0 | 15.4 | 17.2 | 0.77T | 0.86T | 1.58 | ○ | Have |
| Reference example 7 | 20.0/20.0 | 20.0 | 15.6 | 17.0 | 0.78T | 0.85T | 1.77 | ○ | Do not have |
| Reference example 8 | 5.0/5.0 | 5.0 | 0.5 | 3.65 | 0.1T | 0.73T | 2.43 | × | Have |
| Reference example 9 | 5.0/5.0 | 5.0 | 0.5 | 3.75 | 0.1T | 0.75T | 2.23 | × | Do not have |
| Reference example 10 | 7.5/7.5 | 7.5 | 0.75 | 5.475 | 0.1T | 0.74T | 2.34 | × | Have |
| Reference example 11 | 7.5/7.5 | 7.5 | 0.675 | 5.475 | 0.09T | 0.74T | 2.35 | × | Do not have |
| Reference example 12 | 10.0/10.0 | 10.0 | 1.0 | 7.3 | 0.1T | 0.73T | 2.45 | × | Have |
| Reference example 13 | 10.0/10.0 | 10.0 | 1.0 | 7.5 | 0.1T | 0.75T | 2.50 | × | Do not have |
| Reference example 14 | 15.0/15.0 | 15.0 | 1.5 | 10.95 | 01T | 0.73T | 2.62 | × | Have |
| Reference example 15 | 15.0/15.0 | 15.0 | 1.35 | 10.95 | 0.09T | 0.73T | 2.73 | × | Do not have |
Table 1-2
| Conductor minimum widith L/ minimum interval S | Conductor thickness T | min |W1-W2| | Max |W1-W2| | The relation of min|W1-W2| and T | The relation of Max|W1-W2| and T | σ | (* notes) | Have or not the roughening face | |
| Comparative example 1 | 5.0/5.0 | 5.0 | - | - | - | - | - | - | Do not have |
| Comparative example 2 | 7.5/7.5 | 7.5 | - | - | - | - | - | - | Do not have |
| Comparative example 3 | 10.0/10.0 | 10.0 | - | - | - | - | - | - | Do not have |
| Comparative example 4 | 12.5/12.5 | 12.5 | - | - | - | - | - | - | Do not have |
| Comparative example 5 | 15.0/15.0 | 15.0 | - | - | - | - | - | - | Do not have |
| Comparative example 6 | 5.0/5.0 | 5.0 | 3.9 | 4.3 | 0.78T | 0.86T | 1.58 | ○ | Do not have |
| Comparative example 7 | 7.5/7.5 | 7.5 | 6.075 | 6.6 | 0.81T | 0.88T | 1.78 | ○ | Do not have |
| Comparative example 8 | 10.0/10.0 | 10.0 | 7.7 | 8.6 | 0.77T | 0.86T | 1.62 | ○ | Do not have |
| Comparative example 9 | 12.5/12.5 | 12.5 | 9.625 | 10.875 | 0.77T | 0.87T | 1.73 | ○ | Do not have |
| Comparative example 10 | 15.0/15.0 | 15.0 | 12.0 | 12.75 | 0.8T | 0.85T | 1.88 | ○ | Do not have |
| Comparative example 11 | 5.0/5.0 | 5.0 | 0.15 | 0.35 | 0.03T | 0.07T | 0.88 | ○ | Do not have |
| Comparative example 12 | 7.5/7.5 | 7.5 | 0.375 | 0.6 | 0.05T | 0.08T | 0.89 | ○ | Do not have |
| Comparative example 13 | 10.0/10.0 | 10.0 | 0.3 | 0.8 | 0.03T | 0.08T | 1.02 | ○ | Do not have |
| Comparative example 14 | 12.5/12.5 | 12.5 | 0.5 | 0.875 | 0.04T | 0.07T | 0.78 | ○ | Do not have |
| Comparative example 15 | 15.0/15.0 | 15.0 | 0.45 | 1.2 | 0.03T | 0.08T | 0.88 | ○ | Do not have |
※ annotates: for the mark in () of standard deviation, if σ is designated as zero at (0.04T+2) with next, if σ surpass (0.04T+2) then be designated as *.
(evaluation test 1) noise validation test
By the method that the following describes the voltage waveform of the conductor circuit of the multilayer board that produces according to the foregoing description 1～30, reference example 3 and comparative example 1～5 and 11～15 is observed, thereby investigated out with 6 kinds of IC chips (No.1～whether exist when No.6) being installed on multilayer board noise.
At first, make 5 adjacent tests in same conductor circuit layer, form almost parallel, and the 1st, 3,5 wiring is connected with the IC chip, and the 2nd, 4 wiring is not connected and the wiring of conduct mensuration with the IC chip with wiring 1～5.In with following No.1～No.6 any IC chip be installed on each multilayer board as IC chip 90 and the state of drive IC under, use oscilloscope (テ Network ト ロ ニ Network ス (Tektronix) society system, goods title " 11801C ") that 2,4 the voltage waveform of connecting up is observed, investigate out the noise that whether exists from the 1st, 3,5 wiring.
No.1: driving frequency 3.2GHz, bus clock (FSB) 1066MHz
No.2: driving frequency 3.0GHz, bus clock (FSB) 800MHz
No.3: driving frequency 2.8GHz, bus clock (FSB) 533MHz
No.4: driving frequency 2.6GHz, bus clock (FSB) 400MHz
No.5: driving frequency 1.4GHz, bus clock (FSB) 133MHz
No.6: driving frequency 1.1GHz, bus clock (FSB) 100MHz
Its result of the test is shown in table 2.In addition, in the 2nd, 4 wiring, observe being designated as of voltage waveform *, that does not observe voltage waveform is designated as zero.
Table 2
By the experimental result that No.3 and No.4IC chip have been installed as can be known, at the conductor circuit of the L/S=5 μ m/5 μ m that is easy to generate most noise, do not produce noise among the embodiment 1,6,11,16,21,26 in | W1-W2| is in the scope of 0.10T～0.73T.
With respect to this, in comparative example 1, observed noise.Infer that its reason is because the capacitance between the adjacent conductor circuit is bigger, has therefore observed the cross-talk noise on adjacent conductor circuit.
In addition, when the experimental result of the multilayer board of producing according to reference example 3 and comparative example 11 that the No.5IC chip will be installed compares, observed noise on the lower IC of the driving frequency in reference example 3.But,, in the comparative example 11 that the roughening layer is not set, do not observe noise though be all L/S=5 μ m/5 μ m with this reference example 3.
Hence one can see that, the conductor circuit surface by the asperities change printed circuit board (PCB) in be easy to generate noise, but by adopting the present invention, that is, will | W1-W2| is set in the scope of 0.10T～0.73T can suppress noise.Why the conductor circuit surface by the asperities change printed circuit board (PCB) (reference example 3) in be easy to generate noise, can infer that its reason is for owing to the conductor circuit surface is made capacitance between the conductor circuit greater than capacitance between the conductor circuit of comparative example 11 by asperitiesization.
(evaluation test 2) misoperation validation test
In the process of carrying the IC chip, whether exist misoperation to confirm the multilayer board that produces according to the foregoing description 1～30, reference example 1～2,8～15 and comparative example 1～15 by the method that the following describes.
Any the IC chip that to choose from following No.1～No.6 is installed on each multilayer board as IC chip 90, and outside terminal 78 input test signals that are electrically connected to signal with IC chip 90, the result of IC chip institute computing is from IC chip output, for example uses impulse waveform generator/error detector (ア De バ Application テ ス ト (ADVANTEST) society system, trade name " D3186/3286 ") whether the data that arrive outside terminal are once more confirmed by correct output.
No.1: driving frequency 3.2GHz, bus clock (FSB) 1066MHz
No.2: driving frequency 3.0GHz, bus clock (FSB) 800MHz
No.3: driving frequency 2.8GHz, bus clock (FSB) 533MHz
No.4: driving frequency 2.6GHz, bus clock (FSB) 400MHz
No.5: driving frequency 1.4GHz, bus clock (FSB) 133MHz
No.6: driving frequency 1.1GHz, bus clock (FSB) 100MHz
It the results are shown in table 3-1 and 3-2.In addition, when dateout is wrong, be designated as *, when dateout is correct, be designated as zero.
Table 3-1
Table 3-2
Will carry driving frequency be each multilayer board of the IC chip No.4 of 2.6GHz when comparing as can be known, in adjacent conductor circuit relation at interval | there was not misoperation in (embodiment 1～30) when W1-W2| was in the scope of 0.10T～0.73T, and in addition (comparative example 1～15) can the generation misoperation.
It is owing to there be conductor volume poor of capacitance between the conductor circuit and conductor circuit that its difference can be speculated as, if printed circuit board (PCB) of the present invention does not then exist noise and signal delay ground that signal is not passed to the IC chip.
In addition, for according to | the value of W1-W2| is roughly the embodiment 14 of same degree and the multilayer board that reference example 1 produces, will carry driving frequency be each multilayer board of the IC chip No.3 of 2.8GHz when comparing as can be known, | there is not misoperation in the standard deviation of W1-W2| among the embodiment 14 below (0.04T+2), obtain good result, but in reference example 1, produced misoperation.Carry out high-speed driving, then the transistorized moment of the arrival between each signal can become problem more, but can infer in standard deviation and be (0.04T+2) when following, and the difference of the transfer rate on each connects up diminishes and is difficult to produce misoperation.Same situation also meets embodiment 29 and reference example 2.
In addition, having carried driving frequency is that each multilayer board of the IC chip No.2 of 3.0GHz is when comparing, by the comparison of embodiment 1～10 and embodiment 11～15, embodiment 16～25 and embodiment 26～30 more as can be known, when | W1-W2| is in the scope of 0.35T～0.73T, can obtain better result.
Its reason can be speculated as because by making | and the scope of W1-W2| diminishes, and then the difference of the transfer rate between each signal becomes littler, and the capacitance between the conductor circuit diminishes, and therefore is difficult to produce misoperation more.And as can be known, | W1-W2| is in the scope of 0.10T～0.35T and is advisable.It is owing under the state that the resistance with conductor keeps lowlyer that its reason can be speculated as, the cause that the difference of the transfer rate between each signal and the capacitance between the conductor circuit diminish.
(evaluation test 3) noise validation test
No.3IC chip in the evaluation test 1 is installed on the multilayer board that produces according to above-mentioned reference example 4,5, and it has been carried out the test identical with evaluation test 1.Its result is zero (not observing voltage waveform).
When reference example 4,5 and comparative example are compared, even same cross sectional shape is not observed noise yet on the conductor circuit of L/S=20 μ m/20 μ m.It is because the bigger cause of L/S that its reason can be speculated as.By this result as can be known, to adopt the meaning of the multilayer board with the following conductor circuit of L/S=15 μ m/15 μ m be great in the present invention.
(evaluation test 4) misoperation validation test
No.3IC chip in the evaluation test 2 is installed on the multilayer board that produces according to above-mentioned reference example 4,5,6,7, it has been carried out the test identical with evaluation test 2.Its result is zero (not having misoperation).When reference example 4～7 and comparative example are compared, even same cross sectional shape is not observed misoperation yet on the conductor circuit of L/S=20 μ m/20 μ m.It is because the bigger cause of L/S that its reason can be speculated as.By this result as can be known, to adopt the meaning of the multilayer board with the following conductor circuit of L/S=15 μ m/15 μ m be great in the present invention.
Embodiment 31
Make etched facing down, and only use the following side nozzle that is configured in the Etaching device nozzle up and down to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 1.
Make etched facing down, and only use the following side nozzle that is configured in the Etaching device nozzle up and down to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 2.
Embodiment 33
Make etched facing down, and only use the following side nozzle that is configured in the Etaching device nozzle up and down to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 3.
Make etched facing down, and only use the following side nozzle that is configured in the Etaching device nozzle up and down to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 4.
Embodiment 35
Make etched facing down, and only use the following side nozzle that is configured in the Etaching device nozzle up and down to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 5.
Make etched facing down, and only use the following side nozzle that is configured in the Etaching device nozzle up and down to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 16.
Embodiment 37
Make etched facing down, and only use the following side nozzle in the nozzle up and down that is configured in Etaching device to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 17.
Make etched facing down, and only use the following side nozzle in the nozzle up and down that is configured in Etaching device to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 18.
Embodiment 39
Make etched facing down, and only use the following side nozzle in the nozzle up and down that is configured in Etaching device to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 19.
Make etched facing down, and only use the following side nozzle in the nozzle up and down that is configured in Etaching device to carry out 15 seconds etching, in addition produce multilayer board in the same manner with embodiment 20.
Measuring the foregoing description 31～40 | during the value of W1-W2|, the relation of itself and conductor circuit thickness T all satisfies the scope of 0.10T～0.35T.In addition, identical with above-mentioned evaluation test 1 and evaluation test 2, having investigated is being whether 3.46GHz, bus clock (FSB) exist noise when being installed on the multilayer board that produces according to embodiment 31～40 for the IC chip of 1066MHz with driving frequency, and has confirmed whether there is misoperation on the IC chip that carries.Its result is zero.
Utilizability on the industry
As described above, printed circuit board (PCB) of the present invention, the cross sectional shape of conductor circuit is formed: be made as W1 at the interval with the upper surface side of adjacent conductor circuit, when the interval of lower face side is made as W2, the relation of these intervals and conductor circuit thickness T satisfy 0.10T≤| W1-W2|≤0.73T. Form the printed circuit board (PCB) of the conductor circuit with such cross sectional shape, even carried by the IC of high-speed driving, also can suppress cross-talk and signal delay, prevented the misoperation of IC.
Claims (7)
1. printed circuit board (PCB), be that fill insulant forms between conductor circuit, it is characterized in that, the cross sectional shape of above-mentioned conductor circuit is essentially trapezoidal, the conductor circuit upper surface side in the interval between the adjacent conductor circuit is made as W1 at interval, when the conductor circuit lower face side is made as W2 at interval, these satisfy at interval the requirement of following formula with the relation of the thickness T of conductor circuit:
0.10T≤|W1-W2|≤0.73T……(1)。
2. printed circuit board (PCB) according to claim 1 is characterized in that, and is above-mentioned | W1-W2| is below the 0.35T.
3. printed circuit board (PCB) according to claim 1 is characterized in that, above-mentioned conductor circuit lower face side W2 at interval is below the 15 μ m.
4. printed circuit board (PCB) according to claim 2 is characterized in that, above-mentioned conductor circuit lower face side W2 at interval is below the 15 μ m.
5. according to each described printed circuit board (PCB) in the claim 1～4, it is characterized in that, above-mentioned | the standard deviation of W1-W2| is below (0.04T+2).
6. according to each described printed circuit board (PCB) in the claim 1～4, it is characterized in that the surface of above-mentioned conductor circuit is roughened.
7. printed circuit board (PCB) according to claim 5 is characterized in that the surface of above-mentioned conductor circuit is roughened.
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| US6340798B1 (en) * | 1999-11-30 | 2002-01-22 | Fujitsu Limited | Printed circuit board with reduced crosstalk noise and method of forming wiring lines on a board to form such a printed circuit board |
| CN1434672A (en) * | 2002-01-25 | 2003-08-06 | 联能科技（深圳）有限公司 | Multi-layer heap circuit board and making method thereof |
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| US6340798B1 (en) * | 1999-11-30 | 2002-01-22 | Fujitsu Limited | Printed circuit board with reduced crosstalk noise and method of forming wiring lines on a board to form such a printed circuit board |
| CN1434672A (en) * | 2002-01-25 | 2003-08-06 | 联能科技（深圳）有限公司 | Multi-layer heap circuit board and making method thereof |
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