CN100555212C - The carry calibration equipment of a kind of floating dual MAC and multiplication CSA compressed tree thereof - Google Patents
The carry calibration equipment of a kind of floating dual MAC and multiplication CSA compressed tree thereof Download PDFInfo
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Abstract
The invention discloses the carry calibration equipment of multiplication carry save adder (CSA) compressed tree in a kind of floating dual MAC, comprise a carry judging unit and a carry verification unit, described carry judging unit, being used for two operand A of floating dual MAC and the B compression carry portion that compression obtains through first carry save adder and compression and partial data is input value, whether the result who judges addition carry, and according to carry situation output carry check bit M; Described carry verification unit is used for the carry check bit M according to the output of carry judging unit, the C after the operand C negate alignment
InvshiftHigh 55 bits (bit), the higher bit of the carry compression result of the 2nd 3:2 compression carry save adder carries out carry to correct, the value of exporting two group of 55 bit is in high 55 of two groups of data of 161 bit adder.It makes that carry save adder (CSA) compression result obtains correcting, and makes that the calculating of adder and multiplier is correct.
Description
Technical field
The present invention relates to the microprocessor technology field, particularly relate to the floating point multiplication addition Component Design technology in a kind of microprocessor, especially relate to the carry calibration equipment of a kind of floating dual MAC and multiplication carry save adder (CSA) compressed tree thereof.
Background technology
In order to reach the high-level efficiency of Floating-point Computation, floating-point multiplication and addition all use a Float Point Unit-floating dual MAC (Floating-point Multiply-Add Fused Unit FMAF) realize in microprocessor.The instruction of floating dual MAC (FMAF) is carried out needs 3 operand A, B, C, carry out (A * B)+C operation when to add what carry out when operand C is changed to 0 in the instruction be multiplying order taking advantage of, is changed to operand B at 1 o'clock, execution be add instruction.
Operand at floating dual MAC mentioned in this article is the 64 bit double-precision floating pointses that meet the standard of IEEE754.The IEEE754 standard has been done regulation as following table 1 to 64 bit double precisions.Hidden the integer-bit 1 of mantissa in the table 1, added often be 1 integer-bit, double precision mantissa is 53.
Double precision formats table in the table 1IEEE754 standard
| S (1 of symbol) | E (11 of indexes) | F (52 of decimal mantissa) |
What the multiplication A of double precision * B calculated is the multiplication of the mantissa of 2 53 bits, and that obtain is the result of 53+53=106 bit if the result does not round off.
In the microprocessor of existing techniques in realizing, the floating point multiplication addition computing generally realizes that by following steps (related content please refer to document 1:Floating-Point Multiply-Add-Fused with Reduced latency, IEEE transactions on computers, VOL.53, No.8, August 2004 and list of references 2:Architectural design of a fast floating-point multiplication-add fused unit usingsigned-digit addition, IEE proceedings online no.20020409):
When computing, the symbol of operand A * B and C may be identical, also may be opposite.If the opposite in sign of A * B and C is done effective subtraction with A * B and C, the complement code that need obtain C is carried out addition, and C needs negate.The symbol of A * B and C is identical else if does effective addition, and C does not need negate.
The mantissa of double precision operand C is 53 bits, adds 2 extra rounding off (rounding) bit, and the inversion operation that obtains after the negate is counted C
InvMost significant digit than the result of A * B moves to left 55 at most, and perhaps than A * B result's most significant digit 106 bits that move to right at most, promptly shift range is between (55,106).In the design of floating point multiplication addition, to oversimplify in order to make displacement, the normalization inversion operation is counted C
InvDirection of displacement be right shift, the scope of displacement is (0,161) bit.So C
InvShift result C
InvshiftIt is one 161 bit number.
But in above-mentioned steps, 2 results of A * B promptly compress carry portion (mulcarry) and compression and part (mulsum), count C with the inversion operation of alignment shift
InvshiftThe carry save adder (CSA) that utilizes 3: 2 is when compressing, if do not handle, 2 results of A * B, compression carry portion (mulcarry) and compression and part (mulsum) are under certain specific data cases, for example the most significant digit of mulcarry and mulsum all is 1 o'clock, both addition meetings produce a carry to most significant digit 107 bits, and this carry has been brought in 3: 2 CSA compressed tree in 106 bit result after the compression.And this is fictitious carries to 107 bit carries, and in fact floating-point double precision operand A * B is the number of 53 bits * 53 bits, only can obtain the result of a 53+53=106 bit, and 107 bits can not have value, so this carry is wrong.This mistake is caused by the coding of the ripple thatch (booth) among the multiplier compression tree CSA.Because multiplication is only got wherein 106 bits, so this mistake is conductively-closed in multiplier, and if in adder and multiplier, do not do any processing, can since the carry of mistake cause some data computing mistake.
Summary of the invention
The objective of the invention is provides the carry calibration equipment of a kind of floating dual MAC and multiplication carry save adder (CSA) compressed tree thereof at multiplication carry save adder (CSA) compression carry mistake.It makes that carry save adder (CSA) compression result obtains correcting, and makes that the calculating of adder and multiplier is correct.
For realizing the carry calibration equipment of multiplication CSA compressed tree in a kind of floating dual MAC that the object of the invention provides, comprise a carry judging unit and a carry verification unit, wherein:
Described carry judging unit, being used for two operand A of floating dual MAC and the B compression carry portion that compression obtains through the first multiplication carry save adder and compression and partial data is input value, whether the result who judges addition carry, and according to carry situation output carry check bit M;
Described carry verification unit is used for the carry check bit M according to the output of carry judging unit, the C after the operand C negate alignment
InvshiftHigh 55 bits, the higher bit of the carry compression result of the 23: 2 carry save adders is carried out carry and is corrected, the value of exporting two group of 55 bit is in high 55 of two groups of data of 161 bit adder.
Described carry judging unit comprises a plurality of circuit units of being made up of a judgement carry circuit unit and a connecting circuit unit.
Described judgement carry circuit unit is 4 bit decision carry circuits; Described connecting circuit unit is the connecting circuit of 4 bits.
Utilize the judgement carry circuit unit and the described 4 bit connecting circuit unit of described 4 bits to build 16 bit carry decision circuitry unit, the carry decision circuitry unit of the carry decision circuitry unit of 32 bits and 112 bits.
Described carry judging unit is the carry decision circuitry unit that utilizes described 112 bits, and low 6 bits fill 0, and the carry judgement of carrying out 106 bits obtains.
Described carry judging unit and the 23: 2 carry save adder concurrent operations are carried out carry and are corrected.
Described carry verification unit comprises a selector switch of 4: 1, is judged the check bit M and the 23 of output by carry: the higher bit of the carry compression result of 2 carry save adders is selected defeated one 55 bit value.
Another 55 bit value of described carry verification unit is C
InvshiftHigh 55 bits.
For realizing that the object of the invention also provides a kind of floating dual MAC, comprise the negate device, the bit aligned shift unit, the first multiplication carry save adder, the 23: 2 carry save adders, the totalizer of 161 bits, and the normalization and the unit that rounds off, it is characterized in that, also comprise the carry calibration equipment of the multiplication CSA compressed tree that walks abreast with second carry save adder;
Described device comprises a carry judging unit and a carry verification unit, wherein:
Described carry judging unit, being used for two operand A of floating dual MAC and the B compression carry portion that compression obtains through the first multiplication carry save adder and compression and partial data is input value, whether the result who judges addition carry, and according to carry situation output carry check bit M;
Described carry verification unit is used for the carry check bit M according to the output of carry judging unit, the C after the operand C negate alignment
InvshiftHigh 55 bits, the higher bit of the carry compression result of the 23: 2 carry save adders is carried out carry and is corrected, the value of exporting two group of 55 bit is in high 55 of two groups of data of 161 bit adder.
Described carry judging unit comprises a plurality of circuit units of being made up of a judgement carry circuit unit and a connecting circuit unit.
Described judgement carry circuit unit is 4 bit decision carry circuits; Described connecting circuit unit is the connecting circuit of 4 bits.
Described carry judging unit is the carry judging unit that utilizes described 112 bits, and low 6 bits fill 0, and the carry judgement of carrying out 106 bits obtains.
Described carry verification unit is to comprise a selector switch of 4: 1, is judged the check bit M and the 23 of output by carry: the higher bit of the carry compression result of 2 carry save adders selects to export one 55 bit value.
Another 55 bit value of described carry verification unit output is C
InvshiftHigh 55 bits.
The invention has the beneficial effects as follows: the carry calibration equipment of floating dual MAC of the present invention and multiplication carry save adder (CSA) compressed tree thereof, parallel by carry judging unit and the 23: 2 carry save adders, make it under the situation of few delay is tried one's best in increase, obtain the correct result of adder and multiplier.
Description of drawings
Fig. 1 is the carry calibration equipment structural representation of floating dual MAC of the present invention and multiplication carry save adder (CSA) thereof;
Fig. 2 A is the embodiment of the invention 4 bit decision carry circuit synoptic diagram;
Fig. 2 B is 4 bit decision carry circuit figure;
Fig. 3 A is the judgement connecting circuit synoptic diagram of 4 bits;
Fig. 3 B is the judgement connecting circuit figure of 4 bits;
Fig. 4 A is 16 bit carry judging unit synoptic diagram;
Fig. 4 B is 32 bit carry judging unit synoptic diagram;
Fig. 4 C is 112 bit carry judging unit synoptic diagram;
Fig. 5 is the circuit diagram of carry verification unit.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the carry calibration equipment of a kind of floating dual MAC of the present invention and multiplication carry save adder (CSA) compressed tree thereof is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In order to reach purpose of the present invention, as shown in Figure 1, floating dual MAC of the present invention comprises negate device 6, bit aligned shift unit 7, the first multiplication carry save adder (CSA) 1, the 23: 2 carry save adders (CSA) 2,161 bit adder 5, standardize and round off unit 8 and with the carry calibration equipment of parallel multiplication carry save adder (CSA) compressed tree of the 23: 2 carry save adders (CSA) 2.
The carry calibration equipment of described multiplication carry save adder (CSA) compressed tree comprises a carry judging unit 3 and a carry verification unit 4.
Described carry judging unit 3, with two operand A of floating dual MAC and B two groups of compression carry portions (mulcarry) that 1 compression obtains through the first multiplication carry save adder (CSA) and compression and partly (mulsum) as input value, whether the result who judges its addition carry, and according to carry situation output carry check bit M.
Described carry judging unit 3 is input as the multiply each other number of 2 group of 106 bit of compression of two operand A of floating dual MAC and B: compression carry portion (mulcarry) and compression and partly (mulsum) are output as the carry check bit M of 1 bit.
When two operand A of floating dual MAC and B in two groups of compression carry portions (mulcarry) that 1 compression through the first multiplication carry save adder (CSA) obtains and compression with partly after (mulsum), be input to the carry judging unit, when if these two groups of data are added with carry mutually, the output carry check bit M=1 of carry decision circuitry, otherwise M=0.
As a kind of enforceable mode, the carry judging unit comprises that a plurality of 4 bit decision carry circuit unit 21 and a plurality of 4 bit connecting circuit unit 31 form the carry judging unit 3 of judging A * B compression result 106 bits.
Shown in Fig. 2 A, be 4 bit decision carry circuit synoptic diagram, described judgement carry circuit unit 21 is that 4 bits (bit) are judged carry circuit, shown in Fig. 2 B, be 4 bit decision carry circuit figure, wherein, a and b are input 24 bits (bit) signals, g be position and, the k of 2 signals be 2 signals the position or.Output signal M is the carry check bit of 4 bit a and b, and H is that the carry of 4 bit carry decision circuitry unit 21 is transmitted signal, is used to form the carry judging unit 3 of many bits.
Among Fig. 2 B, if the higher bit a[3 of a and b] and b[3] all be 1, g[3 so] be 1, then a+b has a carry 1 certainly, a=1010 for example, b=1001.And as time low level g[2]=1 the time, time low level be described to the peculiar carry of height ratio, at this moment needing only peculiar one of the height ratio of a and b is 1, just h[3]=k[3] be 1 o'clock, can export a carry, the rest may be inferred, can draw the circuit at Fig. 2 B.The H signal that also just is understood that Fig. 2 B circuit output is the carry propagation signal, as long as low than peculiar carry, and the H signal be 1 so output carry is arranged certainly.
As shown in Figure 3A, be the connecting circuit synoptic diagram of 4 bits, described 4 bit connecting circuit unit 31 are connecting circuit that are input as 4 bits, shown in Fig. 3 B, are the connecting circuit figure of 4 bits.Wherein, utilize 24 bits (bit) to judge output signal M1, the H1 of carry circuit unit 21, M2 and new signal MO and the HO of H2 output, wherein, MO is new carry check bit output signal, and HO is that new carry is transmitted signal.
Among Fig. 3 A, if high 4 bits output has carry signal M1=1 in 8 bits of the input of 24 bit decision carry circuit unit 21, the output of 8 bits has carry signal MO=1 certainly so, M1=0 else if, and when hanging down 4 than peculiar carry signal M0=1, then and if only if, and H1 carry propagation signal is 1 o'clock, MO=1.H0 and H1 with obtain 8 bit carry propagation signals.
Utilize 4 bit decision carry circuit unit 21 among Fig. 2 A and 4 bit connecting circuit unit 31 among Fig. 3 A, can build the carry judging unit 3 of any bit.The carry decision circuitry unit 43 that utilizes the carry decision circuitry unit 42 of the judgement carry circuit unit of 4 bits and 16 bit carry decision circuitry unit, 41,32 bits that 4 bit connecting circuit unit are built and 112 bits is shown in Fig. 4 A, 4B, 4C.Wherein, input signal is a and b, and output signal is M, H.M is a carry check bit output signal.
In embodiments of the present invention, utilize the carry judging unit 3 of the carry decision circuitry unit 43 of 112 bits as 106 bits.Utilize the carry decision circuitry unit of described 112 bits, low 6 bits filling 0 (a[5:0]=0, b[5:0]=0), as the carry judging unit 3 in the carry calibration equipment of multiplication CSA compressed tree in the described floating dual MAC, carry out the carry of 106 bits and judge output carry check bit M
112Output signal H
112Do not use in the carry of judging 106 bits, connect the more carry transmission signal of higher bit but can be used as.
Described carry verification unit 4 is used for the carry check bit M according to 3 outputs of carry judging unit, the C after the operand C negate alignment
InvshiftHigh 55 bits, the higher bit maddcarry[105 of the carry compression result of the 23: 2 carry save adders (CSA) 2 compression], carry out carry to correct, export the value of two groups of high 55 bits.
Described carry verification unit 4 comprises a selector switch of 4: 1 51, is judged the check bit M and the 23 of output by carry: the higher bit of the carry compression result of 2 carry save adders (CSA) 2 is selected defeated one 55 bit value.And another 55 bit value is C
InvshiffHigh 55 bits.
Low 106 bits (low 105 bits of maddcarry are filled 0 at lowest order and obtained 106 bits) of these two groups high 55 bit values and the 2 compression outputs of the 23: 2 carry save adders (CSA), form 2 group of 161 bit value madd1[160:0] and madd2[160:0], send in 161 bit adder 5 of adder and multiplier.
As a kind of embodiment, the circuit diagram of carry verification unit 4 as shown in Figure 5, wherein, M is a carry check bit signal, maddcarry[105] be the output higher bit of maddcarry (carry portions of the 23: 2 carry save adders (CSA) 2 compression) output signal as a result of the 23: 2 carry save adders (CSA) 2.As { M, maddcarry[105] }=0, select the signal of 0 path during 0}, as { M, maddcarry[105] }={ 0, select the signal of 1 path during 1}, when M, maddcarry[105] }={ 1, select the signal of 2 paths during 0}, when { M, maddcarry[105] }=1, select the signal of 3 paths during 1}.C
InvshiftSignal directly export as another 55 bit Madd2[160:106] data.
Described carry verification unit 4 utilizes carry check bit signal and compression result maddcarry[105] select, realize the carry verification, make the correct result who under the situation of few delay is tried one's best in increase, obtains carry save adder (CSA) compression, as shown in table 2.
Table 2 carry check bit signal M and compression result maddcarry[105] option table
| M，maddcarry[105] | 00 | 01 | 10 | 11 |
| Madd1[160:106] | 55bit 0 | |
55bit-1 | |
Wherein, maddcarry[105] bit is the higher bit of the 23: 2 carry save adders (CSA) 2 output carries part, is the carries of low 106 bits to high 55 bits, M is that carry is corrected.
The compression result mulcarry and the mulsum addition of the first multiplication carry save adder (CSA) 1 do not have carry in the explanation adder and multiplier when M=0, so the high-order result in the adder and multiplier does not need to correct, the compression result mulcarry of the first multiplication carry save adder (CSA) 1 is added with carry mutually with mulsum in the explanation adder and multiplier when M=1, so the high position in the adder and multiplier needs to correct, just high 55 bits need deduct 1.
As shown in table 1, as M and maddcarry[105] when all being 0, the madd1[160:106 of output] be 55 bits 0;
As M=0 and maddcarry[105] when being 1, do not need to correct carry, high 55 bits need add 1, so the madd1[160:106 of output] be value 1 (high 54 bits are 0, and lowest bit is 1);
As M=1 and maddcarry[105] when being 0, need subtract 1 to high 55 bits, so madd1[160:106] value be-1 (55 bit 1);
As M=1 and maddcarry[105] when being 1, both cancel out each other, so madd1[160:106] value be 55bit0.
Below in conjunction with the drawings to the description of the specific embodiment of the invention, others of the present invention and feature are conspicuous to those skilled in the art.
More than specific embodiments of the invention are described and illustrate it is exemplary that these embodiment should be considered to it, and be not used in and limit the invention, the present invention should make an explanation according to appended claim.
Claims (12)
1, the carry calibration equipment of multiplication CSA compressed tree in a kind of floating dual MAC is characterized in that, comprises a carry judging unit and a carry verification unit, wherein:
Described carry judging unit, being used for two operand A of floating dual MAC and the B compression carry portion that compression obtains through the first multiplication carry save adder and compression and partial data is input value, whether the result who judges addition carry, and according to carry situation output carry check bit M;
Described carry verification unit is used for the carry check bit M according to the output of carry judging unit, the C after the operand C negate alignment
InvshiftHigh 55 bits, the higher bit of the carry compression result of the 2nd 3:2 carry save adder is carried out carry and is corrected, the value of exporting two group of 55 bit is in high 55 of two groups of input data of 161 bit adder; The value of 106 bits of the 2nd 3:2 carry save adder compression output is input among low 106 of two groups of input data.
2, the carry calibration equipment of multiplication CSA compressed tree in the floating dual MAC according to claim 1 is characterized in that, described carry judging unit comprises a plurality of 4 bit decision carry circuit unit and a plurality of 4 bit connecting circuit unit.
3, the carry calibration equipment of multiplication CSA compressed tree in the floating dual MAC according to claim 2, it is characterized in that, utilize described 4 bit decision carry circuit unit and described 4 bit connecting circuit unit to build 16 bit carry decision circuitry unit, the carry decision circuitry unit of the carry decision circuitry unit of 32 bits and 112 bits.
4, the carry calibration equipment of multiplication CSA compressed tree in the floating dual MAC according to claim 3, it is characterized in that, described carry judging unit, it is the carry decision circuitry unit that utilizes described 112 bits, low 6 bits of the carry decision circuitry unit of described 112 bits are filled to 0, carry out the carry of 106 bits and judge.
5, the carry calibration equipment of multiplication CSA compressed tree in the floating dual MAC according to claim 3 is characterized in that, described carry judging unit and the 2nd 3:2 carry save adder concurrent operation are carried out carry and judged.
6, the carry calibration equipment of multiplication CSA compressed tree in the floating dual MAC according to claim 1, it is characterized in that, described carry verification unit comprises the selector switch of a 4:1, is judged that by carry the higher bit of the carry compression result of the check bit M of output and the 2nd 3:2 carry save adder selects to export one 55 bit value.
7, the carry calibration equipment of multiplication CSA compressed tree in the floating dual MAC according to claim 6 is characterized in that, another 55 bit value of described carry verification unit output is C
InvshiftHigh 55 bits.
8, a kind of floating dual MAC, comprise the negate device, the bit aligned shift unit, the first multiplication carry save adder, the 2nd 3:2 carry save adder, the totalizer of 161 bits, and the normalization and the unit that rounds off, it is characterized in that, also comprise a carry calibration equipment with the parallel multiplication CSA compressed tree of the 2nd 3:2 carry save adder;
Described device comprises a carry judging unit and a carry verification unit, wherein:
Described carry judging unit, being used for two operand A of floating dual MAC and the B compression carry portion that compression obtains through the first multiplication carry save adder and compression and partial data is input value, whether the result who judges addition carry, and according to carry situation output carry check bit M;
Described carry verification unit is used for the carry check bit M according to the output of carry judging unit, the C after the operand C negate alignment
InvshiftHigh 55 bits, the higher bit of the carry compression result of the 2nd 3:2 carry save adder is carried out carry and is corrected, the value of exporting two group of 55 bit is in high 55 of two groups of input data of the totalizer of 161 bits; The value of 106 bits of the 2nd 3:2 carry save adder compression output is input among low 106 of two groups of input data.
9, floating dual MAC according to claim 8 is characterized in that, described carry judging unit comprises a plurality of 4 bit decision carry circuit unit and a plurality of 4 bit connecting circuit unit.
10, floating dual MAC according to claim 9, it is characterized in that, described carry judging unit, it is the carry decision circuitry unit that utilizes 112 bits that described 4 bit decision carry circuit unit and described 4 bit connecting circuit unit build, low 6 bits of the carry decision circuitry unit of described 112 bits are filled to 0, carry out the carry of 106 bits and judge.
11, floating dual MAC according to claim 9, it is characterized in that described carry verification unit is the selector switch that comprises a 4:1, judge that by carry the higher bit of the carry compression result of the check bit M of output and the 2nd 3:2 carry save adder selects to export one 55 bit value.
12, floating dual MAC according to claim 11 is characterized in that, another 55 bit value of described carry verification unit output is C
InvshiftHigh 55 bits.
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