CN100543970C - Make the method for optical inductor - Google Patents
Make the method for optical inductor Download PDFInfo
- Publication number
- CN100543970C CN100543970C CNB2008101084140A CN200810108414A CN100543970C CN 100543970 C CN100543970 C CN 100543970C CN B2008101084140 A CNB2008101084140 A CN B2008101084140A CN 200810108414 A CN200810108414 A CN 200810108414A CN 100543970 C CN100543970 C CN 100543970C
- Authority
- CN
- China
- Prior art keywords
- patterning
- layer
- dielectric layer
- silicic dielectric
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000000059 patterning Methods 0.000 claims abstract description 97
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 claims abstract description 59
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 40
- 230000005540 biological transmission Effects 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 248
- 229920002120 photoresistant polymer Polymers 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 29
- 239000011241 protective layer Substances 0.000 claims description 22
- 238000001259 photo etching Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000010408 film Substances 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 238000011161 development Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910020175 SiOH Inorganic materials 0.000 claims description 3
- 239000002159 nanocrystal Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910004205 SiNX Inorganic materials 0.000 claims description 2
- -1 SiONy Inorganic materials 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 229910003465 moissanite Inorganic materials 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 25
- 238000010586 diagram Methods 0.000 description 14
- 208000034699 Vitreous floaters Diseases 0.000 description 10
- 239000003989 dielectric material Substances 0.000 description 7
- 230000009021 linear effect Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 206010034972 Photosensitivity reaction Diseases 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 230000036211 photosensitivity Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
A kind of method of making optical inductor.This method comprises: a substrate is provided, and it comprises a TFT regions and a light-sensitive area; On this substrate, form a patterning first conductive layer; Form a gate dielectric in this substrate and this gate surface; This gate dielectric laminar surface in this grid top forms a patterning amorphous silicon layer; On this substrate, form a patterning second conductive layer; On this substrate, form a patterning silicic dielectric layer; And on this substrate, forming a patterning light transmission conductive layer, it comprises a top electrode of this optical inductor at least, is located at this light-sensitive area.This optical inductor comprises bottom electrode, contains the dielectric layer and the top electrode of silica-rich material, can effectively improve the device reliability of optical inductor, and can integrate the manufacturing process of thin-film transistor and reduce the whole manufacturing process cost of product.
Description
Technical field
The invention relates to that a kind of making optical inductor is in amorphous silicon film transistor (thin filmtransistor, TFT) method of panel, especially (silicon-rich, Si-rich) optical inductor of dielectric material is in the method for amorphous silicon film transistor panel to refer to a kind of making to contain Silicon-rich.
Background technology
Optical inductor is widely used in all types of TFT displays gradually, existing optical inductor is PIN (p-intrinsic-n) diode (photodiode) to utilize three A families and five A family materials to form, yet the light receiving efficiency of PIN diode is on the low side, therefore and be subjected to the influence of non-target light source easily, have shortcomings such as signal to noise ratio is relatively poor.In addition, in the TFT display, three A families that the PINN diode uses and five A family materials and TFT manufacturing process also have the problem of compatibility, and therefore traditional PIN diode all has its development restriction on using with on the production capacity.On the other hand, industry is is also researched and developed the strong photosensitivity of utilizing amorphous silicon material, and makes thin-film transistor inductor (TFTsensor) with amorphous silicon material.Yet the amorphous silicon film transistor inductor has the lower shortcoming of photoelectric current stability, even under the situation of not operating inductor, photoelectric current also can be decayed along with the time, and therefore serious reliability issues is arranged.
Based on above-mentioned various reasons, the employed optical inductor of industry can't satisfy its application on photoelectric field at present, and therefore the optical inductor of a new generation has become the emphasis of research and development.
Summary of the invention
One of purpose of the present invention is to provide a kind of optical inductor is integrated in the method that amorphous is thin-film transistor (a-si TFT) device fabrication, and optical inductor wherein of the present invention is to use the Silicon-rich dielectric material, significantly to improve the production reliability of optical inductor.
The invention provides a kind of method of making optical inductor in the non-crystalline silicon tft panel.Substrate at first is provided, and it comprises non-crystalline silicon tft zone and light-sensitive area, forms patterning first conductive layer then on substrate, and it comprises the grid of non-crystalline silicon tft, is located at this non-crystalline silicon tft zone.Then, form gate dielectric at substrate and gate surface, the gate dielectric laminar surface in the grid top forms the patterning amorphous silicon layer again.Afterwards, form patterning second conductive layer on substrate, it comprises the source electrode of TFT and the bottom electrode of drain electrode and optical inductor, and wherein source electrode is the top of being located at grid with drain electrode, and this bottom electrode is to be located at the light-sensitive area.Form the patterning silicic dielectric layer on substrate, wherein silicic dielectric layer is located at the light-sensitive area at least, and is electrically connected at bottom electrode.In addition, this patterning silicic dielectric layer expose portion drain electrode at least.At last, form the patterning light transmission conductive layer on substrate, it comprises that at least top electrode is located on the light-sensitive area, to form optical inductor.
Because the present invention is applied to the Silicon-rich dielectric material in the optical inductor, and integrate the manufacturing process of optical inductor and non-crystalline silicon tft device, therefore can effectively reduce the whole manufacturing process cost of non-crystalline silicon tft display floater, improve the reliability of product simultaneously.
Description of drawings
Fig. 1 is applied to schematic diagram on the TFT display floater for optical inductor of the present invention.
Fig. 2 to Fig. 7 makes first embodiment of optical inductor for the present invention on the non-crystalline silicon tft panel generalized section.
Fig. 8 makes the generalized section of optical inductor in second embodiment of non-crystalline silicon tft panel for the present invention.
Fig. 9 to Figure 10 makes the schematic diagram of the 3rd embodiment of optical inductor for the present invention.
Figure 11 makes the schematic diagram of the 4th embodiment of optical inductor for the present invention.
Figure 12 to Figure 13 makes the schematic diagram of the 5th embodiment of optical inductor for the present invention.
Figure 14 to Figure 19 makes the schematic diagram of the 6th embodiment of optical inductor for the present invention.
Figure 20 to Figure 23 integrates the schematic diagram of the 7th embodiment of optical inductor and non-crystalline silicon tft device fabrication for the present invention.
Figure 24 is the circuit diagram that comprises the optical touch control type panel 200 of optical inductor of the present invention.
Drawing reference numeral
10 TFT display floaters, 12 periphery circuit regions
14,202 viewing areas, 16,208 pixels
18,204 holding wires, 20,206 scanning linears
22,24,26 environment light sensor spares
28 light-sensing regions, 30 leads
32 connection gaskets, 34 infrabasal plates
36 upper substrates, 38 substrates
52 light-sensitive areas, 50 TFT zone
54 patternings, first conductive layer, 56 grids
58 gate dielectrics, 60 patterning amorphous silicon layers
62 doped amorphous silicon layers, 64 second conductive layers
64 ' patterning, second conductive layer, 66 silicic dielectric layers
First part of 66a silicic dielectric layer
Second part of 66b silicic dielectric layer
68 channel semiconductor layers, 70 source electrode
72 drain electrodes, 74 bottom electrodes
76,214 film transistor devices, 78 protective layers
80,92,94 contact holes 82,134 ' patterning light transmission conductive layer
84 pixel electrodes, 86 top electrodes
88,210 optical inductors, 90 flatness layers
96 silicic dielectric layers, 98 leads
100 amorphous silicon layers, 102,218 photoresist layers
104 the 3rd mask 104a semi-opaque region
Full transparent area 106,122 contact hole patterns of 104b
108,120 patterns of openings, 110,130 contact holes
112,128 openings, 114 connection gasket zones
116 connection gasket bottoms 118,118 ' photoresist layer
124 connection gasket patterns 126 the 3rd mask
126a light tight district 126b semi-opaque region
The full transparent area 132 connection gasket openings of 126c
134 light transmission conductive layer, 136 connection gasket top layers
200 optical touch control type panels, 212 signal read lines
The light tight district of 216 second mask 216a
The full transparent area of 216b semi-opaque region 216c
Embodiment
Please refer to Fig. 1, Fig. 1 is applied to schematic diagram on the non-crystalline silicon tft display floater for optical inductor of the present invention.Non-crystalline silicon tft display floater 10 comprises infrabasal plate 34 and upper substrate 36, and when non-crystalline silicon tft display floater 10 was display panels, infrabasal plate 34 was called array base palte and colored filter substrate again usually with upper substrate 36.Yet TFT display floater 10 also can be the two-d display panel of other types, for example organic electroluminescence display panel.Non-crystalline silicon tft display floater 10 comprises viewing area 14 and periphery circuit region 12 in addition, wherein be provided with a plurality of scanning linears 20 and holding wire 18 in the viewing area 14, define the pixel 16 that is arrayed, each pixel 16 all comprises a TFT device 76 and is electrically connected at scanning linear 20 and holding wire 18.In addition, TFT display floater 10 comprises at least one optical inductor in addition, be arranged at the light-sensing region 28 of 14 peripheries, viewing area, (the ambient light sensor of the environment light sensor spare shown in the figure for example, ALS) 22,24,26, and can electrically connect infrabasal plate 34 lip-deep connection gaskets 32 by lead 30 respectively.
Fig. 2 to Fig. 7 shows that the present invention makes the generalized section of first embodiment of optical inductor on the non-crystalline silicon tft panel.At first as shown in Figure 2, provide substrate 38, the array base palte that it can be two-d display panel comprises at least one TFT zone 50 and at least one light-sensitive area 52.Comprehensive deposition first conductive layer on substrate 38 then carries out photoetching and etching manufacturing process and forms patterning first conductive layer 54 with the first road mask, and it comprises that grid 56 is located at TFT zone 50, wherein the patterning first conductive layer 54 preferable metal materials that comprise.Then, as shown in Figure 3, form gate dielectric 58, form amorphous silicon layer and doped amorphous silicon layer in going up of gate dielectric 58 in regular turn again at substrate 38 and grid 56 surface depositions.This amorphous silicon layer and doped amorphous silicon layer are carried out photoetching and etching manufacturing process with the second road mask, be located at gate dielectric 58 surfaces of grid 56 tops to form patterning amorphous silicon layer 60 and the doped amorphous silicon layer 62 of patterning, wherein patterning amorphous silicon layer 60 comprises the channel semiconductor zone of TFT device.
Please refer to Fig. 4, then form second conductive layer 64 and the silicic dielectric layer 66 that contains the Silicon-rich atom in regular turn on substrate 38, wherein silicic dielectric layer 66 is to be the good dielectric layer of photonasty, and its material comprises the combination of silicon, oxygen, nitrogen, carbon or hydrogen.Then, coating first photoresist layer (figure does not show) on substrate 38 surfaces, carry out photoetching and etching manufacturing process by the 3rd road mask again and on first photoresist layer, define pattern corresponding to light-sensitive area 52, remove part silicic dielectric layer 66 through dry type or wet etching, in light-sensitive area 52, to form the silicic dielectric layer 66 that comprises patterning, remove the first remaining photoresist layer again.It should be noted that, the molecular formula of silicic dielectric layer 66 comprises the combination of SiOC, SiC, SiOx, SiNx, SiONy, SiOH or above-mentioned material, and the method that forms silicic dielectric layer 66 is the gas that can contain silicon, oxygen, nitrogen, carbon, hydrogen or above-mentioned former sub-portfolio by feeding, carry out the chemical vapour deposition (CVD) manufacturing process, for example feed and contain SiH
4/ N
2The gas of O deposits manufacturing process can make the silicic dielectric layer 66 that contains the SiOx material, perhaps feeds SiH
4/ N
2O/H
2Gas is made the silicic dielectric layer 66 that contains SiOH.In addition, because silicic dielectric layer 66 is to be used for being used as photosensitive material in the present invention, therefore when forming silicic dielectric layer 66, can be used for the colored light of sensing different colours by the composition of adjusting its material.Moreover, when forming silicic dielectric layer 66, also can carry out laser annealing step, to form silicon nanocrystal grain (silicon nanocrystal) in silicic dielectric layer 66 to silica-rich material.
Please refer to Fig. 5, then form second photoresist layer (figure does not show) in addition, and carry out the 4th photoetching and etching manufacturing process by the 4th road mask in substrate 38 surfaces.At first after exposure imaging, remove part second conductive layer 64 that is not covered via dry etching or wet etching again by second photoresist layer, forming patterning second conductive layer 64 ', it comprises is located in the TFT zone 50 and mutual disjunct source electrode 70 and drain electrode 72 and the bottom electrode 74 of being located at the optical inductor in the light-sensitive area 52.It should be noted that, in the 4th photoetching and etching manufacturing process, also remove part doped amorphous silicon layer 62, and source electrode 70 can be electrically connected at patterning amorphous silicon layer 60 via remaining doped amorphous silicon layer 62 respectively with drain electrode 72, so just finish the making of a TFT device 76 on the substrate 38.On the other hand, the bottom electrode 74 of being located at light-sensitive area 52 is belows of being located at the silicic dielectric layer 66 of patterning, and is electrically connected at silicic dielectric layer 66.It should be noted that, in other embodiments of the invention, the carrying out order of aforementioned the 3rd, the 4th photoetching and etching manufacturing process also can be exchanged mutually, for example after forming second conductive layer 64, directly carry out aforementioned the 4th photoetching and etching manufacturing process and form patterning second conductive layer 64 ', make source electrode 70, drain electrode 72 and bottom electrode 74, form silicic dielectric layer 66 afterwards again, and carry out aforementioned the 3rd photoetching and etching manufacturing process with patterning silicic dielectric layer 66, be located in the light-sensitive area 52.
Then, as shown in Figure 6, deposit the good protective layer 78 of one deck water-resistance on substrate 38, it can comprise inorganic material, for example silicon nitride or silica material comprehensively.Carry out photoetching and etching manufacturing process by the 5th road mask subsequently, remove partial protection layer 78 and formation contact hole 80, expose part drain electrode 72 and most patterning silicic dielectric layer 66 simultaneously.Please refer to Fig. 7, deposit a light transmission conductive layer at last, for example comprise tin indium oxide (indium tin oxide, ITO) or indium zinc oxide (indium zinc oxide, IZO) material, carry out photoetching and etching manufacturing process via the 6th road mask again and form patterning light transmission conductive layer 82, it comprises the top electrode 86 of pixel electrode 84 and optical inductor, be located at TFT zone 50 and light-sensitive area 52 respectively, wherein pixel electrode 84 is to electrically connect drain electrode 72 via the patterning light transmission conductive layer 82 of inserting contact hole 80, and top electrode 86 is upper surfaces of being located at silicic dielectric layer 66, forms optical inductor 88 with silicic dielectric layer 66 and bottom electrode 74.
Fig. 8 makes the generalized section of optical inductor in second embodiment of non-crystalline silicon tft panel for the present invention, and wherein Fig. 8 has illustrated the step behind the previous embodiment Fig. 5 that continues.The second embodiment of the present invention is to replace protective layer 78 among first embodiment with the organic photoresist material.As shown in Figure 8, after forming source electrode 70, drain electrode 72, bottom electrode 74 and silicic dielectric layer 66, on substrate 38, form flatness layer 90 and cover TFT devices 76 and silicic dielectric layer 66, as the protective layer of TFT device 76.Flatness layer 90 is to comprise the photoresist material, for example for comprising the photoresist layer of organic material.Then, expose with the development manufacturing process with patterning flatness layer 90, in flatness layer 90, form contact hole 80,92, expose part drain electrode 72 and part silicic dielectric layer 66 respectively.Afterwards, the described formation patterning of first embodiment light transmission conductive layer 82 for another example, be covered in the contact drain electrode 72 that exposes of hole 80 in TFT zone 50, and be covered on the silicic dielectric layer 66 that exposes of contact hole 92 in light-sensitive area 52, and the part that patterning light transmission conductive layer 82 electrically connects silicic dielectric layer 66 is to be used as top electrode 56, just finishes the making that optical inductor 88 is integrated in non-crystalline silicon tft device 76.
Fig. 9 to Figure 10 makes the schematic diagram of the 3rd embodiment of optical inductor for the present invention, and wherein Fig. 9 is a hookup 3.As shown in Figure 9, after forming patterning amorphous silicon layer 60 and doped amorphous silicon layer 62, on substrate 38, form patterning second conductive layer 64 ', comprise source electrode 70, drain electrode 72 and bottom electrode 74.Its generation type can deposit one second conductive layer (second conductive layer 64 as shown in Figure 4) and photoresist layer (figure does not show) earlier comprehensively, carry out photoetching and etching manufacturing process then, remove part second conductive layer 64 and part doped amorphous silicon layer 62 through exposure and etch step.Then, form patterned protective layer 78 on substrate 38, it comprises that formation contact hole 80 is to expose part drain electrode 72 and to contact hole 92 to expose most of bottom electrode 74.
Then as shown in figure 10, form silicic dielectric layers 66, to remove part silicic dielectric layer 66, the silicic dielectric layer 66 of patterning is located in the light-sensitive area 52 via photoetching and etching manufacturing process on substrate 38 surface.In other embodiments, can comprise and form silicic dielectric layer 66 simultaneously in the light-sensitive area 52 and TFT zone 50.Subsequently, on substrate 38, form the patterning light transmission conductive layer, comprise the top electrode 86 of pixel electrode 84 and optical inductor 88, electrically connect drain electrode 72 and silicic dielectric layer 66 respectively.Therefore, so present embodiment and first embodiment of the invention difference form protective layer 78 earlier, form silicic dielectric layer 66 again on substrate 38.
In other embodiments of the invention, part silicic dielectric layer 66 also can be formed at TFT zone 50 simultaneously.Please refer to Figure 11, Figure 11 makes the schematic diagram of the 4th embodiment of optical inductor for the present invention, and Figure 11 is the manufacturing process of continuity previous embodiment Fig. 9.According in this example; be after forming TFT device 76 and protective layer 78; then on substrate 38, form the silicic dielectric layer 66 of patterning; it comprises first part 66a that is located at light-sensitive area 52 and the second portion 66b that is located at TFT zone 50; wherein first of silicic dielectric layer 66 partly 66a can be used as photosensitive material in the optical inductor 88, and second portion 66b also can be used as another protective layer in TFT device 76 or source electrode 70, the drain electrode 72.The formation method of the silicic dielectric layer 66 of patterning is to deposit silicic dielectric layer 66 earlier on substrate 38 comprehensively, carry out photoetching and etching manufacturing process then, remove part silicic dielectric layer 66 and stay respectively silicic dielectric layer 66 first partly 66a with second partly 66b in light-sensitive area 52 and TFT zone 50.Then, form patterning light transmission conductive layer 82 again on substrate 38, it comprises the top electrode 86 of being located at light-sensitive area 52 and the pixel electrode 84 of being located at TFT zone 50.
Figure 12 to Figure 13 makes the schematic diagram of the 5th embodiment of optical inductor for the present invention.Present embodiment is the protective layer 78 that replaces among the 3rd embodiment with silicic dielectric layer 66.At first please refer to Figure 12, it is the manufacturing process behind the hookup 3, as described in the 3rd embodiment, after forming patterning amorphous silicon layer 60 and doped amorphous silicon layer 62, deposit, manufacturing process such as photoetching, etching, and on substrate 38, form patterning second conductive layer 64 ', comprise source electrode 70, drain electrode 72 and bottom electrode 74, remove part doped amorphous silicon layer 62 simultaneously, to form TFT device 76.Then, on substrate 38, deposit silicic dielectric layer 96 comprehensively, remove part silicic dielectric layer 96 via photoetching and etching manufacturing process, make remaining silicic dielectric layer 96 cover most TFT device 76 and bottom electrode 74, and form contact hole 94 to expose part drain electrode 72.Then as shown in figure 13, on substrate 38, form patterning light transmission conductive layer 82, comprise pixel electrode 84 that electrically connects drain electrode 72 and the top electrode 86 of being located at light-sensitive area 52, the optical inductor 88 of just finishing fifth embodiment of the invention is integrated in the making of non-crystalline silicon tft device 76.
Please refer to Figure 14 to Figure 19, Figure 14 to 19 makes the schematic diagram of the 6th embodiment of optical inductor on the non-crystalline silicon tft panel for the present invention.In the present embodiment, make optical inductor of the present invention and only need use four road masks to finish in the method for non-crystalline silicon tft panel, be simplified illustration, the device identical with previous embodiment is to use the same device symbol to represent.At first as shown in figure 14, provide substrate 38, definition has TFT zone 50 and light-sensitive area 52 on it.Deposition first conductive layer on substrate 38 uses the first road mask to carry out photoetching and etching manufacturing process, and forms patterning first conductive layer 54 then, comprises that grid 56 is located at TFT zone 50.In the present embodiment, patterning first conductive layer 54 comprises the lead of being located in the light-sensitive area 52 98 in addition, yet in other embodiments, patterning first conductive layer 54 also can not comprise the lead of being located in the light-sensitive area 52 98.Then, on substrate 38, form gate dielectric 58 cover gate 56 and lead 98 comprehensively.
Then please refer to Figure 15, on substrate 38, form amorphous silicon layer 100, doped amorphous silicon layer 62, second conductive layer 64 and silicic dielectric layer 66 in regular turn.Form photoresist layer 218 on substrate 38 surfaces then; use second mask 216 to define source electrode 70, drain electrode 72, channel semiconductor layer 68 (being semiconductor regions), the photosensitive material pattern of optical inductor and the pattern precalculated position of bottom electrode 74 in this photoresist layer, wherein second mask can be gray-tone mask, half-tone mask or phase shift mask.With the half-tone mask is example, the light tight district 216a of second mask 216 is the positions corresponding to predetermined source electrode 70, drain electrode 72 and bottom electrode 74, semi-opaque region 216b is the position corresponding to predetermined channel semiconductor layer 68, and full transparent area 216c is then corresponding to the part beyond TFT zone 50 and the light-sensitive area 52.Then, as shown in figure 16, carry out the etching manufacturing process, remove the part silicic dielectric layer 66, second conductive layer 64, the doped amorphous silicon layer 62 and amorphous silicon layer 100 that are not covered by photoresist layer 218, forming the silicic dielectric layer 66 of channel semiconductor layer 68, source electrode 70, drain electrode 72, bottom electrode 74 and patterning, and finish the making of TFT device 76.This moment silicic dielectric layer 66 comprise first partly 66a be located in the light-sensitive area 52 and be positioned at the upper surface of bottom electrode 74, have the photosensitive material pattern, and comprise that in addition second portion 66b is located at the upper surface of source electrode 70 and drain electrode 72.
Please refer to Figure 17, then remove photoresist layer 218, form protective layer 78 and photoresist layer 102 on substrate 38 surfaces in regular turn.Use 104 pairs of photoresist layers of the 3rd mask 102 to carry out a lithographic fabrication processes; similarly; the 3rd mask 104 can be gray-tone mask, half-tone mask or phase shift mask; for example when the 3rd mask 104 is half-tone mask; its semi-opaque region 104a be can be rough corresponding to first 66a partly of silicic dielectric layers 66 in the light-sensitive area 52, full transparent area 104b is then corresponding to the predetermined contact hole pattern in the drain electrode 74.The manufacturing process of developing then, patterning photoresist layer 102 and make it comprise contact hole pattern 106 and patterns of openings 108, wherein interlayer hole pattern 106 is to expose partial protection layer 78.
Then as shown in figure 18, photoresist layer 102 with patterning is used as the etching shade, carry out anisotropic etching manufacturing process, remove part dielectric layer 78 and silicic dielectric layer 66,50 form respectively with light-sensitive area 52 and contacts hole 110 and opening 112 in TFT zone, expose the first part 66a of part drain electrode 72 and silicic dielectric layer 66 respectively.
Then, please refer to Figure 19, on substrate 38, form patterning light transmission conductive layer 82, its formation method comprises comprehensive light transmission conductive layer and photoresist layer (figure does not show) of forming on substrate 38 earlier, use the 4th mask to carry out photoetching and etching manufacturing process then, remove the part light transmission conductive layer, fill in the contact hole 110 and form pixel electrode 84 in TFT zone 50, electrically connect drain electrode 72, and formation top electrode 86 fills in opening 112 in light-sensitive area 52, be located at the first part 66a upper surface of silicic dielectric layer 66, to finish the making that optical inductor 88 of the present invention is integrated in non-crystalline silicon tft device 76.
Figure 20 to Figure 23 integrates the schematic diagram of the 7th embodiment of optical inductor and non-crystalline silicon tft device fabrication for the present invention.In the present embodiment, the inventive method only need use three road masks and three road lithographic fabrication processes can make TFT device and optical inductor of the present invention on the non-crystalline silicon tft panel.At first, please refer to Figure 20, substrate 38 is provided, its surface definition has TFT zone 50, light-sensitive area 52 and connection gasket 114 zones, the described method of embodiment Figure 14 to 16 is as described above made TFT device 76 and silicic dielectric layer 66 then, and when forming grid 56, make connection gasket bottom 116 in connection gasket zone 114 simultaneously, and when carrying out gate dielectric 58 manufacturing process, also in the lump gate dielectric 58 is covered on the connection gasket bottom 116.Then; after finishing the step of Figure 16 and removing photoresist layer 218; on substrate 38, form protective layer 78 and photoresist layer 118 in regular turn; re-use the 3rd mask 126 and carry out photoetching; the development manufacturing process is come patterning photoresist layer 118; in photoresist layer 118, define patterns of openings 120; contact hole pattern 122 and connection gasket pattern 124; wherein the light tight district 126a of the 3rd mask 126 is the partial protection layer 78 that stay corresponding to needs; full transparent area 126c can be corresponding to connection gasket pattern 124 and contact hole pattern 122, and semi-opaque region 126b then can be corresponding to patterns of openings 120 and selectivity corresponding to a side of contact hole pattern 122 and the marginal portion of light-sensitive area 52.
Then as shown in figure 21; photoresist layer 118 with patterning is used as the etching shade; carry out the etching manufacturing process; remove partial protection layer 78, silicic dielectric layer 66 and gate dielectric 58; 52 protective layer 78 forms opening 128 in the light-sensitive area respectively, forms contact hole 130 and expose part drain electrode 72 above drain electrode 72, and form connection gasket opening 132 in connection gasket zone 114; expose connection gasket bottom 116, and stay part photoresist layer 118 ' corresponding to light tight district 126a.Then, as shown in figure 22, on substrate 38, form light transmission conductive layer 134 comprehensively.At last, please refer to Figure 23, peel off (lift-off) manufacturing process, when removing photoresist layer 118 ', remove simultaneously be formed on photoresist layer 118 ' on light transmission conductive layer 134, the transparency conducting layer 134 that is not formed on the photoresist layer 118 ' then is retained, its remaining part is then respectively in the light-sensitive area 52, TFT zone 50 forms top electrode 86 with connection gasket zone 114, pixel electrode 84 and connection gasket top layer 136 with drain electrode 72 electric connections, wherein connection gasket top layer 136 electrically connects mutually with connection gasket bottom 116, can form connection gasket 32 as shown in Figure 1.
As previously mentioned, optical inductor of the present invention can only use three to six road masks, and cooperates the manufacturing process of TFT device and be made on the non-crystalline silicon tft panel, can effectively simplify whole manufacturing process cost.In addition, optical inductor of the present invention not only can be arranged at the periphery, viewing area of display floater and be used as the environment light source inductor, also can be arranged in each pixel of viewing area, cooperate the colored filter on the panel or adjust silicic dielectric layer the photosensitive material pattern and as the chromatic image sensor, perhaps also can utilize its photoinduction electric current and circuit design of producing, the non-crystalline silicon tft panel is made as optical touch control type panel (optical touch panel) or fingerprint identifier (finger print sensor).
Please refer to Figure 24, Figure 24 comprises the optical touch control type panel 200 of optical inductor of the present invention or the circuit diagram of fingerprint identifier.Optical touch control type panel 200 comprises viewing area 202, it is provided with a plurality of holding wires parallel to each other 204 and signal read line 212 and a plurality of scanning linears 206 perpendicular to holding wire 204, define a plurality of pixels 208 that are arranged, each pixel 208 comprises at least one TFT device 214 and at least one optical inductor 210 respectively, electrically connects holding wire 204 and signal read line 212 respectively.When operating optical touch panel 200, if arbitrary position of user's touch-control optical touch control type panel 200, just can cover the surface of this position institute respective pixel 208, make the photoinduction electric current of the optical inductor 210 in these pixels 208 change, and optical touch control type panel 200 just can be according to being changed by the resulting electric currents of signal read line 212 and then those positions on the panel of having judged user's touch-control, and then optical touch control type panel 200 is sent instruction.
Compared to known technology, the invention provides the optical inductor that comprises the Silicon-rich dielectric material, it has good product reliability, when being applied in as ultraviolet light blue light detectors such as (UV-blue), signal to noise ratio (N/Sratio) can reach 200 to 300, also has good luminous sensitivity (photosensitivity).Particularly the inventive method is the manufacturing process that the optical inductor that will contain the Silicon-rich dielectric material is integrated in the non-crystalline silicon tft device, by the particular design of mask and thin film deposition order, can effectively reduce manufacturing technology steps, cost and time.Moreover the optical inductor that the present invention contains the Silicon-rich dielectric material can be applicable to touch panel in addition, can reduce the manufacturing cost of traditional touch panel simultaneously, and can improve the product surcharge.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; any have a technical field of the invention know the knowledgeable usually; without departing from the spirit and scope of the present invention; when doing various changes and retouching; and can think to carry other different embodiment, so protection scope of the present invention attached claim person of defining before looking is as the criterion.
Claims (23)
1. method of on the amorphous silicon film transistor panel, making optical inductor, this method comprises:
One substrate is provided, and it comprises a TFT regions and a light-sensitive area;
Form a patterning first conductive layer on described substrate, this patterning first conductive layer comprises a grid of a thin-film transistor, is located at this TFT regions;
Form a gate dielectric in described substrate and described gate surface;
Described gate dielectric laminar surface in described grid top forms a patterning amorphous silicon layer;
On described substrate, form a patterning second conductive layer, it comprises the one source pole of described thin-film transistor and a bottom electrode of a drain electrode and an optical inductor, and this source electrode and this drain electrode are the tops of being located at described grid, and described bottom electrode is to be located at described light-sensitive area;
Form a patterning silicic dielectric layer on described substrate, this patterning silicic dielectric layer comprises to be located at described light-sensitive area and to electrically connect described bottom electrode, and the described drain electrode of expose portion at least of described patterning silicic dielectric layer; And
Form a patterning light transmission conductive layer on described substrate, it comprises a top electrode of described optical inductor at least, is located at described light-sensitive area.
2. the method for claim 1 is characterized in that, the material of described patterning silicic dielectric layer comprises the combination of silicon, oxygen, nitrogen, carbon or hydrogen.
3. the method for claim 1 is characterized in that, the molecular formula of described patterning silicic dielectric layer is the combination of SiOC, SiC, SiOx, SiNx, SiONy, SiOH or above-mentioned material.
4. the method for claim 1, it is characterized in that, the method that forms described patterning silicic dielectric layer comprises prior to forming a silicic dielectric layer on the described substrate, carry out a photoetching and etching manufacturing process again with the described silicic dielectric layer of patterning, and the method that forms described silicic dielectric layer comprises and carries out a chemical vapour deposition (CVD) manufacturing process.
5. method as claimed in claim 4 is characterized in that, when carrying out described chemical vapour deposition (CVD) manufacturing process, is to feed the gas that contains silicon, oxygen, nitrogen, carbon, hydrogen or above-mentioned former sub-portfolio.
6. the method for claim 1 is characterized in that, described patterning silicic dielectric layer is covered in the part surface of described source electrode and described drain electrode.
7. the method for claim 1; it is characterized in that; this method be included in addition form described patterning silicic dielectric layer after, on described substrate, form a patterning protective layer, cover described drain electrode of described thin-film transistor and expose portion and described patterning silicic dielectric layer.
8. method as claimed in claim 7 is characterized in that, described patterning protective layer comprises the organic photoresist material.
9. method as claimed in claim 8 is characterized in that, the formation method of described patterning protective layer comprises:
After forming described patterning silicic dielectric layer, on described substrate, deposit an organic photoresist layer comprehensively;
Carry out an exposure manufacturing process, on described organic photoresist layer, define a contact hole pattern and a patterns of openings, be located at described TFT regions and described light-sensitive area respectively; And
Carry out a development manufacturing process, remove the described organic photoresist layer of the part that comprises described contact hole pattern and described patterns of openings, to form described patterning protective layer.
10. method as claimed in claim 7 is characterized in that, the step that forms described patterning second conductive layer, described patterning silicic dielectric layer and described patterning protective layer comprises:
On described substrate, form one second conductive layer and a silicic dielectric layer in regular turn comprehensively;
Remove described second conductive layer of part and the described silicic dielectric layer of part simultaneously, forming described patterning second conductive layer, and make described silicic dielectric layer have identical pattern in described light-sensitive area with described patterning second conductive layer;
On described substrate, form a dielectric layer comprehensively; And
Use a halftoning mask; carry out a photoetching and etching manufacturing process; remove described dielectric layer of part and the described silicic dielectric layer of part simultaneously; forming described patterning silicic dielectric layer, and make described dielectric layer form described patterning protective layer and described drain electrode of expose portion and described patterning silicic dielectric layer.
11. method as claimed in claim 10 is characterized in that, the part semi-opaque region of described half-tone mask is corresponding to described silicic dielectric layer or described light-sensitive area.
12. the method for claim 1 is characterized in that, the method that forms described patterning amorphous silicon layer and described patterning second conductive layer comprises:
After forming described gate dielectric, on described substrate, form an amorphous silicon layer, one second conductive layer, a silicic dielectric layer and a photoresist layer in regular turn;
Use a halftoning mask, on described photoresist layer, define the pattern of the semiconductor passage area of described source electrode, described drain electrode, described bottom electrode and described thin-film transistor;
Be used as the etching shade with described photoresist layer, carry out an etching manufacturing process, to remove the described silicic dielectric layer of part, described second conduction and the described amorphous silicon layer of part of part simultaneously, make remaining described silicic dielectric layer have identical pattern, and expose the described amorphous silicon layer of part in described TFT regions with described patterning second conductive layer.
13. the method for claim 1, it is characterized in that, one semi-opaque region of described half-tone mask is corresponding to described channel semiconductor zone, and a light tight district of described half-tone mask is corresponding to described drain electrode, described source electrode and described bottom electrode.
14. the method for claim 1; it is characterized in that; described method is included in addition and forms before the described patterning silicic dielectric layer, forms a protective layer on described substrate, covers described drain electrode of described thin-film transistor and expose portion and described bottom electrode.
15. the method for claim 1, it is characterized in that this method comprises the pattern that utilizes five road masks to define described grid, described patterning amorphous silicon layer, described source electrode and described drain electrode, described patterning silicic dielectric layer and described patterned transparent conductive layer respectively.
16. the method for claim 1 is characterized in that, described patterning light transmission conductive layer comprises a pixel electrode, is electrically connected at described drain electrode.
17. the method for claim 1 is characterized in that, the method for making described patterning amorphous silicon layer, described patterning second conductive layer and described patterning silicic dielectric layer comprises:
On described substrate, form an amorphous silicon layer, one second conductive layer and a silicic dielectric layer in regular turn comprehensively; And
Carry out a photoetching and etching manufacturing process, remove the described amorphous silicon layer of part, described second conductive layer of part and the described silicic dielectric layer of part simultaneously, to form the semiconductor passage area in described TFT regions, on described grid, form described source electrode and described drain electrode and to form described bottom electrode and described patterning silicic dielectric layer in described light-sensitive area.
18. method as claimed in claim 17 is characterized in that, this method is included in addition and forms before the described patterning light transmission conductive layer, carries out the following step earlier:
On described substrate, deposit a protective layer and a photoresist layer in regular turn;
Use a halftoning mask to carry out a lithographic fabrication processes, the described photoresist layer of patterning makes the described photoresist layer of patterning comprise a contact hole pattern and a patterns of openings; And
Described photoresist layer with patterning is used as the etching shade; carry out an etching manufacturing process; remove described protective layer of the part that is positioned at described TFT regions and described silicic dielectric layer; and remove the described protective layer of the part that is positioned at described light-sensitive area simultaneously, form one respectively at described TFT regions and described light-sensitive area and contact a hole and an opening.
19. method as claimed in claim 18 is characterized in that, a semi-opaque region of described half-tone mask is corresponding to described patterns of openings, and a full transparent area of described half-tone mask is corresponding to described contact hole pattern.
20., it is characterized in that this method comprises in addition as claim 18 a described method:
On described substrate, form a light transmission conductive layer, be covered on the described substrate comprehensively; And
Carry out peeling off manufacturing process, remove the described photoresist layer and the described light transmission conductive layer that is positioned on the described photoresist layer of patterning simultaneously, to form described patterning light transmission conductive layer.
21., it is characterized in that described substrate comprises a connection gasket zone in addition, and described method comprises in addition as claim 1 a described method:
When forming described grid, form a connection gasket bottom in described connection gasket zone simultaneously; And
When forming described patterning light transmission conductive layer, form the surface that a connection gasket top layer is located at described connection gasket bottom simultaneously.
22., it is characterized in that described silicic dielectric layer comprises silicon nanocrystal grain material as claim 1 a described method.
23., it is characterized in that described bottom electrode comprises metal material as claim 1 a described method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008101084140A CN100543970C (en) | 2008-05-27 | 2008-05-27 | Make the method for optical inductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008101084140A CN100543970C (en) | 2008-05-27 | 2008-05-27 | Make the method for optical inductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101281887A CN101281887A (en) | 2008-10-08 |
| CN100543970C true CN100543970C (en) | 2009-09-23 |
Family
ID=40014274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2008101084140A Active CN100543970C (en) | 2008-05-27 | 2008-05-27 | Make the method for optical inductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100543970C (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101995981B (en) * | 2009-08-11 | 2013-02-13 | 北京京东方光电科技有限公司 | Sensing baseplate and manufacture method thereof |
| TWI453805B (en) * | 2011-02-11 | 2014-09-21 | Au Optronics Corp | Display and manufacturing method thereof |
| CN103715137B (en) * | 2013-12-26 | 2018-02-06 | 京东方科技集团股份有限公司 | Array base palte and its manufacture method, display device |
| TWI591841B (en) * | 2015-06-10 | 2017-07-11 | 友達光電股份有限公司 | Sensor and manufacturing method of sensor |
| CN107515488B (en) * | 2017-08-01 | 2020-06-23 | 惠科股份有限公司 | Display panel |
| CN107863319B (en) * | 2017-09-25 | 2021-04-02 | 惠科股份有限公司 | Array substrate and manufacturing method thereof |
| CN107863353A (en) * | 2017-09-25 | 2018-03-30 | 惠科股份有限公司 | A kind of manufacture method of array base palte and array base palte |
| NL2020612B1 (en) * | 2017-12-22 | 2019-07-02 | Illumina Inc | Light detection devices with protective liner and methods of manufacturing same |
| CN113097237B (en) * | 2020-01-09 | 2023-08-29 | 张志峰 | Perovskite-based image sensor chip and preparation method thereof |
| CN114188390A (en) * | 2021-12-09 | 2022-03-15 | 武汉华星光电技术有限公司 | Display panel and method for manufacturing the same |
-
2008
- 2008-05-27 CN CNB2008101084140A patent/CN100543970C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101281887A (en) | 2008-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100543970C (en) | Make the method for optical inductor | |
| US7790487B2 (en) | Method for fabricating photo sensor | |
| US7413940B2 (en) | Thin-film transistor and fabrication method thereof | |
| CN102656698B (en) | Active matrix substrate and method for manufacturing same | |
| CN102034750A (en) | Array substrate and manufacturing method thereof | |
| TWI574374B (en) | Method of fabricating optical sensor device and thin film transistor device | |
| CN102723269A (en) | Array base plate, method for manufacturing same, and display device | |
| TWI464808B (en) | Thin film transistor array substrate and method for fabricating the same | |
| US9190446B1 (en) | Sensing apparatus | |
| WO2013078941A1 (en) | Sensor manufacturing method | |
| CN103033997B (en) | Display device and method for manufacturing the same | |
| CN100499082C (en) | Thin-film transistor substrate and its manufacture method | |
| CN101692439B (en) | Manufacturing method for a plurality of groups of substrates of thin-film transistor | |
| CN101964309B (en) | Manufacturing method of thin film transistor | |
| CN101494256B (en) | X ray sensor and manufacturing method thereof | |
| CN102956550A (en) | Method for manufacturing active array substrate and active array substrate | |
| US20130252384A1 (en) | Trench forming method, metal wiring forming method, and method of manufacturing thin film transistor array panel | |
| CN101598990B (en) | Touch panel and method for forming same | |
| CN101150093B (en) | Pixel structure making method | |
| CN108198819B (en) | Array substrate and preparation method thereof | |
| CN100380634C (en) | Method for making picture element structure | |
| CN101308815A (en) | Image sensor construction and method for making the same | |
| CN110647256A (en) | Manufacturing method of In-cell touch panel | |
| CN101022093B (en) | Method for producing picture element structure | |
| KR100864608B1 (en) | Method Of Manufacturing Thin Film Transistor For Liquid Crystal Display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20240124 Address after: 825 Waterscreek Avenue, Unit 250, Allen, Texas 75013, USA Patentee after: Optoelectronic Science Co.,Ltd. Country or region after: U.S.A. Address before: Hsinchu City, Taiwan, China Patentee before: AU OPTRONICS Corp. Country or region before: China |
|
| TR01 | Transfer of patent right |