CN100541829C

CN100541829C - InGaAs low table alignment or area array infrared detector chip

Info

Publication number: CN100541829C
Application number: CNB2007100476249A
Authority: CN
Inventors: 唐恒敬; 吴小利; 张可锋; 汪洋; 刘向阳; 李永富; 吴家荣; 李雪; 龚海梅
Original assignee: Shanghai Institute of Technical Physics of CAS
Current assignee: Shanghai Institute of Technical Physics of CAS
Priority date: 2007-10-31
Filing date: 2007-10-31
Publication date: 2009-09-16
Anticipated expiration: 2027-10-31
Also published as: CN101170144A

Abstract

The invention discloses a kind of InGaAs low table alignment or area array infrared detector chip, comprising: on the p-InP/InGaAs/n-InP epitaxial wafer, form alignment or the little table top of face battle array p-InP by etching.On the little table top of p-InP, be equipped with the Au/Zn/Pt/Au/P electrode district with its ohmic contact, on alignment or the little table top of face battle array limit, have one to be etched to the n-InP layer and to place public N electrode district on the n-InP layer.Except that P, N electrode district, on the whole epitaxial wafer, comprise that the side is coated with silicon nitride passivation.On the P electrode district, be equipped with the electrode interconnection district with reading circuit interconnection, this little table top in cover part, electrode interconnection district, and extend to the plane from little table top.Advantage of the present invention is: the InGaAs layer of reservation can make table top reduce, and the side of InGaAs layer is effectively protected.Silicon nitride passivation can effectively play antireflection and reduce the effect of InP and InGaAs laminar surface attitude, can increase the quantum efficiency of detector and reduce dark current.The P electrode adopts AuZnPtAu, can form good ohmic contact with p-InP, and Pt can effectively stop the outdiffusion of Zn, the raising device reliability.

Description

InGaAs low table alignment or area array infrared detector chip

Technical field

The present invention relates to Infrared Detectors, specifically be meant p-InP/InGaAs/n-InP (PIN) low table alignment or area array infrared detector chip.

Background technology

PIN indium gallium arsenic detector mainly is divided into plane and mesa two classes at present.Plane type PIN indium gallium arsenic detector adopts the method for Zn diffusion to realize that at the cap layer InP of n-InP/InGaAs/n-InP the p type mixes mostly.This method can access the indium gallium arsenic detector of higher detectivity, but it has some inevitable shortcomings: diffusion technology complexity, photosurface enlarge and Zn diffusion meeting causes a large amount of defectives in the InP layer, and these have all limited the raising of indium gallium arsenic detector performance.Mesa indium gallium arsenic detector is that the p-InP/InGaAs in the epitaxial material is etched into a table top, and p-InP is thinner for the cap layer, is generally 0.1～0.5 μ m, and the InGaAs absorbed layer is thicker, is generally 1.5～3 μ m.The advantage of this structure is that technology is comparatively simple, and shortcoming is that the side of thicker absorbed layer exposes a large amount of interfacial state of introducing, and this has limited the raising of device detectivity to a great extent, and bad side passivation meeting reduces the reliability of device.In addition, realize reliably that on p-InP cap layer it also is a difficult problem that Ohm contact electrode is drawn.

Summary of the invention

Based on the problem that exists on the above-mentioned existing device architecture, the objective of the invention is to propose a kind of p-InP/InGaAs/n-InP low table alignment or area array infrared detector chip, height by the reduction table top solves absorbed layer side exposed problems, reaches with the good ohmic of p-InP layer by the optimization ohmic contact layer to contact.

P-InP/InGaAs/n-InP low table alignment of the present invention or area array infrared detector chip comprise: form alignment or the little table top of face battle array p-InP by etching on the p-InP/InGaAs/n-InP epitaxial wafer.Be equipped with the P electrode district on the regional area of the little table top of p-InP, with the P electrode employing Au/Zn/Pt/Au of p-InP ohmic contact, Au, Zn, Pt, Au are grown in the P electrode district successively; On alignment or the little table top of face battle array limit, have one to be etched to the n-InP layer and to place common electrode area on the n-InP layer, i.e. the N electrode district.Except that P, N electrode district, on the whole epitaxial wafer, comprise that the side of little table top all is coated with silicon nitride passivation.On the P electrode district, be equipped with the electrode interconnection district with reading circuit interconnection, this little table top in cover part, electrode interconnection district, and extend under little table top from little table top.

Advantage of the present invention is:

1. for traditional meas structure, the InGaAs layer of reservation is equivalent to from the body passivating film, and the side of table top is effectively protected.

2. silicon nitride passivation can effectively play antireflection and the effect that reduces InP and InGaAs laminar surface attitude, can increase the quantum efficiency of detector and reduce dark current, and can play the passivation reinforcement effect.

3.P electrode adopts AuZnPtAu, AuZnPtAu can form good ohmic contact with P-InP, and inferior outer field Pt can stop the outdiffusion of Zn, the raising device reliability effectively.

Description of drawings

Fig. 1 is the structural representation of epitaxial wafer;

Fig. 2 is the cross-sectional view of indium gallium arsenic detector array;

Fig. 3 is the vertical view of Fig. 2;

Fig. 4-Fig. 8 is a process chart.

Embodiment

Below in conjunction with drawings and Examples the specific embodiment of the present invention is described in further detail:

See Fig. 1, the used epitaxial wafer of present embodiment for the MBE technology be at thickness on the semi-insulating InP substrate 1 of 350 μ m successively growth thickness be the n type InP layer 2 of 1 μ m, carrier concentration is greater than 2 * 10 ¹⁸Cm ^-3Thickness is the In of 2.5 μ m _0.53Ga _0.47As intrinsic absorbed layer 3; Thickness is the p type InP cap layer 4 of 0.5 μ m, and carrier concentration is greater than 2 * 10 ¹⁸Cm ^-3

Fig. 2 is the cross-sectional view of present embodiment, forms the little table top 4 of alignment p-InP by etching on epitaxial wafer.Be equipped with P electrode district 6 on the regional area of the little table top of p-InP, with the P electrode employing Au/Zn/Pt/Au of p-InP ohmic contact, Au, Zn, Pt, Au are grown in the P electrode district 6 successively; On the little table top of alignment limit, have one to be etched to the n-InP layer and to place Cr/Au common electrode area 7 on the n-InP layer, i.e. the N electrode district.Except that P,

N electrode district

6,7, be coated with silicon nitride passivation 5 on the whole epitaxial wafer, on the P electrode district, be equipped with the electrode interconnection layer 8 with reading circuit interconnection, this little table top in electrode interconnection layer cover part, and extend under little table top from little table top.What do not have the coated electrode interconnection layer on little table top is the light sensitive area 9 of detector.

Conventional method is adopted in the chip preparation of present embodiment, and its process is:

1. use chloroform, ether, acetone, ethanol ultrasonic cleaning epitaxial wafer successively, nitrogen dries up;

2. positive glue (thick glue) photoetching was dried 20 minutes for 65 ℃ after the photoetching;

3.Ar ⁺The p-InP layer of ion etching except that the little table top of p-InP, ion energy is 300eV, line is 80cm ^-3, utilize HCl and H then ₃PO ₄Mixed liquor corrodes remaining p-InP layer, guarantee that the corrosion of p-InP layer is clean, forms the little table top 4 of alignment at last, sees Fig. 4;

4. acetone removes photoresist, deionized water rinsing, and nitrogen dries up;

5. etching public electrode hole: positive glue (thick glue) photoetching, 65 ℃ of oven dry are 20 minutes after the photoetching; Ar ⁺Etching InGaAs absorbed layer uses tartaric acid solution and H then ₂O ₂Selective corrosion solution, 35 ℃ of following wet chemical etching technique InGaAs absorbed layers, deionized water rinsing, nitrogen dries up, and forms public electrode hole 10, sees Fig. 5;

6. acetone removes photoresist, deionized water rinsing, and nitrogen dries up;

7. sulfuration is at 60 ℃ of (NH ₄) ₂In the S solution, vulcanized 30 minutes, washed with de-ionized water, nitrogen dries up;

8. adopt the PECVD method,, comprise the side deposit silicon nitride passivation layer in public electrode hole, see Fig. 6 exposed whole epi-layer surface and side;

9. corrode the silicon nitride passivation of p, n electrode district: positive glue (thick glue) photoetching, dried 20 minutes for 65 ℃ after the photoetching; At first the plasma air purge is 8 minutes, adopts HF: NH then ₄F: H ₂O=3: 6: 9 mixed liquor, 50 ℃ corroded 8 seconds down, see Fig. 7;

10. at the electrode A u/Zn/Pt/Au of electrode district 6 growth p-InP ohmic contact, see Fig. 8;

11. acetone removes photoresist, deionized water rinsing, and nitrogen dries up, and carries out annealing in process; Cr/Au common electrode layer and Cr/Au electrode interconnection layer 8 12. ion beam sputtering is grown in public electrode hole 10 are at first used Ar before the growth ⁺Auxilliary source was cleaned 3 minutes;

13. floating glue: acetone floats glue, ethanol cleans, and nitrogen dries up, and the preparation of low table alignment chip is finished, and sees Fig. 2.

Claims

1. InGaAs low table alignment or area array infrared detector chip comprise: semi-insulating InP substrate, and growth has the p-InP/InGaAs/n-InP epitaxial wafer on the InP substrate, it is characterized in that:

On the p-InP/InGaAs/n-InP epitaxial wafer, alignment or the little table top of face battle array p-InP (4) have been formed by etching, on the regional area of the little table top of p-InP, be equipped with P electrode district (6), adopt Au/Zn/Pt/Au with the P electrode of p-InP ohmic contact, Au, Zn, Pt, Au are grown in the P electrode district (6) successively; On alignment or the little table top of face battle array limit, have one to be etched to the n-InP layer and to place common electrode area (7) on the n-InP layer, it is the N electrode district, except that P, N electrode district, on the whole epitaxial wafer, the side that comprises little table top all is coated with silicon nitride passivation (5), be equipped with the electrode interconnection district (8) that interconnects with reading circuit on the Au/Zn/Pt/Au/ electrode district, this little table top in cover part, electrode interconnection district extends under little table top from little table top.