CN100531091C - I2C bus realization method for point-to-point communication - Google Patents
I2C bus realization method for point-to-point communication Download PDFInfo
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- CN100531091C CN100531091C CNB2007101637303A CN200710163730A CN100531091C CN 100531091 C CN100531091 C CN 100531091C CN B2007101637303 A CNB2007101637303 A CN B2007101637303A CN 200710163730 A CN200710163730 A CN 200710163730A CN 100531091 C CN100531091 C CN 100531091C
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Abstract
The invention provides a bus implementation method for peer-to-peer communications, which is mainly used for the communications between a master device and a slave device. The invention comprises the following steps: step S102, the master device sends the start signal; step S104, the master device sends the bytes including the address of the slave device and the read/write bits indicating the direction of transfer of data; step S106, the master device sends the data bytes; step S108, the master device sends the authorization bit; step S110, the master device continues to carry out the sending in the order of 'first the data bytes then the authorization bit' till the stop bit is sent; step S112, the master device sends the stop bit; wherein, step S110 further comprises: step S110-2, the master device sends the read/write bit which is used for indicating the transfer direction before each data byte is sent. The technical scheme of the invention can simplify the operation of the master device, enhance the efficiency of data transmission and simultaneously assure the reliability of data transmission.
Description
Technical field
The present invention relates to the communications field, particularly, relate to the method for in hardware circuit design, setting up a kind of privately owned serial-port, be specially adapted in the point-to-point communication the less demanding occasion of real-time property.
Background technology
I2C (Inter IC Bus) is the two-wire system serial expansion bus that connects between a kind of IC of being used for device of Philips company release.Compare with parallel expansion bus that to have a circuit structure simple, programming is convenient and be easy to realize advantage such as modularization.The I2C bus is widely used in industrial electronic, consumer electronics and the communication apparatus at present.Can reach 100kbit/s under the message transmission rate mode standard on the I2C bus, 400kbit/s under the quick mode, fast mode is following even can reach 3.4Mbit/s.
With the transmission of traditional computer serial line interface with receive that each is different with a line (RxD and TxD), the hardware characteristics of I2C is for having only two bus lines,, a serial data line (SDA),, a serial time clock line (SCL), any equipment that is connected on the bus only comes transmission information by these two lines.Each device on the bus all has a unique Address Recognition, and can be as main device or from device according to the difference of function.The data that main device is used to start on the bus transmit and the transmitting system clock, and the device that be addressed this moment is from device.
SDA and SCL are bidirectional lines, all are connected to positive supply voltage by a current source or pull-up resistor, to guarantee that these two lines are high level the free time.The clock sync signal that transmits on the I2C bus is to be produced by the clock line logical that is articulated in each device on the SCL clock line, promptly when the clock signal saltus step of some devices is low level, to make scl line also become low level, up to the equal saltus step of all clock signals is high level, and the SCL signal is just by the low height that jumps to.SDA must keep stable in the high level period of clock, and just allows to change in the low-level period of clock.When SCL was high level, SDA was the beginning that low level is represented transfer of data by the high level saltus step; When SCL was high level, SDA was the end that high level is represented transfer of data by low transition.
The data transfer format of I2C bus is: the transmission enabling signal with main device begins, (high 7 is from address of devices and then to send first byte, minimum one is R/W (read/write) position that indicates data transmission direction, this position be 0 expression main device to sending data from device, be that 1 expression sends data from device to main device).The Gao Siwei of address is not complete 0 or complete 1, then can then send required data byte.The byte number of the each transmission of bus without limits, but an authorization bit (the 9th) must be inserted in the byte back of each transmission, also is response bits (ACK).In the clock cycle of replying, receiver (can be main device also can be from device) must drag down sda line, as replying of normal reception; When receiver can not normally receive data, then SDA must be drawn high, main device will produce a stop condition termination transmission or repeat the once new transmission of initial conditions initiation this moment.Concrete form is referring to accompanying drawing 1.
The I2C bus allows a plurality of main devices to be connected on the bus simultaneously, therefore also can cause the situation that two or more main devices want to take simultaneously bus sometimes, therefore, I2C has also introduced the mechanism that the bus contention that occurs on the SDA bus is arbitrated, and guaranteed the reliability of arbitration, can not cause that main frame sends losing of data.
However, the I2C bus has the defective of complicated operation.Therefore need a kind of new technical scheme to overcome above-mentioned defective.
Summary of the invention
For this reason, one of purpose of the present invention is to provide a kind of method of simplifying original I2C bus implementation.This method is mainly used in the point-to-point communication, and under the less demanding occasion of real-time property, use the physical electrical characteristic of I2C technology, and evade bus president, the synchronization mechanism of I2C technical sophistication, adopt a kind of self-defining frame format (as accompanying drawing 3) in one-period, to finish all read-write operations of slave simultaneously, simplified the read-write operation of original I2C bus schemes.
Simultaneously, another purpose of the present invention is in the function of the technical increase of original I2C bus schemes to the bus operation wrong identification, guarantees the reliability of operation.
The I2C bus implementation method of point-to-point communication provided by the invention is used for main device and from the communication between the device, comprises: step S102, and main device sends enabling signal; Step S104, main device send and comprise from the byte of address of devices and the read/write that indicates data transmission direction; Step S106, main device sends data byte; Step S108, main device sends authorization bit; Step S110, main device continue to send with the order of data byte, authorization bit, till sending position of rest; Step S112, main device sends position of rest; Wherein, in step S110, also comprise: step S110-2, before sending each data byte, all send read/write, be used to represent the direction of transfer of next data byte.
In the I2C of above-mentioned point-to-point communication bus implementation method, be set to fixed value from address of devices in comprising from the byte of address of devices of being sent.
In the I2C of above-mentioned point-to-point communication bus implementation method, fixed value is a byte.
In the I2C of above-mentioned point-to-point communication bus implementation method, fixed value is 0x7E.
In the I2C of above-mentioned point-to-point communication bus implementation method, authorization bit is two.
In the I2C of above-mentioned point-to-point communication bus implementation method, authorization bit is respectively 0 and at 1 o'clock, and representative normally receives.
Pass through technique scheme, realized following technique effect: in the I2C of this point-to-point communication bus implementation method, owing to have only a main device and one from device, so can omit complicated mechanism such as clock synchronization in the former I2C interface and data arbitration mechanism, implement more simple and easy to do with programmable logic device.Simultaneously under the constant situation of physical transmission rate, less and form is fixed when data volume, when mostly being byte or a few bytes, adopts this point-to-point I2C bus implementation method can simplify the operation of main device, improve the efficient of transfer of data, guaranteed the reliability of transmission data simultaneously.
Other features and advantages of the present invention will be set forth in the following description, and, partly from specification, become apparent, perhaps understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the specification of being write, claims and accompanying drawing.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 shows the data format of I2C bus definition in the prior art;
Fig. 2 shows according to bus implementation method flow chart of the present invention;
Fig. 3 shows data format according to an embodiment of the invention;
Fig. 4 shows according to an embodiment of the invention the data class plate of a SDH optical transmission device and uses the theory diagram that this bus implementation method is carried out the optical module transfer of data; And
Fig. 5 shows main device and the concrete data format from transmitting between the device in the data class plate of SDH optical transmission device according to an embodiment of the invention.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
At first with reference to Fig. 2, Fig. 2 shows according to bus implementation method flow chart of the present invention; May further comprise the steps:
Step S102, main device sends enabling signal; Step S104, main device send and to comprise from address of devices and the byte that indicates the read/write of data transmission direction; Step S106, main device sends data byte; Step S108, main device sends authorization bit; Step S110, main device continue to send with the order of data byte, authorization bit, till sending position of rest, wherein all send read/write before sending each data byte, are used to represent the direction of transfer of next data byte; And step S112, main device sends position of rest.Wherein, be set to fixed value in comprising from the byte of address of devices of being sent from address of devices.Wherein, fixed value is a byte.Preferably, fixed value is 0x7E.Wherein, authorization bit is two.Preferably, authorization bit is respectively 0 and at 1 o'clock, and representative normally receives.
Fig. 3 shows data format according to an embodiment of the invention.
In original I2C interface data frame format (as accompanying drawing 1), determined it in one-period, can only finish once the operation of reading (or writing).In the present invention, on the basis of legacy data frame format, according to preceding having increased R/W position (as shown in Figure 3), can guarantee in an operation cycle, to finish simultaneously main frame all read-write operations to slave at bits per inch.
As seen, the data frame format of the present invention after the improvement is defined as follows from accompanying drawing 3:
(1) S (): the beginning condition, with the I2C bus definition, when SCL was high level, SDA was the beginning that low level is represented transfer of data by the high level saltus step.
(2) 0x7E (1 byte): frame synchronous byte, also can represent from address of devices, together play the effect of deciding frame (owing to can define by own fully, so 7E is only for reference) with the S position from address of devices.
(3) R/W (1): read-write, R/W are represented the direction of next byte DATA, are to write (main device-from device) still to read (from device-main device), are to carry out read operation at 1 o'clock, are to carry out write operation at 0 o'clock.
(4) DATA (n) (byte): the data byte of concrete transmission.
(5) A (ACK) (two): response bits, with the I2C bus definition, main frame sent in continuous two cycles of clock pulse, and receiver drags down sda line and is released to height (promptly 0---〉1) representative again and normally receives, otherwise, can not continue to receive data for there not being normal response.
(6) P (): termination condition, together with the I2C bus definition, when SCL was high level, SDA was the end that high level is represented transfer of data by low transition.
Owing to have only in the system a fixing main device and one therefore the address byte in each read-write sequence can be fixed from device, can be decided to be 7E, can help frame alignment.Simultaneously, main device with may mostly be byte from the data of communicating by letter between device, therefore after the data of each byte, add a read-write indicating bit, be used for representing the direction of transfer of next data byte, when the direction of two data bytes is inconsistent, just do not need all to initiate an independent operation in this case at every turn, promptly reappear the operation of " initiation---〉address---〉read/write---〉data---〉reply ".If main device is visited from device in the mode of poll, read and write register at interval with regular time from device, then Shang Mian data format can be simplified the operation of main device.
Fig. 4 shows according to an embodiment of the invention the data class plate of a SDH optical transmission device and uses the theory diagram that this serial-port carries out the optical module transfer of data.
As seen from Figure 4, this database is made up of two veneers, and one is interface board, and one is disposable plates.Interface board provides 8 SFP optical module interfaces, finishes the access of 8 road 100BASE-FX business; Disposable plates is then carried out the processing of SDH side to the Ethernet service that inserts.Interface board and programmable logic device is all arranged above the disposable plates, both carry out the mutual of information by backboard line (adopting the designed I2C bus of the present invention).The programmable logic device the inside of interface board is provided with 4 registers:
● optical module sends enable register (TX_DISABLE)
● optical module is at bit register (M_ON)
● optical module sends inefficacy register (TX_FAULT)
● optical module dropout register (LOS)
Among the figure:
M_ONn (n=1～8) optical module is on the throne
TX_FAULTn (n=1～8) optical module sends and lost efficacy
LOSn (n=1～8) dropout
TX_DISABLEn (n=1～8) optical module sends and enables
The programmable logic device of interface board gathers that the optical module of each SFP optical module is on the throne, optical module send lost efficacy and three signals such as optical module dropout after put in the middle of the register of corresponding three bytes.The programmable logic device of disposable plates then sends the optical module transmission enable signal of a byte to the programmable logic device of interface board, put to optical module transmission enable register, is used for enabling respectively 8 SFP optical modules.
The programmable logic device of disposable plates is as main device, the programmable logic device conduct of interface board is from device, the operation of finishing be main device by the modified model I2C bus implementation that is suitable for point-to-point communication setting up this paper and set forth to from the optical module of device at bit register, send the inefficacy register and the dropout register reads, and write optical module enable signal register, the shutoff of laser in the control SFP optical module.The CPU of disposable plates links to each other with the programmable logic device of this plate by cpu i/f, (the optical module enable signal is a write operation to the read-write of initiating three registers from device with Fixed Time Interval to allow this main device by control bus, it is read operation that optical module signal on the throne and optical module dropout signal, optical module send disablement signal) operation, and the register data of three bytes will reading from interface board by data, address bus simultaneously is uploaded to CPU and carries out next step processing.
Fig. 5 shows main device and the concrete data format from transmitting between the device in the data class plate of SDH optical transmission device according to an embodiment of the invention.
As can be seen from Fig. 5, at first start bit S in this form, being fixed address 7E afterwards, is read/write afterwards, is data byte afterwards, be authorization bit then, after the authorization bit is read/write, continues as data bit after the read/write, is position of rest at last, as seen read/write was all arranged before each data byte, be used to indicate the direction of transfer of next data byte.
In sum, pass through technique scheme, the present invention has realized following technique effect: in the I2C of point-to-point communication bus implementation method, owing to have only a main device and one from device, so can omit complicated mechanism such as clock synchronization in the former I2C interface and data arbitration mechanism, implement more simple and easy to do with programmable logic device.Simultaneously under the constant situation of physical transmission rate, less and form is fixed when data volume, when mostly being byte or a few bytes, adopts this point-to-point I2C bus implementation method can simplify the operation of main device, improve the efficient of transfer of data, guaranteed the reliability of transmission data simultaneously.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the I2C bus implementation method of a point-to-point communication is used for main device and from the communication between the device, may further comprise the steps: step S102, and described main device sends enabling signal; Step S104, described main device send and comprise from the byte of address of devices and the read/write that indicates data transmission direction; Step S106, described main device sends data byte; Step S108, described main device sends authorization bit; Step S110, described main device continue to send with the order of data byte, authorization bit, till sending position of rest; Step S112, described main device sends position of rest; It is characterized in that, in described step S110, also comprise:
Step S110-2 sent read/write before sending each data byte, be used to represent the direction of transfer of next data byte.
2. I2C bus implementation method according to claim 1 is characterized in that, describedly describedly from the byte of address of devices is set to fixed value from address of devices in comprising of being sent.
3. I2C bus implementation method according to claim 2 is characterized in that, described fixed value is a byte.
4. I2C bus implementation method according to claim 3 is characterized in that described fixed value is 0x7E.
5. according to each described I2C bus implementation method in the claim 1 to 4, it is characterized in that described authorization bit is two.
6. I2C bus implementation method according to claim 5 is characterized in that, described authorization bit is respectively 0 and at 1 o'clock, and representative normally receives.
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| CNB2007101637303A CN100531091C (en) | 2007-10-23 | 2007-10-23 | I2C bus realization method for point-to-point communication |
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| CNB2007101637303A CN100531091C (en) | 2007-10-23 | 2007-10-23 | I2C bus realization method for point-to-point communication |
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| CN100531091C true CN100531091C (en) | 2009-08-19 |
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| CN102375749B (en) * | 2010-08-24 | 2014-06-18 | 上海华虹集成电路有限责任公司 | Method for quickly downloading and updating firmware by using I2C (Inter-Integrated Circuit) bus |
| CN102801744B (en) * | 2012-09-05 | 2015-11-25 | 上海斐讯数据通信技术有限公司 | A kind of communication means and system |
| CN103856199B (en) * | 2012-11-28 | 2017-02-08 | 苏州新宏博智能科技股份有限公司 | Pulling up device for data bus |
| CN103763220A (en) * | 2014-01-28 | 2014-04-30 | 上海斐讯数据通信技术有限公司 | Read-write structure of single-plate optical module and read-write method |
| CN104866446A (en) * | 2015-06-07 | 2015-08-26 | 英业达科技有限公司 | Transfer interpreter and data reading and writing method of transfer interpreter |
| US9727506B2 (en) * | 2015-10-01 | 2017-08-08 | Sony Corporation | Communication system, communication system control method, and program |
| CN105373511B (en) * | 2015-10-30 | 2018-06-29 | 上海斐讯数据通信技术有限公司 | A kind of device and method that can be communicated simultaneously with multiple optical modules |
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Effective date of registration: 20151222 Address after: Yuhuatai District of Nanjing City, Jiangsu province 210012 Bauhinia Road No. 68 Patentee after: Nanjing Zhongxing New Software Co., Ltd. Address before: 518057 Nanshan District science and Technology Industrial Park, Guangdong high tech Industrial Park, ZTE building Patentee before: ZTE Corporation |
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Granted publication date: 20090819 Termination date: 20161023 |