CN100530111C - Multi-thread access indirect register scheduling method - Google Patents
Multi-thread access indirect register scheduling method Download PDFInfo
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- CN100530111C CN100530111C CNB200710149864XA CN200710149864A CN100530111C CN 100530111 C CN100530111 C CN 100530111C CN B200710149864X A CNB200710149864X A CN B200710149864XA CN 200710149864 A CN200710149864 A CN 200710149864A CN 100530111 C CN100530111 C CN 100530111C
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Abstract
The invention discloses a scheduling method, by the scheduling method, an indirect register can be visited in multi-thread way. The method completes the task scheduling based on the contention manner of the priority-level, and controls the visit to the indirect register by operating a data register and a control register, wherein, when the current priority-level task visiting the indirect register is contented with a higher priority-level, firstly the current priority-level task can be paused, and the value of the data register under the operation of the current priority-level task can be saved, and then, the data register and the control register can be scheduled to deal with the higher priority-level task; when the higher priority-level task is completed, the value of the data register saved before can be rewrote into the data register to restore the environment of the data register and continue the operation of the task paused before; the invention can avoid situation that the operation of the hardware in the indirect register with the function of multi-thread visit is disaccorded with the operation of the software therein.
Description
Technical field
The present invention relates to the light transmission field, proposed a kind of dispatching method of multi-thread access indirect register.
Background technology
Light transmission is occupied important status in modern communications, along with development of Communication Technique, the optical communication equipment function from strength to strength, relative commercial chip function also becomes increasingly complex, but because hardware resource is limited, a lot of commercial chips have adopted a large amount of indirect register read-write modes to economize on resources, and this has but buried bomb to embedded software system.The read-write mode of indirect register once is described here, chip with PMC is an example, the read-write operation of indirect register need be controlled two class registers, one class is a control register, one class is a data register, in the control register the inside three kinds of control operations is arranged, and first kind is the control operation of read/write mode, second kind is the control operation of indirect address content, and the third is the current judgement control operation of whether finishing from indirect address content the inside read/write content.
SDH equipment substantially all is to adopt embedded system to come Application and Development software at present, and embedded OS provides basic task scheduling mode for us. promptly adopt based on the preemptive type mode of priority and come scheduler task, will cause a problem.With two tasks is example, low priority task is just at the service data register time, high-priority task has been seized CPU, again control register and data register have been operated, and then cpu resource given back low priority task, continue the service data register, from the software angle without any problem, but just had problems from hardware point of view, because change has taken place in the content of control register, the data register content of this moment be not before the needed data register content of low priority task.
The way that prior art addresses this problem is: use semaphore to preserve the order of high low priority task read-write, just can address this problem, but the semaphore of introducing can use for high low priority task simultaneously, is absolutely unsafe.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of dispatching method of multi-thread access indirect register, utilizes the principle of register itself, is handled under the prerequisite of not using semaphore, can guarantee that multi-thread access indirect register can access errors.
In order to address the above problem, the invention provides a kind of dispatching method of multi-thread access indirect register, preempt-mode based on priority comes scheduler task, by the visit of the operation of data register and control register being controlled to described indirect register, wherein, in the current priority task of visit indirect register during by the higher task preemption of priority, at first suspend the current priority task, and the value of the data register under the current priority task operating preserved, dispatch described data register and control register the higher task of described priority is operated; After the higher task of described priority is finished, the value of the data register preserved is before write data register again, the restore data registers contexts continues to finish the operation to the task of interrupting before then;
Further, method of the present invention wherein, is operated described control register, select operating mode and indirect address;
Further, method of the present invention, wherein, described operator scheme comprises: read operation and write operation;
Further, method of the present invention wherein, is provided with the time-delay marker bit to described indirect register, and reading this time-delay marker bit is fictitious time, illustrates that described indirect register is occupied by a task, and hardware operation is underway; Reading this time-delay marker bit is true time, illustrates that described indirect register hardware operation interrupts, and current task is suspended or finished;
Further, method of the present invention wherein, by the operation of data register and control register being controlled the visit of current priority task to described indirect register, may further comprise the steps:
(1a) operation control register, select operating mode is read operation and correct indirect address;
(2a) read indirect register time-delay marker bit, if be vacation, then jump procedure (3a); If be true, jump procedure (4a) then;
If the number of times that (3a) reads is less than threshold values, jump procedure (2a) then; If greater than threshold values, jump procedure (5a) then;
(4a) service data register, readout;
(5a) read operation of current priority task finishes;
Further, method of the present invention, wherein, the operation of interrupt task before recovering after the current priority task of described visit indirect register is finished by the higher task preemption of priority and the higher task of described priority may further comprise the steps:
(1b) read indirect register time-delay marker bit, if be vacation, then jump procedure (2b); If be true, jump procedure (3b) then;
If the number of times that (2b) reads is less than threshold values, jump procedure (1b) then; If greater than threshold values, jump procedure (9b) then;
(3b) value of data register is preserved;
(4b) operation control register, select operating mode is read operation and correct indirect address;
(5b) read indirect register time-delay marker bit, if be vacation, then jump procedure (6b); If be true, jump procedure (7b) then;
If the number of times that (6b) reads is less than threshold values, jump procedure (5b) then; If greater than threshold values, jump procedure (9b) then;
(7b) service data register, readout;
(8b) restore data registers contexts writes data register again with the value of the data register preserved before;
(9b) read operation of the task that priority is higher finishes;
Further, method of the present invention, wherein, described by the operation of data register and control register being controlled the visit of current priority task to described indirect register, further comprising the steps of:
(1c) service data register, the value of writing;
(2c) operation control register, select operating mode is a write operation, and correct indirect address;
(3c) read indirect register time-delay marker bit, if be vacation, then jump procedure (4c); If be true, jump procedure (5c) then;
If the number of times that (4c) reads is less than threshold values, jump procedure (3c) then; If greater than threshold values, jump procedure (5c) then;
(5c) write operation of current priority task finishes;
Further, method of the present invention, wherein, the operation of interrupt task before recovering after the current priority task of described visit indirect register is finished by the higher task preemption of priority and the higher task of described priority, further comprising the steps of:
(1d) read indirect register time-delay marker bit, if be vacation, then jump procedure (2d); If be true, jump procedure (3d) then;
If the number of times that (2d) reads is less than threshold values, jump procedure (1d) then; If greater than threshold values, jump procedure (9d) then;
(3d) value of data register is preserved;
(4d) service data register, the value of writing;
(5d) operation control register, select operating mode is write operation and correct indirect address;
(6d) read indirect register time-delay marker bit, if be vacation, then jump procedure (7d); If be true, jump procedure (8d) then;
If the number of times that (7d) reads is less than threshold values, jump procedure (6d) then; If greater than threshold values; Jump procedure (9d) then;
(8d) restore data registers contexts writes data register again with the value of the data register preserved before;
(9d) write operation of the task that priority is higher finishes.
Adopt the method for the invention, compared with prior art, adopt the method for the invention, hardware operation and the inconsistent situation of software operation that can avoid multi-thread access performance indirect register to occur.
Description of drawings
Fig. 1 is the read operation process flow diagram of low priority task access performance indirect register in the embodiment of the invention;
Fig. 2 is the write operation process flow diagram of low priority task access performance indirect register in the embodiment of the invention;
Fig. 3 is the read operation process flow diagram of high-priority task access performance indirect register in the embodiment of the invention;
Fig. 4 is the write operation process flow diagram of high-priority task access performance indirect register in the embodiment of the invention.
Embodiment
The present invention is in order to solve the drawback that conventional solution exists, further set forth the dispatching method of a kind of multi-thread access indirect register of the present invention by following specific embodiment, below embodiment is described in detail, but not as a limitation of the invention.
As shown in Figure 1, be the read operation process flow diagram of low priority task access performance indirect register in the embodiment of the invention.In the multi-thread access indirect register, the read operation of low priority task may further comprise the steps:
Step 100, the read operation of low priority task begins;
Step 101, the operation control register, select operating mode is read operation and correct indirect address;
Step 102 reads indirect register time-delay marker bit, if be false, then jump procedure 103; If be true, then jump procedure 104;
Step 103, if the number of times that reads less than threshold values P, then jump procedure 102; If greater than threshold values P, then jump procedure 105;
Step 104, service data register, readout;
Step 105, the read operation of low priority task finishes.
As shown in Figure 2, be the write operation process flow diagram of low priority task access performance indirect register in the embodiment of the invention.In the multi-thread access indirect register, the write operation of low priority task may further comprise the steps:
Step 203 reads indirect register time-delay marker bit, if be false, then jump procedure 204; If be true, then jump procedure 205;
As shown in Figure 3, be the read operation process flow diagram of high-priority task access performance indirect register in the embodiment of the invention.In the multi-thread access indirect register, high-priority task is seized low priority task, carries out read operation, may further comprise the steps:
Step 300, the read operation of high-priority task begins;
Step 301 reads indirect register time-delay marker bit, if be false, then jump procedure 302; If be true, then jump procedure 303;
Step 302, if the number of times that reads less than threshold values P, then jump procedure 301; If greater than threshold values P, then jump procedure 309;
Step 303 is preserved the data register value to an intermediate quantity;
Step 304, the operation control register, select operating mode is read operation and correct indirect address;
Step 305 reads indirect register time-delay marker bit, if be false, then jump procedure 306; If be true, then jump procedure 307;
Step 306, if the number of times that reads less than threshold values P, then jump procedure 305; If greater than threshold values P, then jump procedure 309;
Step 307, service data register, readout;
Step 308, the restore data registers contexts writes data register with the value of this intermediate quantity;
Step 309, the read operation of high-priority task finishes.
As shown in Figure 4, be the write operation process flow diagram of high-priority task access performance indirect register in the embodiment of the invention.In the multi-thread access indirect register, high-priority task is seized low priority task, carries out write operation, may further comprise the steps:
Step 400, the write operation of high-priority task begins;
Step 401 reads indirect register time-delay marker bit, if be false, then jump procedure 402; If be true, then jump procedure 403;
Step 402, if the number of times that reads less than threshold values P, then jump procedure 401; If greater than threshold values P, then jump procedure 409;
Step 403 is preserved the control data register value to an intermediate quantity;
Step 404, service data register, the value of writing;
Step 405, the operation control register, select operating mode is write operation and correct indirect address;
Step 406 reads indirect register time-delay marker bit, if be false, then jump procedure 407; If be true, then jump procedure 408;
Step 407, if the number of times that reads less than threshold values P, then jump procedure 406; If greater than threshold values P; Then jump procedure 409;
Step 408, the restore data registers contexts writes data register with the value of this intermediate quantity;
Step 409, the write operation of high-priority task finishes.
Suppose A performance and B performance respectively in different indirect registers, but shared one group of control register and data register.And the A performance will priority tasks a in read, the B performance will read in high-priority task b, and reads in a task in the A performance, in the time of the intact control register of firm operation, is preferentially read the B performance by b task preemption resource.
Operate as follows:
The first step: in a task, the operation control register.
Second step: this moment, task a was seized by task b.
The 3rd step: task b read latch marker bit is false (hardware operation that reads the A performance of a task is also continuing).
The 4th step: task b read latch marker bit once more is true.
The 5th step: task b preserves the value of data register to m_dwRegValue.
The 6th step: task b operates control register, prepares to read the B performance.
The 7th step: task b read latch is labeled as very.
The 8th step: task b service data register, read the B performance.
The 9th step: the value of task b restore data register is m_dwRegValue.
The tenth step: task b inquiry B performance finishes, and returns CPU and gives task a.
The 11 step: task a read latch marker bit is true.
The 12 step: task a service data register, read the A performance.
The 13 step: task a inquiry A performance finishes.
Suppose that the A data will be written in the different indirect registers respectively with the B data, but ablation process is wanted shared one group of control register and data register.The A data will priority tasks a in write, the B data will write in high-priority task b, and write in a task in the A data, in the time of the intact control register of firm operation, are preferentially write the B data by b task preemption resource.
Operate as follows:
The first step: in a task, the operation control register.
Second step: this moment, task a was seized by task b.
The 3rd step: task b read latch marker bit is false (hardware operation that writes the A data of a task is also continuing).
The 4th step: task b read latch marker bit once more is true.
The 5th step: task b preserves the value of data register to m_dwRegValue.
The 6th step: task b operates control register, prepares to write the B data.
The 7th step: task b read latch is labeled as very.
The 8th step: task b service data register writes the B data.
The 9th step: the value of task b restore data register is m_dwRegValue.
The tenth step: task b writes the B ED, returns CPU and gives task a.
The 11 step: task a read latch marker bit is true.
The 12 step: task a service data register writes the A data.
The 13 step: task a writes the A ED.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (8)
1, a kind of dispatching method of multi-thread access indirect register comes scheduler task based on the preempt-mode of priority, and the visit by the operation of data register and control register being controlled to described indirect register is characterized in that,
In the current priority task of visit indirect register during by the higher task preemption of priority, at first suspend the current priority task, and the value of the data register under the current priority task operating preserved, dispatch described data register and control register the higher task of described priority is operated;
After the higher task of described priority is finished, the value of the data register preserved is before write data register again, the restore data registers contexts continues to finish the operation to the task of interrupting before then.
2, the method for claim 1 is characterized in that, operates described control register, select operating mode and indirect address.
3, method as claimed in claim 2 is characterized in that, described operator scheme comprises: read operation and write operation.
4, method as claimed in claim 3 is characterized in that, described indirect register is provided with the time-delay marker bit, and reading this time-delay marker bit is fictitious time, illustrates that described indirect register is occupied by a task, and hardware operation is underway; Reading this time-delay marker bit is true time, illustrates that described indirect register hardware operation interrupts, and current task is suspended or finished.
5, method as claimed in claim 4 is characterized in that, by the operation of data register and control register being controlled the visit of current priority task to described indirect register, may further comprise the steps:
(1a) operation control register, select operating mode is read operation and correct indirect address;
(2a) read indirect register time-delay marker bit, if be vacation, then jump procedure (3a); If be true, jump procedure (4a) then;
If the number of times that (3a) reads is less than threshold values, jump procedure (2a) then; If greater than threshold values, jump procedure (5a) then;
(4a) service data register, readout;
(5a) read operation of current priority task finishes.
6, method as claimed in claim 4, it is characterized in that, the operation of the task of interrupting before recovering after the current priority task of described visit indirect register is finished by the higher task preemption of priority and the higher task of described priority may further comprise the steps:
(1b) read indirect register time-delay marker bit, if be vacation, then jump procedure (2b); If be true, jump procedure (3b) then;
If the number of times that (2b) reads is less than threshold values, jump procedure (1b) then; If greater than threshold values, jump procedure (9b) then;
(3b) value of data register is preserved;
(4b) operation control register, select operating mode is read operation and correct indirect address;
(5b) read indirect register time-delay marker bit, if be vacation, then jump procedure (6b); If be true, jump procedure (7b) then;
If the number of times that (6b) reads is less than threshold values, jump procedure (5b) then; If greater than threshold values, jump procedure (9b) then;
(7b) service data register, readout;
(8b) restore data registers contexts writes data register again with the value of the data register preserved before;
(9b) read operation of the task that priority is higher finishes.
7, method as claimed in claim 4 is characterized in that, and is by the operation of data register and control register being controlled the visit of current priority task to described indirect register, further comprising the steps of:
(1c) service data register, the value of writing;
(2c) operation control register, select operating mode is a write operation, and correct indirect address;
(3c) read indirect register time-delay marker bit, if be vacation, then jump procedure (4c); If be true, jump procedure (5c) then;
If the number of times that (4c) reads is less than threshold values, jump procedure (3c) then; If greater than threshold values, jump procedure (5c) then;
(5c) write operation of current priority task finishes.
8, method as claimed in claim 4, it is characterized in that, the operation of the task of interrupting before recovering after the current priority task of described visit indirect register is finished by the higher task preemption of priority and the higher task of described priority, further comprising the steps of:
(1d) read indirect register time-delay marker bit, if be vacation, then jump procedure (2d); If be true, jump procedure (3d) then;
If the number of times that (2d) reads is less than threshold values, jump procedure (1d) then; If greater than threshold values, jump procedure (9d) then;
(3d) value of data register is preserved;
(4d) service data register, the value of writing;
(5d) operation control register, select operating mode is write operation and correct indirect address;
(6d) read indirect register time-delay marker bit, if be vacation, then jump procedure (7d); If be true, jump procedure (8d) then;
If the number of times that (7d) reads is less than threshold values, jump procedure (6d) then; If greater than threshold values; Jump procedure (9d) then;
(8d) restore data registers contexts writes data register again with the value of the data register preserved before;
(9d) write operation of the task that priority is higher finishes.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2009294712A (en) * | 2008-06-02 | 2009-12-17 | Panasonic Corp | Priority controller and priority control method |
| CN101321030B (en) * | 2008-07-09 | 2012-04-04 | 中兴通讯股份有限公司 | Write-enabling control method and device |
| CN101625887B (en) * | 2009-08-14 | 2011-11-02 | 西北工业大学 | Memory access and request scheduling device and method for memory access and request scheduling by using device |
| US8453150B2 (en) * | 2010-06-08 | 2013-05-28 | Advanced Micro Devices, Inc. | Multithread application-aware memory scheduling scheme for multi-core processors |
| CN102207890A (en) * | 2011-05-27 | 2011-10-05 | 苏州阔地网络科技有限公司 | Task information processing method and scheduling control processing device |
| CN103699437B (en) * | 2013-12-20 | 2017-06-06 | 华为技术有限公司 | A kind of resource regulating method and equipment |
| CN104636205B (en) * | 2014-12-26 | 2019-02-05 | 北京奇艺世纪科技有限公司 | A kind of method and apparatus that task is seized |
| CN105138308B (en) * | 2015-08-28 | 2018-02-27 | 青岛海信宽带多媒体技术有限公司 | A kind of method and device for updating register |
| CN106775988A (en) * | 2016-12-30 | 2017-05-31 | 广东欧珀移动通信有限公司 | A kind of data processing method and equipment |
| CN112068945A (en) * | 2020-09-16 | 2020-12-11 | 厦门势拓御能科技有限公司 | Priority reversal method in optimized embedded system |
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