CN101625887B - Memory access and request scheduling device and method for memory access and request scheduling by using device - Google Patents
Memory access and request scheduling device and method for memory access and request scheduling by using device Download PDFInfo
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- CN101625887B CN101625887B CN2009100235858A CN200910023585A CN101625887B CN 101625887 B CN101625887 B CN 101625887B CN 2009100235858 A CN2009100235858 A CN 2009100235858A CN 200910023585 A CN200910023585 A CN 200910023585A CN 101625887 B CN101625887 B CN 101625887B
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Abstract
The invention discloses a memory access and request scheduling device and a method for memory access and request scheduling by using the device; the device comprises memory access request register stacks of a plurality of Banks, a plurality of Bank schedulers and a DRAM scheduler and is characterized in that the device also comprises a plurality of window constrain circuits which comprise a memory access request counter and a window length register. As the window constrain circuits are built in a memory access request scheduling circuit, the window constrain circuits guarantee that the Bank schedulers only schedule limited quantities of memory access requests at a time, can prevent memory access requests of individual addresses with poor locality from being postponed and scheduled indefinitely by the Bank schedulers, eliminates threading starvation caused by memory access request out-of-order scheduling, and increases the lowest processing capability of a multi-core processor.
Description
Technical field
The present invention relates to a kind of dispatching device, particularly memory access request scheduling device.Also relate to the method for carrying out the memory access request scheduling with this memory access request scheduling device.
Background technology
Document 2 " patent No. is the United States Patent (USP) of US20050246481 " discloses the Memory Controller that a kind of unrest is the memory access request scheduling.Memory access information before this device utilizes is dispatched the memory access request, has certain conjecture, guesses that successful basis is that the behavior of program is more fixing, and the memory access locality is better.In polycaryon processor, the program behavior that a plurality of processor core parallel computations are formed is also unstable, and can produce the relatively poor memory access request of locality.Therefore, this device and be not suitable for polycaryon processor and use.
Document 3 " patent No. is the United States Patent (USP) of US20030033493 " discloses a kind of Memory Controller of out of order memory access request scheduling.This device adopts the loss of memory control state machine instruction to carry out, command scheduler is used for memory command, out of order scheduling such as line activating instruction, precharge instruction, simultaneously, this command scheduler can also be carried out out of order scheduling to read-write requests, adopts the disorderly system scheduling of memory access request can reduce the memory access delay, but can cause the relatively poor request of certain locality to be postponed execution indefinite duration, cause thread hungry to death, reduced the lowest performance performance of processor, real-time is calculated in influence.Therefore, this processor can't solve the real-time demand of polycaryon processor in flowmeter is calculated in real time.
With reference to Fig. 5, the composition of memory access Request Processing device comprises a plurality of memory access request register heaps, Bank scheduler and the DRAM scheduler of branch Bank in the known shared storage polycaryon processor.Memory access request register heap is used to preserve the memory access request that processor thread sends, the Bank scheduler is used for choosing certain request from memory access request register heap and sends to the DRAM scheduler, the DRAM scheduler receives the memory access request that the Bank scheduler sends, and selects a memory access request to send to the DRAM scheduler.Wherein, the identical Bank that the Bank scheduler is concentrated address realm, the memory access request priority scheduling of going together mutually, the identical Bank that the DRAM scheduler also sends the Bank scheduler, colleague's memory access request priority scheduling mutually.There is following problem in this device: if certain thread continues to send memory access request in the range set of a large amount of addresses in the polycaryon processor, all memory access requests of this thread will preferentially be carried out, and the memory access request that the address realm that other thread sends disperses will be postponed by indefinite duration, cause thread hungry to death, reduced the lowest performance performance of processor and influenced the real-time that program is carried out.
Summary of the invention
Influence the problem of thread process real-time at out of order memory access dispatching device in traditional polycaryon processor, the invention provides a kind of memory access request scheduling device, in memory access request scheduling circuit, made up window constraint circuit, window constraint circuit assurance Bank scheduler once only can be dispatched the memory access request of limited quantity, can prevent that the relatively poor memory access request of individual address locality from being delayed scheduling indefinite duration by the Bank scheduler, it is hungry to death to eliminate the thread that the out of order scheduling of memory access request causes, and improves the minimum processing power of polycaryon processor.
The present invention also provides and utilizes this memory access request scheduling device to carry out the method for memory access request scheduling.At first window constraint circuit is carried out initialization, visible memory access request quantity in the once scheduling is set in the length of window register; After the memory access request comes,, this memory access request is saved in the request register heap if the Bank memory access request register of memory access request correspondence heap is discontented; The window constraints module is reading numerical values from the length of window register, and as seen the read request of respective value is set in the Bank memory access request register, and as seen all write requests are set to.In Bank memory access request register heap, the Bank scheduler sends to the DRAM scheduler with visible memory access request, for the DRAM scheduler schedules.
The technical solution adopted for the present invention to solve the technical problems: a kind of memory access request scheduling device, memory access request register heap, several Bank schedulers and a DRAM scheduler of comprising several Bank, be characterized in also comprising several window constraint circuit, comprise a memory access request counter and length of window register in the window constraint circuit; As seen all write requests of window constraint circuit are set to; Memory access request register heap receives the memory access request of from processor, and the memory access request is saved in the memory access request register heap, and the witness marking of memory access request is set to invisible; Window constraint circuit is operated the witness marking of the memory access request of arrival in the memory access request register heap, is that the Bank scheduler is visible or invisible with the memory access request marks; The memory access request counter is counted the memory access request of as seen reading that enters memory access request register heap, when memory access request counter numerical value during less than the length of window register value, as seen invisible read request in the memory access request register is set to, memory access request count value accumulative total, when memory access request counter numerical value equals the memory access request of as seen reading in length of window register and the memory access request register heap and all is performed, the memory access request counter makes zero, as seen window constraint circuit memory access request is set to the Bank scheduler, the Bank scheduler is only dispatched visible memory access request, and the DRAM scheduler sends memory instructions according to the result of Bank scheduler to the DRAM scheduler.
A kind ofly utilize above-mentioned memory access request scheduling device to carry out the method for memory access request scheduling, be characterized in may further comprise the steps:
(a) initialization window constraint circuit, it is zero that the memory access request counter is set, the length of window register is a preset value;
(b) receive the memory access request of from processor, when the memory access request register heap of the Bank of memory access request correspondence is discontented, this memory access request is saved in the memory access request register heap of corresponding Bank;
(c) window constraint circuit is provided with the memory access request in the memory access request register heap, when the memory access request is write request, then as seen it be set to, when the memory access request is read request, and memory access request counter value is less than the length of window register value, then as seen it be set to, otherwise be set to invisible;
(d) the Bank scheduler is dispatched the visible memory access request in the memory access request register heap, will preferentially send to the DRAM scheduler with Bank colleague's request;
(e) the DRAM scheduler sends memory instructions according to the memory access request of Bank scheduler to the DRAM scheduler;
(f) after the memory access request was finished, it is invalid that the preservation item of this memory access request in memory access request register heap is set to.
The invention has the beneficial effects as follows: owing in memory access request scheduling circuit, made up window constraint circuit, window constraint circuit assurance Bank scheduler once only can be dispatched the memory access request of limited quantity, can prevent that the relatively poor memory access request of individual address locality from being delayed scheduling indefinite duration by the Bank scheduler, it is hungry to death to have eliminated the thread that memory access request out of order scheduling causes, and has improved the minimum processing power of polycaryon processor.
Below in conjunction with drawings and Examples the present invention is elaborated.
Description of drawings
Fig. 1 is the structured flowchart of memory access request scheduling device of the present invention.
Fig. 2 is the detail drawing of memory access request register heap among Fig. 1.
Fig. 3 is the further explanatory drawings of window constraint circuit among Fig. 1.
Fig. 4 is the detail drawing of Bank scheduler among Fig. 1.
Fig. 5 is the structured flowchart of known memory access request scheduling device.
Embodiment
With reference to Fig. 1～4, the present invention is at the textural out of order dispatching device of memory access request that adopts the window constraint.Whole device is made up of the memory access request register heap of minute Bank, the window constraint circuit that divides Bank, Bank scheduler and DRAM scheduler four major parts.Memory access request register heap is used to preserve the memory access request that processor sends, and is made up of a plurality of memory access request registers, and Fig. 2 has provided the memory access request register heap of being made up of four memory access request registers.Each memory access request register is formed by nine, row address item and column address item are used to preserve the address information of memory access request, data item is used to preserve the data that write of write request, the read/write item is used to preserve the request type of memory access, whether the information that significance bit is used to indicate this register record is effective, time mark is preserved order time of arrival of request, to the Bank scheduler as seen whether the memory access request that witness marking shows this register holds, by window constraint circuit operation, current activation row shows whether the row of this memory access request is activated, and mode bit is followed the tracks of the implementation status of memory access request.To the Bank scheduler as seen whether the memory access request that window constraint circuit is used for controlling memory access request register heap mainly be made up of memory access request counter and length of window register.The Bank scheduler is dispatched visible memory access request in the memory access request register heap.The DRAM scheduler carries out centralized dispatching to the memory access request that the Bank scheduler sends.
The information flow direction of entire circuit is: processor sends the memory access request, and memory access request scheduling device receives this memory access request and according to address information this memory access request is saved in the corresponding memory access request register heap.Window constraint circuit is operated the witness marking of the memory access request of arrival in the memory access request register heap, is that the Bank scheduler is visible or invisible with the memory access request marks.The Bank scheduler is chosen arrival memory access request the earliest from memory access request register heap, the row of this memory access request is kept at and activates in the row register as activating row, and will the information of going equal to activate the memory access request centralized dispatching of capable register.The Bank scheduler sends the memory access request to the DRAM scheduler, and the DRAM scheduler responds simultaneously to a plurality of memory access requests, sends memory command to the DRAM scheduler.After the memory access request was finished, it is invalid that this its significance bit of Bank scheduler is set to.
It is specific as follows that memory access request scheduling device carries out the method for memory access request scheduling:
(1) memory access request scheduling device initialization.
(2) the memory access request of reception from processor is saved in the memory access request in the memory access request register heap.The witness marking of memory access request is set to invisible.
(3), then block processor and send the memory access request if the memory access request register piles with.
Whether (4) have the witness marking of reading the memory access request to be set in the window constraint channel check memory access request register heap invisible, if any, if the numerical value of memory access request counter is less than the length of window register, then as seen this read request is set to, and as seen all write requests of window constraint circuit are set to.
(5) the Bank scheduler is dispatched the visible memory access request in the memory access request register heap, the priority orders that dispatching office adopts is: the visible read request that row information equals to activate capable register is the highest, secondly row information equal to activate capable visible write request, the priority that row information is not equal to the visible lines request that activates the row register a little less than, the priority that row information is not equal to the visible write request that activates the row register is minimum.
(6) the Bank scheduler changes the mode bit of memory access request into and carrying out.
(7) the DRAM scheduler responds the memory access request that a plurality of Bank schedulers send, and sends memory command to the DRAM scheduler.
(8) the memory access request complete after, the Bank scheduler changes the mode bit of memory access request into executed, it is invalid that significance bit is changed into.
Above-mentioned (2), (3) go on foot as memory access request receiving unit, and (4) step, remainder was as memory access request scheduling part as memory access request windowing part, and the operation of these three parts is parallel to be carried out, and the operation of various piece circulation is carried out.
From carrying out on the flow process as can be seen, this device has following characteristics: at first, observability to the Bank scheduler of memory access request before carrying out the memory access request scheduling is provided with, in the memory access request sequence that a processor sends, the Bank scheduler only can be dispatched the visible memory access request of a part wherein, have only the visible memory access request of this part of working as all to be sent to after the DRAM scheduler, as seen the window constraint circuit just memory access request of other parts is set to, and the Bank scheduler also could be dispatched the memory access request of other parts.The memory access request scheduling strategy of this windowing constraint guarantees that the memory access request is not postponed scheduling by the Bank scheduler indefinite duration, and it is hungry to death to have eliminated the thread that is caused by the memory access request scheduling, has improved the lowest performance performance of polycaryon processor, has guaranteed the real-time demand of calculating.Secondly, the out of order scheduling of parallelization has been taked in the memory access scheduling, reduces and has covered the precharge line activating time, has improved the memory access bandwidth.
Claims (2)
1. memory access request scheduling device, memory access request register heap, several Bank schedulers and a DRAM scheduler of comprising several Bank, it is characterized in that: also comprise several window constraint circuit, comprise a memory access request counter and length of window register in the window constraint circuit; As seen all write requests of window constraint circuit are set to; Memory access request register heap receives the memory access request of from processor, and the memory access request is saved in the memory access request register heap, and the witness marking of memory access request is set to invisible; Window constraint circuit is operated the witness marking of the memory access request of arrival in the memory access request register heap, is that the Bank scheduler is visible or invisible with the memory access request marks; The memory access request counter is counted the memory access request of as seen reading that enters memory access request register heap, when memory access request counter numerical value during less than the length of window register value, as seen invisible read request in the memory access request register is set to, memory access request count value accumulative total, when memory access request counter numerical value equals the memory access request of as seen reading in length of window register and the memory access request register heap and all is performed, the memory access request counter makes zero, as seen window constraint circuit memory access request is set to the Bank scheduler, the Bank scheduler is only dispatched visible memory access request, and the DRAM scheduler sends memory instructions according to the result of Bank scheduler to the DRAM scheduler.
2. method of utilizing the described memory access request scheduling of claim 1 device to carry out the memory access request scheduling is characterized in that may further comprise the steps:
(a) initialization window constraint circuit, it is zero that the memory access request counter is set, the length of window register is a preset value;
(b) receive the memory access request of from processor, when the memory access request register heap of the Bank of memory access request correspondence is discontented, this memory access request is saved in the memory access request register heap of corresponding Bank;
(c) window constraint circuit is provided with the memory access request in the memory access request register heap, when the memory access request is write request, then as seen it be set to, when the memory access request is read request, and memory access request counter value is less than the length of window register value, then as seen it be set to, otherwise be set to invisible;
(d) the Bank scheduler is dispatched the visible memory access request in the memory access request register heap, will preferentially send to the DRAM scheduler with Bank colleague's request;
(e) the DRAM scheduler sends memory instructions according to the memory access request of Bank scheduler to the DRAM scheduler;
(f) after the memory access request was finished, it is invalid that the preservation item of this memory access request in memory access request register heap is set to.
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| CN103559147B (en) * | 2013-11-11 | 2017-02-08 | 龙芯中科技术有限公司 | Memory access scheduling method, device and system |
| CN110688209B (en) * | 2019-09-10 | 2022-09-13 | 无锡江南计算技术研究所 | Binary tree-based large-window access flow scheduling buffer structure and method |
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| CN1735869A (en) * | 2001-09-27 | 2006-02-15 | 英特尔公司 | Method and apparatus for memory access scheduling to reduce memory access latency |
| CN101145113A (en) * | 2007-09-10 | 2008-03-19 | 中兴通讯股份有限公司 | Multi-thread access indirect register scheduling method |
| CN101470678A (en) * | 2007-12-29 | 2009-07-01 | 中国科学院声学研究所 | Outburst disorder based memory controller, system and its access scheduling method |
| CN201449602U (en) * | 2009-08-14 | 2010-05-05 | 西北工业大学 | Access memory request dispatching device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1735869A (en) * | 2001-09-27 | 2006-02-15 | 英特尔公司 | Method and apparatus for memory access scheduling to reduce memory access latency |
| CN101145113A (en) * | 2007-09-10 | 2008-03-19 | 中兴通讯股份有限公司 | Multi-thread access indirect register scheduling method |
| CN101470678A (en) * | 2007-12-29 | 2009-07-01 | 中国科学院声学研究所 | Outburst disorder based memory controller, system and its access scheduling method |
| CN201449602U (en) * | 2009-08-14 | 2010-05-05 | 西北工业大学 | Access memory request dispatching device |
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