CN100524749C - Silicon-base multi-layer helical differential inductance - Google Patents

Abstract

A silicon-based multilayer spiral differential inductor in the field of microelectronic technology. The invention includes: a substrate, six layers of silicon dioxide layers, six layers of metal spiral coils, connecting through holes, metal conductors and ports, the first layer of silicon dioxide layer is arranged on the silicon substrate, and the six layers of metal spiral coils respectively correspond to Set on six layers of silicon dioxide, the port is on the same plane as the metal helical coil of the sixth layer, and it is connected to both sides of the conductor of the first metal helical coil respectively, and the metal helical coils of different layers are connected through connecting through holes Then connect to the metal conductor. The invention has a simple structure, is easy to implement, and can minimize parasitic capacitance, thereby obtaining higher self-resonant frequency and higher quality factor. The optimal connection mode of the present invention greatly reduces the parasitic capacitance caused by electric field energy storage, thereby greatly improving the high-frequency performance of the micro-inductor and having wide applications.

Description

Silicon based multilayer spiral differential inductor

technical field

The invention relates to a multilayer spiral inductor, specifically a silicon-based multilayer spiral differential inductor, which has almost the same inductance value and the same chip size as a traditional differentially excited multilayer spiral inductor, and belongs to the field of electronic technology .

Background technique

In integrated circuits, active devices are very important, but they also include large-area passive devices, including on-chip transmission lines and on-chip inductors. In typical wireless products, inductive components account for less than 10% of the total components, but they have a significant impact on the overall RF performance. Therefore, the design and analysis of these passive components have also been extensively studied. Although the loss of the semiconductor silicon substrate and the thickness of the interconnection limit the performance of the on-chip inductor, the silicon integrated circuit has the advantages of relatively low manufacturing cost, easy integration of radio frequency and baseband circuits, and high integration to reduce the chip size. , RF integrated circuits on silicon substrates are still quite competitive. It is very attractive to design spiral inductors with high performance, especially the improvement under the existing process.

As the core component of the RF circuit, the spiral inductor can usually affect the overall performance of the entire circuit. It is widely used in voltage controlled oscillators, low noise amplifiers, power amplifiers, mixers and impedance matching circuits, etc. Spiral inductors have high quality factor, high resonant frequency and the smallest chip area. In order to effectively improve the quality factor of spiral inductors, some very special structures or manufacturing processes have been proposed, such as suspended vertical structures, differential drive modes, and line shielding. ground structure.

With the development of integrated circuit technology, the interconnection structure in the CMOS chip has developed from 4 layers of metal at 0.35 μm to 6 layers of metal at 0.18 μm, and even 8 layers at 90nm. These additional process conditions give the spiral inductor design a wider space to enhance the performance of the inductor. After searching the existing literature, it was found that A. Zolfaghari et al. published "Stacked inductors and transformers in CMOS technology," (multilayer inductors and transformers based on CMOS technology), this paper proposes to connect the inductors of each layer in series, that is, after the first layer is fully wound from the outside to the inside, it passes through the via hole to the second layer, and from the inside to the After the outer winding is full, continue to the third layer of winding (Figure 1). Such an inductor has a larger inductance than a planar inductor in the same area. In addition, C.Tang et al published "Miniature 3-D inductors in standard CMOS process," on IEEE J.Solid-State Circuit (vol.37, no.4, pp.471-479, 2002), (based on standard Miniaturized three-dimensional inductors in CMOS technology), which proposes that after the first circle of the first layer is completed, the second circle is not wound inward, but goes down to the second layer, and is wound at the same position as the first layer. After the second circle, and then to the third layer, enter the inner circle of the third layer to wind, and then retreat to the second layer and the first layer to wind respectively (Figure 2). Although the vertical solenoid inductance has many Advantages, but it also has a potential problem that limits its use, that is, the conductors between adjacent layers are completely overlapped and the distance is very close (usually less than 1 μm). Even if the capacitance between the turns is in series, the total value is considerable. When the vertical solenoid structure is directly applied to the differential inductor, since the high and low voltage conductors are directly adjacent, the electric field energy storage is extremely large, which greatly reduces the self-resonant frequency and quality factor of the inductor.

Contents of the invention

The purpose of the present invention is to design a new type of silicon-based multilayer spiral differential inductor for the deficiencies of the prior art, which has a simple structure, is easy to implement, and can minimize parasitic capacitance, thereby obtaining a higher self-resonant frequency and Higher quality factor.

The present invention is achieved through the following technical solutions, the present invention comprises: substrate, six-layer silicon dioxide layer, six-layer metal spiral coil, connection via hole, metal conductor and port, the first layer of silicon dioxide layer is arranged on the silicon lining On the bottom, the six layers of metal spiral coils are respectively arranged on the six layers of silicon dioxide, and the ports are on the same plane as the sixth layer of metal spiral coils, which are respectively connected to both sides of the conductors of the first layer of metal spiral coils. The metal helical coils of different layers are connected through the connection via holes and then connected to the metal conductor.

All inductors have a self-resonant frequency. The self-resonant frequency can be determined by the inverse relationship between the inductance of the coil and the residual capacitance of the inductor coil. The self-resonant frequency decreases with increasing residual capacitance. It is important to have as high a self-resonant frequency as possible, as this will allow the inductor to operate at higher frequencies. Therefore, in order to maximize the self-resonant frequency, it is necessary to reduce the residual capacitance in the inductor.

Differential spiral inductance is particularly important with the widespread application of differential circuits. Differential inductors with a traditional structure are wound from outside to inside or from top to bottom in sequence, regardless of whether they are planar or vertical. Such winding makes the high and low voltage wires coupled to each other to generate huge parasitic capacitance, which greatly limits the performance of the differential inductor. The invention redesigns the differential inductance, adopts a new winding sequence, and makes conductors with similar voltages close to each other to reduce parasitic capacitance. For the planar inductance, the group cross structure is adopted, which is easy to implement with two-layer interconnection; for the vertical inductance, the optimal connection structure is used to minimize the parasitic capacitance. The differential inductance of the new structure is consistent with the traditional structure in terms of external dimensions, low-frequency inductance, and manufacturing process, so it is a non-sacrificing improvement of the traditional differential inductance. As a typical multilayer inductor structure, the vertical multilayer inductor structure has superior performance. Compared with the planar inductor structure, it is very suitable for realizing a smaller chip footprint and a larger inductance.

Different connection sequences of differential inductors will produce different electric field energy storage. Since the types of connection sequences are limited, there is always a connection method with the lowest electric field energy storage. Because the length of each circle of the vertical inductor is equal, the voltage drop of the current in the circle is equal, so the voltage order is a linear function of the average voltage of the circle. In order to make the potential of the bottom circle close to zero, the selection range of the connection order is limited. limit, but it is still limited, so there is also the lowest order of electric field energy storage based on the above conditions. The invention manufactures vertical differential inductors on the SMIC 0.18μm process. As the number of layers increases, the improvement of the optimal connection sequence is more significant, so a total of six metal layers allowed by the process, that is, six turns of vertical differential inductors, are filled. The vias of traditional vertical differential inductors do not interfere with each other, so vias of different layers can be stacked to reduce the parasitic effect caused by the area of the connection area. The optimally connected inductor must have all the vias arranged in an array for more complex connections. When some layers are connected to vias, in order to avoid irrelevant vias, they have to be detoured from the outside. These curved wires and longer vias will slightly increase the series resistance of the inductor, but account for a very large part of the total series resistance. A small part, so the degradation of the low-frequency quality factor is very limited.

Therefore, the present invention provides an improved multi-layer differential inductor with high self-resonant frequency and high quality factor, which can make the self-resonant frequency much higher than the self-resonant frequency of the existing traditional differential inductor design, so that the voltage is similar The conductors are close to each other to reduce the parasitic capacitance, and it has the ability to manufacture smaller components. It is realized on the micron-scale process of the silicon substrate; it has superior performance. Compared with the planar inductance structure, it is very suitable for realizing smaller The area occupied by the chip and the large inductance; the labor cost is reduced, the output is increased, and the reliability of the components is improved, which is effective, durable and easy to produce.

Description of drawings

Figure 1 is a schematic diagram of the structure of a traditional multilayer inductor.

FIG. 2 is a schematic diagram of the structure of an existing miniaturized multilayer inductor.

Fig. 3 is a schematic side view of the structure of the present invention.

FIG. 4 is a schematic side view of a conventional silicon-based multilayer spiral differential inductor structure.

Fig. 5 is a schematic top view of the structure of the present invention.

FIG. 6 is a schematic top view of a conventional silicon-based multilayer spiral differential inductor structure.

Fig. 7 is a schematic diagram of a three-dimensional topological structure of the present invention.

FIG. 8 is a schematic diagram of a three-dimensional topological structure of a traditional silicon-based multilayer spiral differential inductor.

Among them, 1 is the silicon substrate layer, 2 is the first layer of silicon dioxide, 3 is the first layer of metal spiral coil, 4 is the second layer of metal spiral coil, 5 is the third layer of metal spiral coil, and 6 is the fourth layer of metal Spiral coil, 7 is the fifth layer of metal spiral coil, 8 is the sixth layer of metal spiral coil, 9 is the connection through hole, 10 is the port, 11 is the bottom center differential joint, 12 is the metal conductor, 13 is the second layer of carbon dioxide Silicon layer, 14 is the third silicon dioxide layer, 15 is the fourth silicon dioxide layer, 16 is the fifth silicon dioxide layer, and 17 is the sixth silicon dioxide layer.

Detailed ways

As shown in Fig. 3, Fig. 4, Fig. 5, Fig. 6, the present invention comprises: substrate 1, six layers of silicon dioxide layers 2, 13, 14, 15, 16, 17, six layers of metal spiral coils 3, 4, 5, 6, 7, 8, connecting the through hole 9, the metal conductor 12 and the port 10. The first layer of silicon dioxide layer 2 is arranged on the silicon substrate 1, the first layer of metal spiral coil 3 is located on the plane of the first layer of silicon dioxide layer 2, and the second layer of metal spiral coil 4 is located on the second layer of silicon dioxide layer 13 plane, the third layer of metal spiral coil 5 is located on the plane of the third layer of silicon dioxide layer 14, the fourth layer of metal spiral coil 6 is located on the plane of the fourth layer of silicon dioxide layer 15, and the fifth layer of metal spiral coil 7 is located on the plane of the silicon dioxide layer 14. On the plane of the fifth layer of silicon dioxide layer 16, the sixth layer of metal spiral coil 8 is located on the plane of the sixth layer of silicon dioxide layer 17, and the port 10 is on the same plane as the sixth layer of metal spiral coil 8 on the top layer. Both sides of the conductor of one layer of metal spiral coil 3 are respectively connected. The six-layer metal spiral coils 3 , 4 , 5 , 6 , 7 , and 8 are connected through the connecting through holes 9 and then connected to the metal conductor 12 .

As shown in Figure 7, the current of the structure of the present invention flows in from the port 10, passes through the sixth layer of metal spiral coil 8 on the left side, connects with the second layer of metal spiral coil 4 on the right side through the first connection through hole 9, and then passes through the second layer of metal spiral coil 4 on the right side. Two connecting through holes 9 are connected to the left metal coil 7, and then connected to the additional metal conductor 12 through the third connecting through hole 9, then connected to the third layer of metal spiral coil 5 on the right, and then connected to the metal conductor 12 Connection, through the fourth connection through hole 9 to connect with the metal spiral coil 6 on the fourth layer on the left, and finally through the fifth connection through hole 9 to connect with the metal spiral coil 3 on the first layer on the right, reaching the bottom center differential joint 11 at the end point . The connection of the metal helical coil on the right side starting from the uppermost layer is symmetrical to the connection of the metal helical coil on the left side described above.

As shown in Figure 8, the current of the traditional structure compared with the structure of the present invention flows in from the port 10, passes through the sixth layer of metal spiral coil 8 on the left side, and passes through the first connecting through hole 9 and the fifth layer of metal spiral coil 7 on the right side connected, and then connected to the left metal coil 6 through the second connecting through hole 9, and then connected to the third layer of metal spiral coil 5 on the right through the third connecting through hole 9, and then through the fourth connecting through hole 9 It is connected with the metal helical coil 4 of the second layer on the left, and finally connected with the first layer of metal helical coil 3 on the right through the fifth connection through hole 9 to reach the bottom center differential joint 11 at the end point. The connection of the metal helical coil on the right side starting from the uppermost layer is symmetrical to the connection of the metal helical coil on the left side described above.

The spatial shape of the connecting through hole 9 is a cuboid, with a height of 0.8 μm to 4.94 μm, a length and a width of 4 μm, and the number of connecting through holes is 10.

The thickness of the first layer of silicon dioxide layer 2 is 0.6 μm, the thickness of the second layer of silicon dioxide layer 13 is 1.28 μm, the thickness of the third layer of silicon dioxide layer 14 is 1.38 μm, and the thickness of the fourth layer of silicon dioxide layer 15 is 1.38 μm. μm, the thickness of the fifth silicon dioxide layer 16 is 1.38 μm, and the thickness of the sixth silicon dioxide layer 17 is 1.38 μm.

The shape of the first metal helical coil 1 is a cuboid helical coil, six layers of metal helical coils 3, 4, 5, 6, 7, 8, the conductor width is 10 μm, and the conductor thickness of the first metal helical coil 3 is 0.48 μm. Among them, the thickness of the conductors of the second, third, fourth, and fifth layers of metal spiral coils 4, 5, 6, and 7 is 0.58 μm, the thickness of the conductors of the sixth layer of metal spiral coils 8 is 0.86 μm, and the thickness of the conductors of the six layers of metal spiral coils 3 , 4, 5, 6, 7, 8 The inner diameter spacing between the conductors is 60μm.

The thickness of the metal conductor 12 is the same as that of the second-layer metal spiral coil 4, and the width is 4 μm.

The present invention has substantive features and significant progress. The optimal connection method of the present invention greatly reduces the parasitic capacitance caused by electric field energy storage, thereby greatly improving the high-frequency performance of the micro-inductance, so the optimal connection inductance ( Figure 7) The self-resonant frequency is much higher than that of the traditional inductor without improvement (Figure 8), reaching about one time. The inductance is improved not only in the self-resonant frequency, but also in the quality factor. After measurement: when the width of six-layer metal spiral coils 3, 4, 5, 6, 7, and 8 is 10 μm, and the inner diameter spacing between conductors is 60 μm, the inductance of this structure reaches 10nH near the resonance frequency of 19.5GHz, and its Q value It can reach 5, and its performance is much higher than that of traditional inductors with the same parameters.

Claims (7)

1. A silicon-based multilayer spiral differential inductor, comprising: substrate (1), six layers of silicon dioxide layers (2, 13, 14, 15, 16, 17), six layers of metal spiral coils (3, 4, 5, 6, 7, 8), connecting through holes (9), metal conductors (12) and ports (10), characterized in that: the first silicon dioxide layer (2) is arranged on the silicon substrate (1) , the first layer of metal spiral coil (3) is located on the plane of the first layer of silicon dioxide layer (2), the second layer of metal spiral coil (4) is located on the plane of the second layer of silicon dioxide layer (13), and the third layer The metal spiral coil (5) is positioned on the third layer of silicon dioxide layer (14) plane, the fourth layer of metal spiral coil (6) is positioned on the fourth layer of silicon dioxide layer (15) plane, and the fifth layer of metal spiral coil ( 7) Located on the plane of the fifth layer of silicon dioxide layer (16), the top layer of the sixth layer of metal spiral coil (8) is located on the plane of the sixth layer of silicon dioxide layer (17), the port (10) and the sixth layer of metal spiral The circle (8) is on a plane, and the port (10) is connected to both sides of the conductor of the first layer of metal helical coil (3), and the six layers of metal helical coils (3, 4, 5, 6, 7, 8) pass through The connecting through hole (9) is connected to the metal conductor (12) after being connected. 2. The silicon-based multilayer spiral differential inductor according to claim 1, characterized in that the six-layer metal spiral coils (3, 4, 5, 6, 7, 8) are in the shape of a cuboid, and the conductor width is 10 μm , The inner diameter spacing between conductors is 60μm. 3. The silicon-based multilayer spiral differential inductor according to claim 1 or 2, characterized in that the conductor thickness of the first metal spiral coil (3) is 0.48 μm, the second, third, fourth, and fifth The conductor thickness of the layer metal spiral coil (4, 5, 6, 7) is 0.58 μm, and the conductor thickness of the sixth layer metal spiral coil (8) is 0.86 μm. 4. The silicon-based multilayer spiral differential inductor according to claim 1 or 2, characterized in that the width of the six-layer metal spiral coils (3, 4, 5, 6, 7, 8) is 10 μm, and the inner diameter spacing between the conductors The silicon-based multilayer spiral differential inductor has an inductance of 10nH near the resonant frequency of 19.5GHz, and its Q value reaches 5. 5. The silicon-based multilayer spiral differential inductor according to claim 1, characterized in that the spatial shape of the connecting through hole (9) is a cuboid, the height is 0.8 μm to 4.94 μm, and the length and width are both 4 μm. The number of holes (9) is ten. 6. The silicon-based multilayer spiral differential inductor as claimed in claim 1, characterized in that the thickness of the first layer of silicon dioxide layer (2) is 0.6 μm, the substrate is silicon, and the thickness of the second layer of silicon dioxide layer is 0.6 μm. The thickness of the third layer to the sixth layer of silicon dioxide layer is 1.38 μm. 7. The silicon-based multilayer spiral differential inductor according to claim 1, characterized in that the thickness of the metal conductor (12) is the same as that of the second metal spiral coil (4), and the width is 4 μm.

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