CN100524749C - Silicon-base multi-layer helical differential inductance - Google Patents
Silicon-base multi-layer helical differential inductance Download PDFInfo
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- CN100524749C CN100524749C CNB2006100291375A CN200610029137A CN100524749C CN 100524749 C CN100524749 C CN 100524749C CN B2006100291375 A CNB2006100291375 A CN B2006100291375A CN 200610029137 A CN200610029137 A CN 200610029137A CN 100524749 C CN100524749 C CN 100524749C
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Abstract
The present invention relates to a silica-based support multilayer spiral difference inductor of microelectronic technique field. It contains substrate, six layers silicon dioxide, six layers metal spiral coil, connection through hole, metallic conductor and terminal; wherein first floor silicon dioxide layer set on silicon substrate, six layers metal spiral coil respectively corresponded set on six layers silicon dioxide layer, terminal and sixth layer metal spiral coil in one plane, respectively connected with both sides of first layer metal spiral coil conductor, different layered metal spiral coil connected through connection through hole and connected with metallic conductor. The present invention has simple structure and can lower spurious capacitance to the lowest, thereby to obtain higher self resonant frequency and higher figure of merit. The optimum connecting type of said invention greatly reduces electric field energy storage induced spurious capacitance, thereby largely raising micro-inductive high frequency performance.
Description
Technical field
The present invention relates to a kind of multi-layer helical inductance, specifically is a kind of silicon-base multi-layer helical differential inductance, has inductance value about the same and occupies onesize chip size with the multi-layer helical inductance of traditional difference excitation, belongs to electronic technology field.
Background technology
In integrated circuit, active device is no doubt extremely important, but has more comprised large-area passive device, comprises transmission line on the sheet, on-chip inductor.In common wireless product, inductance element only account for component population less than 10%, but they have very significant effects to total radio-frequency performance.Therefore design and the analysis to these passive components also obtained extensive studies.Though the loss of semiconductor silicon substrate and the thickness limits of interconnection line the performance of on-chip inductor, but since silicon integrated circuit to have manufacturing cost relatively low, be convenient to the integrated of radio frequency and baseband circuit, high integration makes advantages such as chip size reduces, and silicon substrate RF integrated circuit still has suitable competitiveness.Design has high performance spiral inductance, especially improves to have very large attraction under existing technology.
Spiral inductance is as the core component of radio circuit, and it can have influence on the overall performance of entire circuit usually.It is widely applied to voltage controlled oscillator, low noise amplifier, and power amplifier, in frequency mixer and the impedance matching circuit or the like.Spiral inductance has high quality factor, and high resonance frequency and minimum chip area are in order to improve the quality factor of spiral inductance effectively, people have proposed some very special structure or manufacturing process, for example unsettled vertical stratification, differential driving pattern, structures such as lines shielding ground.
Along with the development of integrated circuit technology, the 4 layer metal of the interconnection structure in the CMOS chip during from 0.35 μ m develop into 6 layers of metal of 0.18 μ m, and even under the 90nm 8 layers.These extra process conditions strengthen the performance of inductance for the spiral inductance design with more wide space.Find through retrieval existing document, people such as A.Zolfaghari are at IEEE J.Solid-State Circuit periodical (vol.36, no.4, pp.620-628, delivered " Stacked inductors and transformers in CMOS technology; " 2001) (based on the multilayer inductor and the transformer of CMOS technology), this article proposes the inductance of each layer is together in series, be that ground floor is from outside to inside after full, to the second layer, after full, proceed to the 3rd layer of coiling (Fig. 1) by through hole from inside to outside.Such inductance has bigger inductance value than planar inductor under equal area.People such as C.Tang is at IEEE J.Solid-State Circuit (vol.37 in addition, no.4, pp.471-479, delivered " Mini ature 3-D inductors in standard CMOS process; " 2002) (based on the three-dimensional inductance of the micro of standard CMOS process) literary composition, it after the first lap of this article proposition ground floor is finished inside coiling second circle, but down to the second layer, in the position same with ground floor, coiling second circle, again to the 3rd layer after intact, enter the 3rd layer inner ring coiling, retreat to then the second layer and ground floor respectively coiling (Fig. 2) though. vertical solenoid inductor has many advantages, and it also exists a potential problem to limit its use, be that conductor between the adjacent layer overlaps fully, and distance very near (usually less than 1 μ m).Even the electric capacity between the circle is series connection, but total value is also very considerable.When directly vertical solenoid structure being applied to differential inductance,, greatly reduced the self-resonant frequency and the quality factor of inductance because high-low pressure conductor direct neighbor makes the electric field energy storage especially big.
Summary of the invention
The objective of the invention is at the deficiencies in the prior art, design a kind of novel silicon-base multi-layer helical differential inductance, make it simple in structure, be easy to realize that it is minimum that parasitic capacitance is dropped to, thereby obtain higher self-resonant frequency and higher quality factor.
The present invention is achieved by the following technical solutions, the present invention includes: substrate, six layers of silicon dioxide layer, six layers of metal spiral coil, connecting through hole, metallic conductor and port, the ground floor silicon dioxide layer is arranged on the silicon substrate, six layers of metal spiral coil correspondence respectively is arranged on six layers of silicon dioxide layer, port and layer 6 metal spiral coil are on the plane, and it links to each other respectively with the conductor both sides of ground floor metal spiral coil.The metal spiral coil of different layers links to each other with metallic conductor after connecting by connecting through hole again.
All inductance all have self-resonant frequency.Reverse-power between the inductance that self-resonant frequency can be by coil and the residual capacitance of inductance coil is determined.Self-resonant frequency reduces along with the increase of residual capacitance.It is very important having high as far as possible self-resonant frequency, because this will make inductance work under higher frequency.Therefore, reach maximum, need reduce the residual capacitance in the inductance in order to make self-resonant frequency.
It is especially important that the difference spiral inductance seems along with the widespread usage of difference channel.No matter the differential inductance plane of traditional structure or vertical multilayer all are in order successively from outside to inside or coiling from top to bottom.Such coiling makes the lead of high low-voltage intercouple and produces huge parasitic capacitance, limited the performance of differential inductance greatly.This invention is adopted new coiling order to the differential inductance redesign, thereby makes the close conductor of voltage mutually near having reduced parasitic capacitance.Adopt the grouping chi structure for planar inductor, be easy to realize with two-layer interconnection; It is minimum to adopt best syndeton that parasitic capacitance is dropped to for vertical inductance.The differential inductance of new construction externally all keeps consistent with traditional structure on size, low frequency inductance value, the manufacture craft, therefore is that the no sacrifice of traditional differential inductance improves.As a kind of typical multilayer inductor structure, vertical multilayer inductor structure has superior good performance, and compared with the planar inductor structure, it is fit to realize less chip occupied area and bigger inductance value very much.
The different orders of connection of differential inductance will produce different electric field energy storage.Because the kind of the order of connection is limited, therefore always there is a kind of connected mode of minimum electric field energy storage.Because the equal in length of vertical each circle of inductance, the pressure drop of electric current in circle just equates, therefore voltage is the linear function of the average voltage of circle in proper order, for the current potential that makes the orlop circle approaches zero, the range of choice of the order of connection just is restricted, but still be limited, therefore also there is minimum electric field energy storage order based on above-mentioned condition.The present invention makes vertical differential inductance on SMIC 0.18 μ m technology.Because the number of plies is many more, the improvement that the best order of connection obtains is just remarkable more, therefore does six layers of metal level altogether that full technology allows, i.e. the vertical differential inductance of six circles.The through hole of the vertical differential inductance of tradition does not disturb mutually, therefore the through hole of different layers can be gathered into folds, to reduce the ghost effect that the join domain area brings.And the best inductance that connects must be lined up all through holes array, to realize comparatively complicated connection.When some layer is connected with through hole, in order to avoid incoherent through hole, have to from outside detour, lead that these are crooked and longer through hole will increase the series resistance of inductance slightly, but account for the minimum part of total series resistance, therefore the reduction of the low frequency quality factor that causes is very limited.
Therefore, the invention provides a kind of improved multilayer differential inductance with high self resonant frequency and high quality factor, it can make self-resonant frequency be far longer than the self-resonant frequency that existing traditional differential inductance designs, thereby make the close conductor of voltage mutually near having reduced parasitic capacitance, have the ability of making small parts, it is based upon on the silicon substrate micro process and realizes; Have superior good performance, compared with the planar inductor structure, it is fit to realize less chip occupied area and bigger inductance value very much; Reduce labour cost, improved output, and improved the reliability of parts, effective, durable and be easy to produce.
Description of drawings
Fig. 1 is traditional multilayer inductor structural representation.
Fig. 2 is existing micro type multilayer inductor structural representation.
Fig. 3 is a structural representation end view of the present invention.
Fig. 4 is existing silicon-base multi-layer helical differential inductance structural representation end view.
Fig. 5 is a structural representation vertical view of the present invention.
Fig. 6 is existing silicon-base multi-layer helical differential inductance structural representation vertical view.
Fig. 7 is a three-dimensional topology structural representation of the present invention.
Fig. 8 is traditional silicon-base multi-layer helical differential inductance three-dimensional topology structural representation.
Wherein 1 is layer-of-substrate silicon, 2 is the ground floor silicon dioxide layer, 3 is ground floor metal spiral coil, 4 is the second layer metal helical coil, 5 is the three-layer metal helical coil, and 6 is the 4th layer of metal spiral coil, and 7 is layer 5 metal spiral coil, 8 is layer 6 metal spiral coil, 9 is connecting through hole, and 10 is port, and 11 is bottom centered difference joint, 12 is metallic conductor, 13 is second layer silicon dioxide layer, and 14 is the 3rd layer of silicon dioxide layer, and 15 is the 4th layer of silicon dioxide layer, 16 is the layer 5 silicon dioxide layer, and 17 is the layer 6 silicon dioxide layer.
Embodiment
As Fig. 3, Fig. 4, Fig. 5, shown in Figure 6, the present invention includes: 1, six layer of silicon dioxide layer of substrate 2,13,14,15,16,17, six layers of metal spiral coil 3,4,5,6,7,8, connecting through hole 9, metallic conductor 12 and port one 0.Ground floor silicon dioxide layer 2 is arranged on the silicon substrate 1, ground floor metal spiral coil 3 is positioned on ground floor silicon dioxide layer 2 planes, second layer metal helical coil 4 is positioned on second layer silicon dioxide layer 13 planes, three-layer metal helical coil 5 is positioned on the 3rd layer of silicon dioxide layer 14 plane, the 4th layer of metal spiral coil 6 is positioned on the 4th layer of silicon dioxide layer 15 plane, layer 5 metal spiral coil 7 is positioned on layer 5 silicon dioxide layer 16 planes, layer 6 metal spiral coil 8 is positioned on layer 6 silicon dioxide layer 17 planes, port one 0 and top layer layer 6 metal spiral coil 8 places in one plane, it links to each other respectively with the conductor both sides of ground floor metal spiral coil 3.After connecting by connecting through hole 9, six layers of metal spiral coil 3,4,5,6,7,8 link to each other with metallic conductor 12 again.
As shown in Figure 7, the electric current of structure of the present invention flows into from port one 0, through left side layer 6 metal spiral coil 8, link to each other with right side second layer metal helical coil 4 by first connecting through hole 9, link to each other with left side wire coil 7 by second connecting through hole 9 again, and then be connected with the metallic conductor 12 that adds by the 3rd connecting through hole 9, be connected with right side three-layer metal helical coil 5 again, be connected with metallic conductor 12 again, link to each other by the 4th layer of metal spiral coil 6 in the 4th connecting through hole 9 and left side, link to each other with right side ground floor metal spiral coil 3 by the 5th connecting through hole 9 at last, reach terminal point bottom centered difference joint 11.The right side metal spiral coil that begins for the superiors connects situation, and to be connected situation with the metal spiral coil in described left side before be symmetric case.
As shown in Figure 8, flow into from port one 0 with the electric current of the traditional structure of structure of the present invention contrast, through left side layer 6 metal spiral coil 8, link to each other with right side layer 5 metal spiral coil 7 by first connecting through hole 9, link to each other with left side wire coil 6 by second connecting through hole 9 again, and then be connected with right side three-layer metal helical coil 5 by the 3rd connecting through hole 9, link to each other with left side second layer metal helical coil 4 by the 4th connecting through hole 9 again, link to each other with right side ground floor metal spiral coil 3 by the 5th connecting through hole 9 at last, reach terminal point bottom centered difference joint 11.The right side metal spiral coil that begins for the superiors connects situation, and to be connected situation with the metal spiral coil in described left side before be symmetric case.
The spatial form of connecting through hole 9 is a cuboid, highly is 0.8 μ m～4.94 μ m, and length and width are 4 μ m, and the number of connecting through hole is 10.
Ground floor silicon dioxide layer 2 thickness are 0.6 μ m, second layer silicon dioxide layer 13 thickness are 1.28 μ m, the 3rd layer of silicon dioxide layer 14 thickness are 1.38 μ m, the 4th layer of silicon dioxide layer 15 thickness are 1.38 μ m, layer 5 silicon dioxide layer 16 thickness are 1.38 μ m, and layer 6 silicon dioxide layer 17 thickness are 1.38 μ m.
Ground floor metal spiral coil 1 is shaped as the helical coil of cuboid, six layers of metal spiral coil 3,4,5,6,7,8, conductor width is 10 μ m, the conductor thickness of the first metal spiral coil 3 is 0.48 μ m, wherein second, third, the 4th, the conductor thickness of layer 5 metal spiral coil 4,5,6,7 is 0.58 μ m, the conductor thickness of layer 6 metal spiral coil 8 is 0.86 μ m, and the internal diameter spacing is 60 μ m between six layers of metal spiral coil 3,4,5,6,7,8 conductor.
The present invention has substantive distinguishing features and marked improvement, and Best link mode of the present invention has greatly reduced The parasitic capacitance that the electric field energy storage causes, thus the high frequency performance of little inductance can be improved to a great extent, therefore The self-resonant frequency of Best link inductance (Fig. 7) is much higher than the traditional inductance (Fig. 8) that does not make improvements, and reaches About one times. Inductance not only is improved in self-resonant frequency, also is improved on quality factor. Warp Measure: when six layers of metal spiral coil 3,4,5,6,7,8 width are 10 μ m, internal diameter spacing between conductor Be 60 μ m, near the inductance of this structure inductance value resonant frequency 19.5GHz reaches 10nH, its Q value Can reach 5, performance is higher than traditional inductance of identical parameters far away.
Claims (7)
1, a kind of silicon-base multi-layer helical differential inductance, comprise: substrate (1), six layers of silicon dioxide layer (2,13,14,15,16,17), six layers of metal spiral coil (3,4,5,6,7,8), connecting through hole (9), metallic conductor (12) and port (10), it is characterized in that: ground floor silicon dioxide layer (2) is arranged on the silicon substrate (1), ground floor metal spiral coil (3) is positioned on ground floor silicon dioxide layer (2) plane, second layer metal helical coil (4) is positioned on second layer silicon dioxide layer (13) plane, three-layer metal helical coil (5) is positioned on the 3rd layer of silicon dioxide layer (14) plane, the 4th layer of metal spiral coil (6) is positioned on the 4th layer of silicon dioxide layer (15) plane, layer 5 metal spiral coil (7) is positioned on layer 5 silicon dioxide layer (16) plane, top layer layer 6 metal spiral coil (8) is positioned on layer 6 silicon dioxide layer (17) plane, port (10) is located in one plane with layer 6 metal spiral circle (8), port (10) links to each other respectively with the conductor both sides of ground floor metal spiral coil (3), six layers of metal spiral coil (3,4,5,6,7,8) by linking to each other with metallic conductor (12) again after connecting through hole (9) connection.
2, silicon-base multi-layer helical differential inductance as claimed in claim 1 is characterized in that, six layers of metal spiral coil (3,4,5,6,7,8), and it is shaped as cuboid, and conductor width is 10 μ m, and the internal diameter spacing is 60 μ m between conductor.
3, as claim 1 or 2 described silicon-base multi-layer helical differential inductances, it is characterized in that, the conductor thickness of ground floor metal spiral coil (3) is 0.48 μ m, second, third, the 4th, the conductor thickness of layer 5 metal spiral coil (4,5,6,7) is 0.58 μ m, the conductor thickness of layer 6 metal spiral coil (8) is 0.86 μ m.
4, as claim 1 or 2 described silicon-base multi-layer helical differential inductances, it is characterized in that, six layers of metal spiral coil (3,4,5,6,7,8) width is 10 μ m, the internal diameter spacing is 60 μ m between its conductor, near silicon-base multi-layer helical differential inductance inductance value resonance frequency 19.5GHz reaches 10nH, and its Q value reaches 5.
5, silicon-base multi-layer helical differential inductance as claimed in claim 1 is characterized in that, the spatial form of connecting through hole (9) is a cuboid, highly is 0.8 μ m～4.94 μ m, and length and width are 4 μ m, and the number of connecting through hole (9) is 10.
6, silicon-base multi-layer helical differential inductance as claimed in claim 1, it is characterized in that ground floor silicon dioxide layer (2) thickness is 0.6 μ m, its substrate is a silicon, second layer silicon dioxide layer thickness is 1.28 μ m, and the 3rd layer is 1.38 μ m to layer 6 silicon dioxide layer thickness.
7, silicon-base multi-layer helical differential inductance as claimed in claim 1 is characterized in that, metallic conductor (12) thickness is identical with the second metal spiral coil (4), and width is 4 μ m.
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| TWI594572B (en) * | 2014-12-10 | 2017-08-01 | Murata Manufacturing Co | Electronic parts |
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| CN101707478B (en) * | 2009-11-24 | 2012-05-16 | 南京航空航天大学 | Eliminator for parasitic inductance of smoothing capacitor |
| CN102087996A (en) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | Method for manufacturing integrated circuit with thickened top and sub-top metals, and laminated inductor |
| CN102103921B (en) * | 2009-12-16 | 2013-01-30 | 瑞昱半导体股份有限公司 | Stacked structure of spiral inductor |
| CN102097429B (en) * | 2011-03-04 | 2012-07-04 | 杭州电子科技大学 | Differential integrated spiral inductor in vertical structure |
| CN103077809A (en) * | 2011-10-26 | 2013-05-01 | 上海华虹Nec电子有限公司 | Symmetrical stacked inductor structure and winding method thereof |
| CN104051229B (en) * | 2013-03-11 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Passive device manufacturing process and its manufactured passive device are integrated in a kind of copper wiring |
| CN104733452B (en) * | 2013-12-19 | 2018-02-02 | 深圳市中兴微电子技术有限公司 | A kind of transformer and preparation method thereof and chip |
| CN104037165A (en) * | 2014-06-05 | 2014-09-10 | 西安电子科技大学 | Differential helical inductor |
| CN106898456B (en) * | 2015-12-21 | 2019-05-10 | 瑞昱半导体股份有限公司 | Helical form stack product body inductance and transformer |
| CN109860148A (en) * | 2019-03-18 | 2019-06-07 | 西安电子科技大学 | It is layered multiport spiral inductor |
| CN113053622B (en) * | 2021-03-18 | 2022-06-24 | 无锡豪帮高科股份有限公司 | Radio frequency inductor with three-dimensional structure and design method thereof |
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| 硅衬底RF集成电路螺旋电感品质因数Q的优化. 潘瑞，毛军发，王彬.高技术通讯，第2003.7期. 2003 |
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| TWI594572B (en) * | 2014-12-10 | 2017-08-01 | Murata Manufacturing Co | Electronic parts |
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