CN101707478B

CN101707478B - Eliminator for parasitic inductance of smoothing capacitor

Info

Publication number: CN101707478B
Application number: CN2009102343397A
Authority: CN
Inventors: 崔永生; 王世山; 周小林; 武丽芳
Original assignee: Nanjing University of Aeronautics and Astronautics
Current assignee: Nanjing University of Aeronautics and Astronautics
Priority date: 2009-11-24
Filing date: 2009-11-24
Publication date: 2012-05-16
Anticipated expiration: 2029-11-24
Also published as: CN101707478A

Abstract

The invention provides an eliminator for parasitic inductance of a smoothing capacitor, which comprises a printed circuit board (401), and an upper layer plane helical coil (402) and a lower layer plane helical coil (403) which are arranged on the printed circuit board (401). The upper layer plane helical coil and the lower layer plane helical coil are formed by connecting im semi-circular PCB windings end to end of which semi-diameters are increased successively; the semi-circular PCB windings with the same semi-diameter are symmetrical about mirror image, so that the upper layer plane helical coil and the lower layer plane helical coil are in staggered arrangement; the upper layer plane helical coil is connected in series with the lower layer plane helical coil through a through hole E which is formed on the printed circuit board (401) to form an orthodromic coupled structure, namely, the directions of currents in the upper layer plane helical coil and the lower layer plane helical coil are the same. The through hole E is also used for accommodating a pin of the capacitor; the values of mutual inductance and the parasitic inductance are the same by controlling the number of the semi-circular PCB windings in the upper layer plane helical coil and the lower layer plane helical coil according to the parasitic inductance value of the capacitor.

Description

Eliminating device for parasitic inductance of filter capacitor

Technical Field

The invention relates to a device for eliminating parasitic parameters of components, in particular to a device for eliminating parasitic inductance of a filter capacitor.

Background

The capacitor works under the condition of high frequency, and the equivalent model thereof is composed of self capacitance C₁₁Equivalent inductance L₁₁And an equivalent resistance R₁₁In series, as shown in FIG. 1. Due to the existence of parasitic inductance, resonance can occur on the capacitance branch, and the impedance characteristic higher than the resonance frequency shows inductance, so that the bypass effect of the capacitor on high-frequency noise is reduced sharply, and the high-frequency performance of the capacitor is reduced.

In order to improve the high-frequency characteristics of the capacitor, a large amount of research is carried out by domestic and foreign scholars on the elimination of the parasitic inductance of the capacitor, particularly the elimination of the parasitic inductance of the capacitor in an EMI filter, and two methods are developed in the technical field at present:

first, in the multi-capacitor parallel method, parasitic inductance and parasitic resistance of the capacitor are reduced due to parallel connection. Wang S, university of Virginia rational, proposes a structure with capacitors connected in parallel in a crossed manner, and after circuit equivalence, parasitic inductance of a filter capacitor can be eliminated. However, the capacitor parallel connection requires an increase in the number of capacitors, so that the volume of the EMI filter becomes large.

Secondly, a coupling inductance method is adopted to offset the parasitic inductance of the filter capacitor.

FIG. 2 shows that in 2007A new method for eliminating parasitic inductance of differential mode capacitor of EMI filter (patent No. US 7180389B2) uses a 3/4 turn coil L₂₁Is closely attached to the capacitor C₂₂So that the parasitic inductance L of the coil and the capacitor₂₂Is equal to the parasitic inductance L₂₂Therefore, the influence of parasitic inductance of the capacitor is eliminated, and the high-frequency characteristic of the whole filter is improved. However, 3/4 turns of the coil are made to have large discreteness for different capacitors, so that the mutual inductance value of the capacitor parasitic inductance is not easy to control.

Fig. 3A shows a structure proposed by american scholars t.c.neugebauer et al to eliminate parasitic inductance of a capacitor, in which a coil 301 is an upper PCB winding and a coil 302 is a lower PCB winding, which are connected together by a via at O points and mounted below the capacitor. The method effectively eliminates the parasitic inductance of the capacitor by applying the mutual inductance of the two planar spiral coils under the condition of not increasing the physical volume of the EMI filter, thereby opening up a new way for researching the parasitic effect of the EMI filter. FIG. 3B is a cross-sectional view taken along line M-N, in which the upper and

lower coils

301 and 302 are disposed opposite to each other, and the distributed capacitance C is formed therebetween₃₁Larger, thereby bringing about the problem of secondary parasitic effect and influencing the elimination effect.

Disclosure of Invention

The purpose of the invention is as follows:

the invention aims to provide a device for eliminating parasitic inductance of a capacitor, which reduces secondary parasitic capacitance caused by adding an eliminating device when the parasitic inductance of the capacitor is eliminated compared with the prior art.

The invention content is as follows:

the invention adopts the following technical scheme to achieve the aim of the invention,

a device for eliminating parasitic inductance of a filter capacitor comprises a printed circuit board, an upper-layer plane spiral coil and a lower-layer plane spiral coil, wherein the upper-layer plane spiral coil is arranged on the upper surface of the printed circuit board, the lower-layer plane spiral coil is arranged on the lower surface of the printed circuit board, a first via hole and a second via hole are also formed in the printed circuit board, the upper-layer plane spiral coil and the lower-layer plane spiral coil are arranged in a staggered mode, and the synonym end of the upper-layer plane spiral coil is connected with the synonym end of the lower-layer plane spiral coil through the first via hole; the first through hole is connected with the first pin of the capacitor, and the second through hole is connected with the second pin of the capacitor.

The eliminating device of the parasitic inductance of the filter capacitor comprises an upper layer plane spiral coil and a lower layer plane spiral coil which are respectively formed by i_mThe semi-circular PCB windings with the radius increased according to the winding width are connected end to form the structure, wherein i_mIs a positive integer, i_mAccording to the size of the parasitic inductance.

The number of the semicircular PCB windings contained in the upper and lower layer plane spiral coils can be the same or different. Semi-circular PCB windings with the same radius in the upper and lower layer plane spiral coils are in mirror symmetry, so that the upper and lower layer plane spiral coils are arranged in a staggered mode. Then the upper and lower layer plane spiral coils are connected in series through a via hole E to form a forward coupling structure, namely the current flow directions in the upper and lower layer spiral coils are the same. Meanwhile, the through hole E is used for placing one pin of the capacitor, and the mutual inductance is equal to the parasitic inductance value by controlling the number of the semicircular PCB windings in the upper and lower coils according to the parasitic inductance value of the capacitor.

Has the advantages that:

the invention adopts the winding staggered structure of the planar PCB, so that the invention does not increase the volume and the cost of the filter, reduces the dead area of the upper and lower layers of windings, and effectively reduces the influence of the secondary parasitic capacitance of the elimination device on the improvement of the high-frequency characteristic of the capacitor.

The device for eliminating the parasitic inductance of the capacitor can conveniently control the mutual inductance between the upper coil and the lower coil.

The invention can be applied to filtering devices containing capacitors, such as EMI filters, LC low-pass filters, band-pass filters and the like, and improves the high-frequency characteristic of the capacitors, thereby improving the insertion loss of the filters.

Drawings

Fig. 1 is a model of an actual capacitor.

Fig. 2 is a block diagram of the 3/4 turn coil cancellation capacitor parasitic inductance shown in US 7180389B 2.

Fig. 3A shows a structure of a device for eliminating parasitic inductance of a capacitor in the prior art.

Fig. 3B is an enlarged cross-sectional view taken along line M-N shown in fig. 3A.

Fig. 4A is a novel capacitor parasitic inductance cancellation arrangement.

Fig. 4B is an equivalent circuit of fig. 4A.

Fig. 4C is the decoupling equivalent circuit of fig. 4B.

Fig. 5 is a single layer planar spiral winding structure.

Fig. 6 is an enlarged sectional view taken along the line M-N shown in fig. 4A.

Detailed Description

The technical scheme of the invention is explained in detail in the following with the accompanying drawings:

as shown in fig. 4A, the apparatus for eliminating parasitic inductance of a capacitor according to the present invention includes a PCB board 401 for mounting a capacitor 404, and two

PCB winding coils

402 and 403, which are respectively disposed on the upper layer and the lower layer of the PCB board and are coupled in a forward direction, that is, the end a of the upper coil 402 and the end C of the lower coil 403 are named ends, and the end B, C is connected by a via E. Pins G and H of capacitor 404 are mounted on vias E and F, respectively, and the parasitic inductance of the capacitor can be eliminated in accordance with the above-described connections.

FIG. 4B is the equivalent circuit diagram of FIG. 4A, wherein the inductance values of the upper and

lower PCB coils

402 and 403 are L₄₁And L₄₂，M₄₁Is mutual inductance, C₄₂Is the distributed capacitance between

coils

402 and 403, C₄₁Is the capacitance value, L, of capacitor 404₄₃Is the parasitic inductance, R, of the capacitor 404₄₁Is the parasitic resistance of capacitor 404. The equivalent circuit after the decoupling of FIG. 4B is as shown in FIG. 4C, and a negative inductance is generated, and the magnitude of the negative inductance is controlled to be equal to the parasitic inductance L of the capacitor₄₃The influence of the parasitic inductance on the filtering effect of the capacitor can be eliminated.

The single-layer inductance winding of the device for eliminating the parasitic inductance of the capacitor is formed by i_mThe semi-circular PCB winding with the radius increased according to the winding width is formed by connecting the end to end, the turns of the upper layer and the lower layer can be equal or unequal, and the mutual inductance of the semi-circular PCB winding is only ensured to be matched with the parasitic inductance of the capacitor. The upper and lower layers of the coil in this example have the same number of turns and the single layer coil structure is sized as shown in fig. 5. Omega_iRepresenting a semicircle, can be described as: r is_i＝0.5[2r₁+(i-1)(w+s)]、R_i＝0.5[2r₁+2w+(i-1)(w+s)]，(i＝1，2，3，4……)，r_iIs the i-th inner radius of the semicircle, R_iIs the i-th semicircular outer radius, d_inThe minimum semi-circle inner diameter is w, the winding width is w, and the winding space is s, so that the purpose of staggering can be realized by fully utilizing the space, the winding space is equal to the winding width, namely w is equal to s. In addition, the number of turns of the spiral coil is defined as: n ═ i_m/2, wherein i_mThe single-layer winding comprises a semicircle number.

The mutual inductance is determined by the number of turns of the upper and lower layers of PCB coils, the outer radius and the thickness h of the PCB, the thickness of the common PCB is a fixed value, and the width of the winding is determined according to the current density. Therefore, the number of turns n of the winding and the radius r of the first semicircle can be changed₁The mutual inductance can be controlled to match the parasitic inductance of the capacitor.

Can be based on

Wherein,

R_{i_{m}} = 0.5 [{2 r}_{1} + 2 w + (i_{m} - 1) (w + s)]

is the largest radius, r₁For the minimum radius, Φ determines its value according to the following equation,

<math> <mrow> <mn>4</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mfrac> <mn>2</mn> <mn>3</mn> </mfrac> <msup> <mi>ξ</mi> <mn>2</mn> </msup> <mo>-</mo> <mfrac> <mn>2</mn> <mn>5</mn> </mfrac> <msup> <mi>ξ</mi> <mn>4</mn> </msup> <mo>-</mo> <mfrac> <mn>1</mn> <mn>3</mn> </mfrac> <msup> <mi>ξ</mi> <mn>2</mn> </msup> <msup> <mi>ρ</mi> <mn>2</mn> </msup> <mo>)</mo> </mrow> <mfrac> <mi>ξ</mi> <mi>ρ</mi> </mfrac> <mi>arctan</mi> <mfrac> <mi>ρ</mi> <mi>ξ</mi> </mfrac> <mo>-</mo> <mn>1</mn> <mo>+</mo> <mfrac> <mn>37</mn> <mn>24</mn> </mfrac> <msup> <mi>ξ</mi> <mn>2</mn> </msup> <mo>+</mo> <mfrac> <mn>43</mn> <mn>144</mn> </mfrac> <msup> <mi>ρ</mi> <mn>2</mn> </msup> <mo>-</mo> <mfrac> <mn>301</mn> <mn>360</mn> </mfrac> <msup> <mi>ξ</mi> <mn>4</mn> </msup> <mo>-</mo> <mfrac> <mn>1</mn> <mn>270</mn> </mfrac> <msup> <mi>ξ</mi> <mn>2</mn> </msup> <msup> <mi>ρ</mi> <mn>2</mn> </msup> <mo>+</mo> <mfrac> <mn>1</mn> <mn>75</mn> </mfrac> <msup> <mi>ρ</mi> <mn>4</mn> </msup> <mo>]</mo> </mrow> </math>

wherein,

h is the thickness of the PCB. R is determined according to the value of parasitic inductance of the capacitor and the packaging form of the capacitor in specific application₁So that the number i of semi-circles of suitable cancellation means can be calculated_mThis value is rounded.

FIG. 6 is a cross-sectional view taken along line M-N of FIG. 4A, showing a capacitor C₄₂In order to distribute capacitance between the upper layer coil 403 and the lower layer coil 402 as secondary parasitic capacitance, the parasitic inductance eliminating device of the capacitor provided by the invention has the advantages that the upper layer PCB inductance coil and the lower layer PCB inductance coil are arranged in a staggered manner, and the upper layer coil 403 and the lower layer coil 402 are completely staggered at the position M-N, so that the secondary parasitic capacitance C is effectively reduced₄₂The size of (2) reduces the influence of secondary parasitic capacitance on the filter circuit after the accessory removal device.

Although a specific example of the present invention in which the upper and lower coils have the same number of turns is described in detail above, it should be understood that the embodiments of the present invention are not limited thereto, and this example is only for the purpose of facilitating understanding of the present invention, and examples of the present invention in which the upper and lower coils have different numbers of turns should be included in the scope of the present invention.

Claims

1. A filter capacitor parasitic inductance eliminating device is characterized in that: the circuit comprises a printed circuit board (401), an upper-layer plane spiral coil (402) and a lower-layer plane spiral coil (403), wherein the upper surface of the printed circuit board (401) is provided with the upper-layer plane spiral coil (402), the lower surface of the printed circuit board (401) is provided with the lower-layer plane spiral coil (403), the printed circuit board (401) is also provided with a first via hole (E) and a second via hole (F), the upper-layer plane spiral coil (402) and the lower-layer plane spiral coil (403) are arranged in a staggered manner, and the synonym end of the upper-layer plane spiral coil (402) is connected with the synonym end of the lower-layer plane spiral coil (403) through the first via hole (E); the first via hole (E) is connected with a first pin (G) of the capacitor (404), and the second via hole (F) is connected with a second pin (H) of the capacitor (404);

the upper layer plane spiral coil (402) and the lower layer plane spiral coil (403) are respectively formed by i_mThe semi-circular PCB windings with the radius increased according to the winding width are connected end to form the structure, wherein i_mIs a positive integer, i_mThe parasitic inductance is determined according to the size, specifically according to the formula:

obtaining; wherein,

is the maximum radius of the planar spiral coil, r₁The minimum radius of a planar spiral coil, w the winding width, s the winding spacing, M the value of the parasitic inductance, Φ the value of which is determined according to the following equation:

wherein,

h is the thickness of the PCB.