CN100516779C - Capacitance resistance induction circuit structure - Google Patents
Capacitance resistance induction circuit structure Download PDFInfo
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- CN100516779C CN100516779C CNB2007100379785A CN200710037978A CN100516779C CN 100516779 C CN100516779 C CN 100516779C CN B2007100379785 A CNB2007100379785 A CN B2007100379785A CN 200710037978 A CN200710037978 A CN 200710037978A CN 100516779 C CN100516779 C CN 100516779C
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Abstract
The invention discloses a novel capacitor resistance sensing circuit, comprising a voltage buffer, a current mirror, a sensitive resistance, a sensitive capacitor, an initial comparator, an end comparator, and a time digit converter TDC, wherein a reference voltage is fed into an input of the voltage buffer while an output of the voltage buffer is respectively connected with the input of the current mirror and the sensitive resistance, and the output of the current mirror is respectively connected with the sensitive capacitor, the input of the initial comparator and the input of the end comparator, and the outputs of the initial comparator and the end comparator are connected with the time digit converter TDC, the reference voltage via the voltage buffer and the sensitive resistance generates a reference current which via the current mirror is converted into a charge current to charge the sensitive capacitor, the pins of the sensitive capacitor are connected with the initial comparator and the end comparator, and the outputs of the initial comparator and the end comparator are connected with the STA and END control pins of the time digit converter TDC which converts the time value into data to be processed by a data input processor.
Description
Technical field
The present invention relates to a kind of circuit framework, particularly a kind of novel capacitor resistance induction circuit structure that is used for inductance capacitance, resistance value.
Background technology
Long-run development is gone through in the design of man-machine interface, develop into various products based on technology such as infrared ray, surface acoustic wave, resistance induction, capacitive sensings by the mechanical switch of Electromechanical Control, wherein emerging resistance induction, capacitive sensing technology become the focus that the designer pays close attention to advantages such as its low cost, durability, reliabilities.
The essence of resistance induction is IDC (Impedance to Digital Converter) resistance digital quantizer.Resistance is converted to digital signal for processor processing.Here resistance can be owing to STRESS VARIATION changes, so system just becomes the stress digital quantizer; Also can be a temperature variant resistance, so system is exactly the temperature digital converter.The essence of capacitive sensing is CDC (Capacitanceto Digital Converter), and changes in capacitance can be that STRESS VARIATION causes equally, also can be to touch to cause, or the bottom crown motion causes on the electric capacity.Just because of capacitance resistance can be responded to so various natural sign, capacitance resistance induction circuit is actually an ADC (Analog toDigital Converter analog-digital converter) truly, many natural analog signal conversion are become digital signal and only is that aanalogvoltage is converted to digital signal unlike traditional ADC.Just because of this, a capacitance resistance induction IC (integrated circuit) who simplifies practicality has and wide application prospect.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of novel capacitor resistance induction circuit structure, can select inductance capacitance or inductive reactance according to the nature amount of actual sensed.For example should consider in the application of electric field complexity that inductive reactance changes; And change in displacement, media variations then is fit to inductance capacitance and changes, and simple in structure, practical, application prospect is extensive.
Technical matters to be solved by this invention can be achieved through the following technical solutions:
A kind of novel capacitor resistance induction circuit structure is characterized in that, it comprises voltage buffer, current mirror, inductive reactance, inductance capacitance, initial comparer, finishes comparer and time-to-digit converter TDC; Reference voltage inserts the input end of described voltage buffer, the output terminal of voltage buffer connects the input end and the inductive reactance of described current mirror respectively, the output terminal of described current mirror connects the input end of inductance capacitance, initial comparer respectively and finishes the input end of comparer, and the output terminal of described initial comparer and end comparer inserts described time-to-digit converter TDC; Reference voltage produces reference current through voltage buffer and inductive reactance, reference current converts charging current to by current mirror inductance capacitance is charged, the pin of inductance capacitance connects initial comparer and finishes comparer, and STA and END control pin that the output of initial comparer and end comparer meets time-to-digit converter TDC are converted into the processing of data input processor by time-to-digit converter TDC with time quantum.
Described inductive reactance is connected with described voltage buffer by a non-essential resistance pin, and another termination external electric is flat; Described inductance capacitance is connected with the input end that finishes comparer with the input end of the output terminal of described current mirror, initial comparer by an external capacitive pin, and another termination external electric is flat.
Described voltage buffer is followed the NMOS pipe that is connected by an error amplifier and a source and is constituted; The positive pole of described reference voltage put-into error amp.in, the output terminal of error amplifier connects the grid of NMOS pipe, the source electrode of NMOS pipe inserts described inductive reactance with after the negative pole of error amplifier input end is connected, and the drain electrode of described NMOS pipe inserts the input end of described current mirror.
For the interference on the isolating exterior power supply, insert a low drop out voltage regurator at described voltage buffer, initial comparer with before finishing comparer, it is made of reference source, error amplifier, PMOS pipe and divider resistance, described reference source inserts the negative pole of amp.in, and the output terminal of error amplifier is connected with the grid of PMOS pipe; External power source inserts the source electrode of PMOS pipe, and the drain electrode of PMOS pipe connects four divider resistances ground connection then successively, produces three reference voltages between the divider resistance, the reference voltage end in the middle of the positive pole of error amplifier input end inserts.
Described current mirror is made of metal-oxide-semiconductor MP1, MP2; The grid of metal-oxide-semiconductor MP1, MP2 is connected to each other, and is connected the input end as current mirror then with the drain electrode of metal-oxide-semiconductor MP1, and the source electrode of metal-oxide-semiconductor MP1, MP2 is connected to each other, and the drain electrode of metal-oxide-semiconductor MP2 is as the output terminal of current mirror.
Above-mentioned current mirror is a kind of easy current mirror, and the unequal electric current that will cause of the drain terminal voltage of metal-oxide-semiconductor MP1 and MP2 can be not proportional by mirror image; In order to overcome the existing problem of common current mirror, the invention provides the common-source common-gate current mirror of another kind of resistance self-bias, good PSRR (supply-voltage rejection ratio) and mirror-image property are arranged, it is made of metal-oxide-semiconductor MP1, MP2, MP3, MP4 and resistance R a; The source electrode of metal-oxide-semiconductor MP1, MP2 is connected to each other, the drain electrode of metal-oxide-semiconductor MP1, MP2 is connected with the source electrode of metal-oxide-semiconductor MP3, MP4 respectively, the grid of metal-oxide-semiconductor MP1, MP2 is connected to each other, be connected with resistance R a with the drain electrode of metal-oxide-semiconductor MP3 respectively then, the grid of metal-oxide-semiconductor MP3, MP4 is connected to each other, and then be connected with the other end of resistance R a, as the input end of current mirror, the drain electrode of metal-oxide-semiconductor MP4 is as the output terminal of current mirror.
Another drain terminal follow current mirror, it is made of metal-oxide-semiconductor MP1, MP2, MP3 and error amplifier EA; The source electrode of metal-oxide-semiconductor MP1, MP2 is connected to each other, the drain electrode of metal-oxide-semiconductor MP1 connects the negative pole of metal-oxide-semiconductor MP3 source electrode and error amplifier EA input end respectively, the grid of metal-oxide-semiconductor MP1, MP2 is connected to each other, drain electrode with metal-oxide-semiconductor MP3 is connected then, as the input end of current mirror, the grid of metal-oxide-semiconductor MP3 connects the output terminal of error amplifier EA; The drain electrode of metal-oxide-semiconductor MP2 is connected with the positive pole of error amplifier EA input end, as the output terminal of current mirror.The drain terminal voltage of metal-oxide-semiconductor MP2 can be fed back to the drain terminal of metal-oxide-semiconductor MP1 by error amplifier EA and metal-oxide-semiconductor MP3, makes the electric current that flows through metal-oxide-semiconductor MP1, MP2 reach the proportionate relationship of expectation, and weak point is that error amplifier can consume extra power consumption.
Principle of the present invention is as follows:
Reference voltage V
REFProduce one road reference current I through voltage buffer and inductive reactance
1, reference current I
1Convert charging current I to by current mirror
2To the inductance capacitance charging, when the inductance capacitance pin reaches nominal level V
STAThe time, initial comparer upset, time-to-digit converter TDC picks up counting; When the inductance capacitance pin reaches a higher nominal level V
ENDThe time, finishing the comparer upset, time-to-digit converter TDC finishes timing, and this time interval is converted into data and gives processor processing.
Inductive reactance Rs both end voltage is V
REF-V
PR, twice turnover voltage on the inductance capacitance Cs is V
STA-V
PCAnd V
END-V
PCFor ease of explanation, only consider the equal ground connection of the other end of inductive reactance Rs and inductance capacitance Cs, i.e. V
PR=V
PC=0.
Q＝IT＝VC
T＝(V
END-V
STA)Cs/I
2
I
2＝mI
1＝mV
REF/Rs
T＝RsCs*(V
END-V
STA)/mV
REF
Wherein m is the mirror image coefficient of current mirror, reference voltage V
END, V
STAAnd V
REFProduce by a reference voltage dividing potential drop, so (V
END-V
STA)/mV
REFBe constant, establishing this constant is β.
T＝βRsCs
If V
PR, V
PC≠ 0
T＝RsCs*(V
END-V
STA)/m(V
REF-V
PR)
As long as V
END, V
STA, V
PRAnd V
REFProduced by same benchmark, the equivalence of also can cancelling out each other becomes constant.
If inductive reactance Rs is constant, then inductance capacitance Cs changes delta C=T/ β Rs regulates the induction precision that inductive reactance Rs can regulate inductance capacitance Cs.
If inductance capacitance Cs is constant, then inductive reactance Rs changes delta R=T/ β Cs regulates the induction precision that inductance capacitance Cs can regulate inductive reactance Rs.
A kind of novel capacitor resistance induction circuit structure of the present invention has following advantage:
1, the resistance capacitance value is converted to a time quantum, and this time quantum is only on duty long-pending relevant with resistance capacitance, and irrelevant with supply voltage and reference voltage.
2, applying flexible during inductance capacitance, is regulated non-essential resistance and can be regulated induction precision.During inductive reactance, regulate external capacitive and can regulate induction precision.
Description of drawings
Further specify the present invention below in conjunction with the drawings and specific embodiments.
Fig. 1 is the circuit theory diagrams of a kind of novel capacitor resistance induction circuit structure of the present invention;
Fig. 2 is the circuit theory diagrams of low drop out voltage regurator of the present invention;
Fig. 3 is the circuit theory diagrams of a kind of current mirror of the present invention;
Fig. 4 is the circuit theory diagrams of another kind of current mirror of the present invention.
Embodiment
Embodiment 1
As shown in Figure 1, a kind of novel capacitor resistance induction circuit structure, it comprises voltage buffer (106), current mirror (107), inductive reactance (101), inductance capacitance (102), initial comparer (103), finishes comparer (104) and time-to-digit converter TDC (105); Reference voltage V
REFInsert the input end of voltage buffer (106), the output terminal of voltage buffer (106) connects the input end and the inductive reactance (101) of current mirror (107) respectively, the output terminal of current mirror (107) connects the input end of inductance capacitance (102), initial comparer (103) respectively and finishes the input end of comparer (104), the output terminal digital quantizer turn-on time TDC (105) of initial comparer (103) and end comparer (104); Reference voltage V
REFProduce reference current I through voltage buffer (106) and inductive reactance (101)
1, reference current I
1Convert charging current I to by current mirror (107)
2Inductance capacitance (102) is charged, the pin of inductance capacitance (102) connects initial comparer (103) and finishes comparer (104), and STA and END control pin that the output of initial comparer (103) and end comparer (104) meets time-to-digit converter TDC (105) are converted into the processing of data input processor by time-to-digit converter TDC (105) with time quantum.
Voltage buffer (106) is followed the NMOS pipe that is connected by error amplifier EA with the source and is constituted; Reference voltage V
REFThe positive pole of put-into error amplifier EA input end, the output terminal of error amplifier EA connects the grid of NMOS pipe, the source electrode of NMOS pipe inserts inductive reactance (101) with after the negative pole of error amplifier EA input end is connected, and the drain electrode of NMOS pipe inserts the input end of current mirror (107).
When inductance capacitance (102) pin reaches nominal level V
STAThe time, initial comparer (103) upset, time-to-digit converter TDC (105) picks up counting; When inductance capacitance (102) pin reaches a higher nominal level V
ENDThe time, finishing comparer (104) upset, time-to-digit converter TDC (105) finishes timing, and this time interval is converted into data and gives processor processing.
Inductive reactance Rs both end voltage is V
REF-V
PR, twice turnover voltage on the inductance capacitance Cs is V
STA-V
PCAnd V
END-V
PCFor ease of explanation, only consider the equal ground connection of the other end of inductive reactance Rs and inductance capacitance Cs, i.e. V
PR=V
PC=0.
Q＝IT＝VC
T＝(V
END-V
STA)Cs/I
2
I
2＝mI
1＝mV
REF/Rs
T＝RsCs*(V
END-V
STA)/mV
REF
Wherein m is the mirror image coefficient of current mirror, reference voltage V
END, V
STAAnd V
REFProduce by a reference voltage dividing potential drop, so (V
END-V
STA)/mV
REFBe constant, establishing this constant is β.
T＝βRsCs
If V
PR, V
PC≠ 0
T＝RsCs*(V
END-V
STA)/m(V
REF-V
PR)
As long as V
END, V
STA, V
PRAnd V
REFProduced by same benchmark, the equivalence of also can cancelling out each other becomes constant.
If inductive reactance Rs is constant, then inductance capacitance Cs changes delta C=T/ β Rs regulates the induction precision that inductive reactance Rs can regulate inductance capacitance Cs.
If inductance capacitance Cs is constant, then inductive reactance Rs changes delta R=T/ β Cs regulates the induction precision that inductance capacitance Cs can regulate inductive reactance Rs.
Inductive reactance (101) is by non-essential resistance pin R
PADBe connected with voltage buffer (106), other end PR connects outside level; Inductance capacitance (102) is by external capacitive pin C
PADBe connected with the input end that finishes comparer (104) with the input end of the output terminal of current mirror (107), initial comparer (103), other end PC connects outside level.
The PR end of inductive reactance (101) can be that any one is lower than reference voltage V
REFVoltage, the PC of inductance capacitance (102) end can be that any one is lower than reference voltage V
STAVoltage; The PR end of normal conditions inductive reactance (101) and the PC end of inductance capacitance (102) can ground connection.
As shown in Figure 2, for the interference on the isolating exterior power supply, provide three road reference voltage V
REF, V
STA, V
END, reference voltage V
STAInsert the negative pole of initial comparer (103) input end, reference voltage V
ENDInsert the negative pole that finishes comparer (104) input end, insert a low drop out voltage regurator before at voltage buffer (106), initial comparer (103) and end comparer (104), it is made of reference source BANDGAP, error amplifier, PMOS pipe and divider resistance, reference source BANDGAP inserts the negative pole of amp.in, and the output terminal of error amplifier is connected with the grid of PMOS pipe; External power source VDD inserts the source electrode of PMOS pipe, and the drain electrode of PMOS pipe connects four divider resistances ground connection then successively, produces three reference voltage V between the divider resistance
REF, V
STA, V
END, the reference voltage V in the middle of the positive pole of error amplifier input end inserts
REFEnd.
Band gap reference BANDGAP produces not temperature variant constant voltage.This voltage produces three reference voltage V through the low drop out voltage regurator structure of error amplifier and PMOS pipe formation at the divider resistance place
REF, V
STA, V
ENDV wherein
STAAnd V
ENDChoose in decision inductance capacitance (102) charging process starting potential and the end voltage of time-to-digit converter TDC (105) timing.Current source charges to electric capacity, is being charged to from 0V the supply voltage process, and electric current has and overcharges when initial, the precipitous rising of charging voltage curve meeting, and electric current has decay during end, and the charging voltage curve can rise gently.The target of design is the linear time of rising of metered voltage of trying one's best, and this time data more can linear reaction resistance capacitance change.So V
STAShould be higher than minimum voltage V
PC0.5V about, V
ENDShould be lower than ceiling voltage VDD 0.5V or more.
As shown in Figure 1, current mirror (107) is made of metal-oxide-semiconductor MP1, MP2; The grid of metal-oxide-semiconductor MP1, MP2 is connected to each other, and is connected the input end as current mirror then with the drain electrode of metal-oxide-semiconductor MP1, and the source electrode of metal-oxide-semiconductor MP1, MP2 is connected to each other, and the drain electrode of metal-oxide-semiconductor MP2 is as the output terminal of current mirror.
Above-mentioned current mirror (107) is a kind of easy current mirror, and the unequal electric current that will cause of the drain terminal voltage of metal-oxide-semiconductor MP1 and MP2 can be not proportional by mirror image; In order to overcome the existing problem of common current mirror, the invention provides the common-source common-gate current mirror of another kind of resistance self-bias, good PSRR (supply-voltage rejection ratio) and mirror-image property are arranged, it is made of metal-oxide-semiconductor MP1, MP2, MP3, MP4 and resistance R a; The source electrode of metal-oxide-semiconductor MP1, MP2 is connected to each other, the drain electrode of metal-oxide-semiconductor MP1, MP2 is connected with the source electrode of metal-oxide-semiconductor MP3, MP4 respectively, the grid of metal-oxide-semiconductor MP1, MP2 is connected to each other, be connected with resistance R a with the drain electrode of metal-oxide-semiconductor MP3 respectively then, the grid of metal-oxide-semiconductor MP3, MP4 is connected to each other, and then be connected with the other end of resistance R a, as the input end of current mirror, the drain electrode of metal-oxide-semiconductor MP4 is as the output terminal of current mirror.
Described current mirror (107) also can be drain terminal follow current mirror, and it is made of metal-oxide-semiconductor MP1, MP2, MP3 and error amplifier EA; The source electrode of metal-oxide-semiconductor MP1, MP2 is connected to each other, the drain electrode of metal-oxide-semiconductor MP1 connects the negative pole of metal-oxide-semiconductor MP3 source electrode and error amplifier EA input end respectively, the grid of metal-oxide-semiconductor MP1, MP2 is connected to each other, drain electrode with metal-oxide-semiconductor MP3 is connected then, as the input end of current mirror, the grid of metal-oxide-semiconductor MP3 connects the output terminal of error amplifier EA; The drain electrode of metal-oxide-semiconductor MP2 is connected with the positive pole of error amplifier EA input end, as the output terminal of current mirror.The drain terminal voltage of metal-oxide-semiconductor MP2 can be fed back to the drain terminal of metal-oxide-semiconductor MP1 by error amplifier EA and metal-oxide-semiconductor MP3, makes the electric current that flows through metal-oxide-semiconductor MP1, MP2 reach the proportionate relationship of expectation, and weak point is that error amplifier can consume extra power consumption.
Because there is stray capacitance at the chip pin place, PCB layout also can be brought dead resistance electric capacity.In the small capacitance resistance value of metering, need consider these ghost effects so use framework of the present invention.When measuring bigger capacitance resistance value, then need not to consider stray capacitance.
More than show and described ultimate principle of the present invention and principal character and advantage thereof.The technician of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the instructions just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (8)
1, a kind of novel capacitor resistance induction circuit structure is characterized in that, it comprises voltage buffer, current mirror, inductive reactance, inductance capacitance, initial comparer, finishes comparer and time-to-digit converter TDC; Reference voltage inserts the input end of described voltage buffer, the output terminal of voltage buffer connects the input end and the inductive reactance of described current mirror respectively, the output terminal of described current mirror connects the anodal of inductance capacitance, initial comparator input terminal respectively and finishes the positive pole of comparator input terminal, and the output terminal of described initial comparer and end comparer inserts described time-to-digit converter TDC; Reference voltage produces reference current through voltage buffer and inductive reactance, reference current converts charging current to by current mirror inductance capacitance is charged, the pin of inductance capacitance connects initial comparer and finishes the positive pole of comparator input terminal, the STA control pin of the output termination time-to-digit converter TDC of initial comparer, finish the END control pin of the output termination time-to-digit converter TDC of comparer, convert time quantum to the data input processor by time-to-digit converter TDC and handle.
2, circuit framework according to claim 1 is characterized in that: an end of described inductive reactance is connected with described voltage buffer by a non-essential resistance pin, and another termination external electric of described inductive reactance is flat.
3, circuit framework according to claim 1, it is characterized in that: an end of described inductance capacitance is connected with the anodal and positive pole that finishes comparator input terminal of the output terminal of described current mirror, initial comparator input terminal by an external capacitive pin, and another termination external electric of described inductance capacitance is flat.
4, circuit framework according to claim 1 is characterized in that: described voltage buffer is followed the NMOS pipe that is connected by an error amplifier and a source and is constituted; The positive pole of described reference voltage put-into error amp.in, the output terminal of error amplifier connects the grid of NMOS pipe, the source electrode of NMOS pipe inserts described inductive reactance with after the negative pole of error amplifier input end is connected, and the drain electrode of described NMOS pipe inserts the input end of described current mirror.
5, circuit framework according to claim 1, it is characterized in that: insert a low drop out voltage regurator at described voltage buffer, initial comparer with before finishing comparer, it is made of reference source, error amplifier, PMOS pipe and divider resistance, described reference source inserts the negative pole of amp.in, and the output terminal of error amplifier is connected with the grid of PMOS pipe; External power source inserts the source electrode of PMOS pipe, and the drain electrode of PMOS pipe connects four divider resistances ground connection then successively, produces three reference voltages between the divider resistance, the reference voltage end in the middle of the positive pole of error amplifier input end inserts.
6, circuit framework according to claim 1 is characterized in that: described current mirror is made of metal-oxide-semiconductor MP1, MP2; The grid of metal-oxide-semiconductor MP1, MP2 is connected to each other, and is connected the input end as current mirror then with the drain electrode of metal-oxide-semiconductor MP1, and the source electrode of metal-oxide-semiconductor MP1, MP2 is connected to each other, and the drain electrode of metal-oxide-semiconductor MP2 is as the output terminal of current mirror.
7, circuit framework according to claim 1 is characterized in that: described current mirror is made of metal-oxide-semiconductor MP1, MP2, MP3, MP4 and resistance R a; The source electrode of metal-oxide-semiconductor MP1, MP2 is connected to each other, the drain electrode of metal-oxide-semiconductor MP1, MP2 is connected with the source electrode of metal-oxide-semiconductor MP3, MP4 respectively, the grid of metal-oxide-semiconductor MP1, MP2 is connected to each other, be connected with the drain electrode of metal-oxide-semiconductor MP3 and the end of resistance R a respectively then, the grid of metal-oxide-semiconductor MP3, MP4 is connected to each other, and then be connected with the other end of resistance R a, as the input end of current mirror, the drain electrode of metal-oxide-semiconductor MP4 is as the output terminal of current mirror.
8, circuit framework according to claim 1 is characterized in that: current mirror is made of metal-oxide-semiconductor MP1, MP2, MP3 and error amplifier EA; The source electrode of metal-oxide-semiconductor MP1, MP2 is connected to each other, the drain electrode of metal-oxide-semiconductor MP1 connects the negative pole of metal-oxide-semiconductor MP3 source electrode and error amplifier EA input end respectively, the grid of metal-oxide-semiconductor MP1, MP2 is connected to each other, drain electrode with metal-oxide-semiconductor MP3 is connected then, as the input end of current mirror, the grid of metal-oxide-semiconductor MP3 connects the output terminal of error amplifier EA; The drain electrode of metal-oxide-semiconductor MP2 is connected with the positive pole of error amplifier EA input end, as the output terminal of current mirror.
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| CNB2007100379785A CN100516779C (en) | 2007-03-12 | 2007-03-12 | Capacitance resistance induction circuit structure |
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|---|---|---|---|
| CNB2007100379785A CN100516779C (en) | 2007-03-12 | 2007-03-12 | Capacitance resistance induction circuit structure |
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| CN102253286A (en) * | 2011-06-27 | 2011-11-23 | 郑军 | Resistance/capacitance measuring method and device thereof |
| CN109945899B (en) * | 2019-03-22 | 2021-01-26 | 重庆邮电大学 | Detection coding circuit applied to process angle compensation of output buffer |
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Non-Patent Citations (2)
| Title |
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| 电阻式触摸屏实现人机接口. Rick，Downs.电子产品世界，第11期. 2006 |
| 电阻式触摸屏实现人机接口. Rick，Downs.电子产品世界，第11期. 2006 * |
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