CN100514585C - Wafer construction structure with the inductance and its construction method - Google Patents
Wafer construction structure with the inductance and its construction method Download PDFInfo
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- CN100514585C CN100514585C CNB2006100722215A CN200610072221A CN100514585C CN 100514585 C CN100514585 C CN 100514585C CN B2006100722215 A CNB2006100722215 A CN B2006100722215A CN 200610072221 A CN200610072221 A CN 200610072221A CN 100514585 C CN100514585 C CN 100514585C
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 11
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- 238000004806 packaging method and process Methods 0.000 abstract 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Abstract
The invention discloses a wafer packaging structure having an inductor and a packaging method thereof. Firstly the inductor, wires distributing and via holes producing are completed on a substrate to connect the inductor and a wafer substrate, then the substrate with an inductor structure is jointed with the wafer substrate by a connection pad, so that the inductor and the wafer substrate separate an air medium, inductance dissipation loss is reduced, thus, an inductor with a high quality coefficient can be integrated on a wafer substrate having active members and(or) passive members.
Description
Technical field
The present invention relates to a kind of assembling structure and construction method thereof, relate in particular to a kind of wafer scale assembling structure and construction method thereof with inductance.
Background technology
Inductor (Inductor) is a kind of of passive component, is commonly called as coil.Inductor is with lead coiled coiled type, and the element with inductive nature borrows coil current to change, to produce magnetic flux change.Usually have only the plain conductor coiled, have self-induction action, with one with the upper conductor coiling, the mutual inductance effect is then arranged.The major function of inductor is to prevent electromagnetic interference, and electromagnetic radiation is covered, the noise in the filter current.Have wide range of applications, comprise power supply unit, monitor, switch, motherboard, scanner, telephone set, modulator-demodulator etc.
In addition, in wireless communications products, need the element of small-sized, economic and high degree of integration, on semiconductor substrate, be integrated into inductance to reach the purpose that reduces production costs mostly at present.(RadioFrequency, RF) inductance is widely used in the radio-frequency module of radio communication radio frequency, and is when carrier frequency constantly promotes, also urgent more for the demand of high-quality coefficient (quality factor) inductance.
The greatest problem of integrated inductor is that the quality of inductance is good inadequately usually on semiconductor substrate.Because coil can produce the phenomenon of impedance consume in metallized process, add the impedance of semiconductor-based flaggy and the electric capacity that is coupled to substrate, make the inductance usefulness on the semiconductor and the usefulness of ideal inductance element that sizable drop be arranged.The quality of assessment inductance usefulness is assessed with quality coefficient usually, in order to reduce the wastage and to obtain best quality coefficient, simultaneously again can conjunction with semiconductors technology, and inductance coil must be selected the lower metal of loss.In addition, for the loss of the eddy current (eddy current) that reduces semiconductor-based flaggy, and reduce the electric capacity that is coupled to substrate, the coil metal layer can be far away more good more from substrate layer.
Therefore, in order to promote the inductance quality coefficient, in No. 5844299 patent case of the U.S., disclose a kind of integration type inductance, its manufacture method is elder generation's etching depression on substrate, deposition of dielectric materials group in depression again, then form dielectric layer above dielectric material group, on dielectric layer, form conductive coil at last.Utilize isolated coil body of dielectric material group and dielectric layer and substrate, so can reduce the ghost effect and the energy loss of substrate.In addition, disclose a kind of integration type inductance with three-dimensional structure coil in No. 6008102 patent case of the U.S., its production method is the loop construction that forms solid through the mode type of little shadow, etching and deposit metallic material repeatedly.Inductance coupling high effect between three-dimensional coil can suppress magnetic field and keep the effect of hanging down reactance and reaching self-shileding (Self shielding), promotes the inductance quality coefficient.
In addition, can utilize etched mode to hollow out several parts of substrate, only prop up inductance, to reduce the energy loss that causes by substrate with the minority support.For example disclose a kind of integrated circuit inductance in No. 6495903 patent case of the U.S., this inductance has the spiral type aluminum coil on the oxide layer that is deposited on silicon substrate.This silicon substrate etching is free channeling, and the air ditch provides the medium of low-k below coil.Electric capacity that can reduce the impedance of silica-based flaggy and be coupled to silicon substrate like this.But the manufacture method of this inductance needs behind the plated metal coil again, and etching air ditch utilizes oxide layer to provide and builds bridge the support metal coil below wire coil, and the etching step of its process is comparatively complicated.In addition, in No. 6835631 patent case of the U.S., disclose a kind of inductance manufacture method that promotes the inductance quality coefficient, the method is to form first oxide layer earlier on substrate, forms low-dielectric constant layer again on first oxide layer, then forms second oxide layer on low-dielectric constant layer.Next step forms air compartment (air gap) for etching second oxide layer and low-dielectric constant layer, forms the top low-dielectric constant layer again, forms inductance in the last top low-dielectric constant layer above air compartment.This manufacture method also is to utilize etching step to form air compartment to promote the inductance quality coefficient.
Comprehensive above-mentioned institute says, is integrated in the inductance of semiconductor substrate because the impedance of substrate and the electric capacity that is coupled to substrate make the inductance quality descend.Therefore for making inductance coil and substrate at interval to lower above-mentioned interference, need provide air dielectric between the two, present method all is to utilize etch process that air ditch or air compartment are provided, and makes technology comparatively complicated, and yield is difficult for promoting.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of wafer scale assembling structure and construction method thereof with inductance.On substrate, finish earlier inductance, arrangement of conductors and make through hole to link inductance and wafer substrate is carried out contraposition with wafer substrate by connection gasket with the substrate of tool inductance again and is engaged, and makes inductance and wafer substrate interval air dielectric, reduce the inductance scattering, promote the inductance quality coefficient.Therefore utilize inductance that the present invention can integrate the high-quality coefficient in have active element and (or) on the wafer substrate of passive component.
The disclosed wafer scale construction method with inductance of the present invention includes following step.First substrate is provided earlier.Then form second substrate, this second substrate has a plurality of inductance.Engage first substrate and second substrate by a plurality of connection gaskets at last, therefore allow have the gap between first substrate and second substrate, each connection gasket is in order to be electrically connected to first substrate with each inductance.Can also cut first substrate and second substrate afterwards, to form a plurality of chip-scale assembling structures with inductance.Wherein first substrate can be have active element and (or) silicon substrate of passive component.
The step that wherein forms second substrate comprises as follows.One dielectric layer is provided earlier, and the first surface of this dielectric layer is formed with the first metal layer, and the second surface of dielectric layer is formed with second metal level.Follow the etching the first metal layer and second metal level, in order to coil and a plurality of plain conductor that forms each inductance.Form a plurality of through holes again in dielectric layer, form a plurality of metal conduction bodies then in each through hole, each metal conduction body and function is to connect the first metal layer and second metal level.Then form first insulating barrier and second insulating barrier, wherein first insulating barrier covers the first metal layer, and second insulating barrier covers second metal level.Final etch first insulating barrier and second insulating barrier are in order to expose a plurality of contacts of plain conductor.
In addition, the wafer scale assembling structure with inductance of the present invention includes first substrate; A plurality of connection gaskets are positioned on first substrate; And second substrate, being positioned on each connection gasket, this second substrate has a plurality of inductance, and each connection gasket has the gap in order to each inductance is electrically connected to first substrate between first substrate and second substrate.And first substrate also have active element and (or) passive component.
Wherein second substrate includes dielectric layer; The first metal layer is positioned at the first surface of dielectric layer, and this first metal layer includes inductance; Second metal level is positioned at the second surface of dielectric layer; A plurality of metal conduction bodies are arranged in a plurality of through holes of dielectric layer, and each metal conduction body and function is to connect the first metal layer and second metal level; First insulating barrier is positioned on the first metal layer; And second insulating barrier, be positioned on second metal level.This second substrate also comprises a plurality of tin balls (solder bump), and each tin ball is positioned on the first metal layer.When cutting first substrate and second substrate, then form a plurality of chip-scale assembling structures with inductance.
Construction method of the present invention is to form inductance on second substrate, therefore, can utilize the thickness that increases dielectric layer, and the inductance value of three-dimensional solenoid type (Solenoid) design is increased.But the passive component of assembling structure integrated inductor of the present invention in have active element and (or) on first substrate of passive component, do not need etching in addition and form the air gap, can reduce the loss and the waste of base material, the electric capacity that the air gap of formation after connection gasket is fitted can be reduced the resistance of first substrate and is coupled to first substrate with first substrate and second substrate is so as to increasing the inductance quality coefficient.Utilize the method need can not avoid element impaired, and improve and make yield by complicated etching step because of etching process.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the assembling structure figure of the first embodiment of the present invention;
Fig. 2 A to Fig. 2 G is the construction method schematic diagram of the first embodiment of the present invention; And
Fig. 3 is second embodiment of the present invention figure.
Wherein, Reference numeral:
10,100: the first substrates 11,110: silicon substrate
12: insulation layer 13: conduction region
20,200: the second substrates 21,210: dielectric layer
22,220: the first metal layer 22a, 220a: inductance
23,230: the second metal levels 24: metal conduction body
25,250: the first insulating barriers 26,260: the second insulating barriers
27,270: tin ball 30,300: connection gasket
40: 0: the first insulation layer of carrier 12
140: the first metal conduction bodies of 130: the first conduction regions
160: the second conduction regions of 150: the second insulation layers
240: the second metal conduction bodies
Embodiment
For making purpose of the present invention, structure, feature and function thereof there are further understanding, cooperate embodiment to be described in detail as follows now.Above about content of the present invention explanation and the explanation of following execution mode in order to demonstration with explain principle of the present invention, and provide patent claim of the present invention further to explain.
Fig. 1 is the chip-scale assembling structure with inductance of the first embodiment of the present invention.Its structure includes first substrate 10 as shown in FIG.; A plurality of connection gaskets 30 are positioned on first substrate 10; And second substrate 20, be positioned on each connection gasket 30, second substrate, 20 tool inductance 22a, each connection gasket 30 has the gap in order to inductance 22a is electrically connected to first substrate, 10, the first substrates 10 and 20 of second substrates.Also have on the surface that first substrate 10 and connection gasket 30 join active element and (or) electronic component such as passive component (not shown).
Wherein second substrate 20 includes dielectric layer 21; The first metal layer 22 is positioned at the first surface (position as shown in FIG.) of dielectric layer 21, and the first metal layer 22 includes inductance 22a; Second metal level 23 is positioned at the second surface (position as shown in FIG.) of dielectric layer 21; A plurality of metal conduction bodies 24 are positioned at a plurality of through holes (position of metal conduction body 24 as shown in FIG.) of dielectric layer 21, and each metal conduction body 24 is in order to connect the first metal layer 22 and second metal level 23; First insulating barrier 25 is positioned on the first metal layer 22; And second insulating barrier 26, be positioned on second metal level 23.This second substrate 20 also comprises a plurality of tin balls 27, and each tin ball 27 is positioned on the first metal layer 22.
Next described the wafer scale construction method of first embodiment since Fig. 2 A to Fig. 2 G in detail with inductance.Shown in Fig. 2 A, provide first substrate 10 earlier.First substrate 10 comprises silicon substrate 11, a plurality of insulation layer 12 and a plurality of conduction regions 13.The passivation layer (passivation layer) that insulation layer 12 forms for silicon substrate 11 oxidations or other insulating material forms.Conduction region 13 is the metal line on the silicon substrate 11, is formed through steps such as deposition, little shadow and etchings by metal material.First substrate 10 can be formed with active element and (or) electronic component such as passive component (not shown), wherein conduction region 13 electrically connect active elements and (or) the passive component (not shown).First substrate 10 can pass through wafer thinning technology (WaferThinning) earlier, lowers the thickness of first substrate 10.
Fig. 2 B to Fig. 2 D describes the step that forms second substrate in detail.Shown in Fig. 2 B, dielectric layer 21 is provided earlier, the first surface of this dielectric layer 21 (position as shown in FIG.) is formed with the first metal layer 22, and the second surface of dielectric layer 21 (position as shown in FIG.) is formed with second metal level 23.Dielectric layer 21 is soft flexible substrate, for example is polyimides (Polyimide) base material or polyester (Polyester) base material.Then shown in Fig. 2 C, the etching the first metal layer 22 and second metal level 23 are in order to coil and a plurality of plain conductor (distributing position as shown in FIG.) that forms each inductance 22a.And utilize modes such as machine drilling, laser or etching to form a plurality of through holes (position of metal conduction body 24 as shown in FIG.) in dielectric layer 21, deposit metallic material is in through hole then, form a plurality of metal conduction bodies 24 in each through hole, each metal conduction body 24 connects the first metal layer 22 and second metal level 23.Therefore have inductance 22a, the heavily plain conductor (with reference to icon) after distributing and the metal conduction body 24 that links the inductance 22a and second metal level 23 on second substrate.The thickness increase of dielectric layer 21 can make the inductance value of the inductance 22a of three-dimensional solenoid type increase.Next shown in Fig. 2 D, form first insulating barrier 25 and second insulating barrier 26, wherein first insulating barrier 25 covers the first metal layer 22, and second insulating barrier 26 covers second metal level 23.The method that forms first insulating barrier 25 and second insulating barrier 26 can be the steam coating silicon dioxide layer on the first metal layer 22 and second metal level 23; or being coated with organic membrane on the first metal layer 22 and second metal level 23, first insulating barrier 25 and second insulating barrier 26 are as the passivation layer with insulation and protective effect.Final etch first insulating barrier 25 and second insulating barrier 26 are in order to expose the first metal layer 22 and second metal level 23 as plain conductor a plurality of contacts (with reference to icon) partly.
Then shown in Fig. 2 E, engage first substrate 10 and second substrate 20 by a plurality of connection gaskets 30, therefore allow first substrate 10 and 20 of second substrates have the gap, each connection gasket 30 is in order to be electrically connected to first substrate 10 with each inductance 22a (with reference to the position shown in Fig. 2 D).With metal material (or electric conducting material) be deposited on earlier conduction region 13 or (with) on the contact (with reference to icon) that exposes of second metal level 23, utilize modes such as hot pressing, eutectic welding, conducting particles or conduction tube bank to engage again, formation connection gasket 30 is between the contact that conduction region 13 and second metal level 23 expose.When carrying out the contraposition joint,, utilize carrier 40 that the correspondence position that second substrate 20 is positioned on first substrate 10 is carried out hot pressing more earlier with carrier 40 absorption second substrate 20.Carrier 40 is transparent rigid material, can provide first substrate 10 hardness, makes things convenient for contraposition to engage.Engaged the removable carrier 40 in back.Because each connection gasket 30 is interval in 20 of first substrate 10 and second substrates, make and produce the space between the two, the air dielectric of low-k is provided, can reduces the resistance of first substrate 10 and the electric capacity that inductance 22a is coupled to first substrate 10, promote the quality coefficient of inductance 22a.So far the making of step with wafer scale assembling structure of inductance finished.
In addition, shown in Fig. 2 F, can form a plurality of tin balls 27 on the first metal layer 22, for the usefulness of follow-up chip bonding.Because dielectric layer 21 has pliability, and the preferable stress buffer of contact of tin ball 27 can be provided, help the contact reliability that crystalline substance or the assembling of wafer scale joint are covered in subsequent module or system.
Shown in Fig. 2 G, cut first substrate 10 and second substrate 20 at last, to form a plurality of chip-scale assembling structures (as shown in Figure 1) with inductance.First substrate 10 can avoid inductance 22a impaired in thinning technology earlier through engaging with second substrate 20 after the wafer thinning technology again.Size with chip-scale assembling structure of inductance is dwindled because of thinning first substrate 10, and has air dielectric can promote the inductance quality coefficient at interval because of inductance 22a and first substrate 10.The existence of dielectric layer 21 can be dwindled the area coil of inductance 22a, reduces the magnetic field coupling effect, promotes the electrical effect of passive component.And form the air gap through laminating type and can avoid complicated etching step, improve and integrate yield.
In addition, Fig. 3 is with the explanation second embodiment of the present invention.The chip-scale assembling structure with inductance of second embodiment includes first substrate 100 as shown in FIG.; A plurality of connection gaskets 300 are positioned on first substrate 100; And second substrate 200, be positioned on each connection gasket 300, second substrate, 200 tool inductance 220a, each connection gasket 300 has the gap in order to inductance 220a is electrically connected to first substrate, 100, the first substrates 100 and 200 of second substrates.First substrate 100 also have active element and (or) the passive component (not shown).
First substrate 100 includes silicon substrate 110, a plurality of first insulation layer 120, a plurality of first conduction region 130, a plurality of second insulation layer 150, a plurality of second conduction region 160, and a plurality of first metal conduction body 140.First insulation layer 120 and first conduction region 130 are positioned at the first surface (position as shown in FIG.) of silicon substrate 110, and second insulation layer 150 and second conduction region 160, are positioned at the second surface (position as shown in FIG.) of silicon substrate 110.The formation method of the first metal conduction body 140 can be with reference to the formation method of metal conduction body 24 among the 1st embodiment, and the first metal conduction body 140 can electrically connect first conduction region 130 and second conduction region 160.In addition, the second surface of silicon substrate 110 have wiring, active element and (or) passive component, be the active face (active side) of silicon substrate 110.Wherein second conduction region 160 electrically connect active elements and (or) the passive component (not shown).Because each connection gasket 300 is interval between each the 1st conduction region 130 and second metal level 230, make to form conductive path by the first metal layer 220 (comprising inductance 220a), the second metal conduction body 240, second metal level 230, connection gasket the 300, the 1st conduction region 130, the first metal conduction body, 140 to second conduction regions 160.
About the wafer scale construction method of second embodiment with inductance, and the wafer scale assembling structure that will have an inductance cut into a plurality of methods with chip-scale assembling structure of inductance can be with reference to the explanation of first embodiment.In a second embodiment, utilize construction method of the present invention, can engage have inductance 220a second substrate 200 in first conduction region 130 of the first surface of silicon substrate 110, by the first metal conduction body 140 second conduction region 160 of the second surface (active face) of inductance 220a and silicon substrate 110 is electrically connected again.Therefore can form the two-sided wafer scale assembling structure that conductive connection pads is all arranged of silicon substrate 110.
Owing to be subject to the size of passive component (as inductance, electric capacity and resistance), high frequency, radio frequency and mixed signal circuit block can't dwindle with characteristic size evolution as the piece of digital block at present.The connecting line between the consideration circuit and the transmission of signal except the resistance or capacity effect considered, also will be considered the effect of inductance in the past in high-frequency circuit.In addition, when integration more height, the noise that is coupled in the integrated circuit is just big more to the influence of circuit.For high-frequency signal, the impedance step-down of electric capacity, signal just propagates into other circuit by semiconductor substrate easily.High frequency or radio circuit are because used many passive components such as inductance at present, and the density of metal level is difficult to reach the requirement of semiconductor factory.Inductance construction method of the present invention can be applicable on the wireless transport module, directly on semiconductor substrate, do not make inductance, and in the mode of fitting inductance is combined on the semiconductor substrate, can avoid that metal level density is too high, the noise of reduction and substrate coupling, dwindle the passive component area, promote the electrical effect of passive component and improve the integration yield.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (15)
1. the wafer scale construction method with inductance is characterized in that, includes following step:
One first substrate is provided;
Form one second substrate, this second substrate has a plurality of inductance; And
Engage this first substrate and this second substrate by a plurality of connection gaskets, so that have the gap between this first substrate and this second substrate, respectively this connection gasket is in order to being electrically connected to this inductance this first substrate,
Wherein, the step that forms this second substrate includes:
One dielectric layer is provided, and the first surface of this dielectric layer is formed with a first metal layer, and the second surface of this dielectric layer is formed with one second metal level;
This first metal layer of etching and this second metal level are in order to form respectively this inductance and a plurality of plain conductor;
Form a plurality of through holes in this dielectric layer;
Form a plurality of metal conduction bodies in this through hole respectively, respectively this metal conduction body and function is to connect this first metal layer and this second metal level;
Form one first insulating barrier and one second insulating barrier, wherein this first insulating barrier covers this first metal layer, and this second insulating barrier covers this second metal level; And
This first insulating barrier of etching and this second insulating barrier are in order to expose a plurality of contacts of this plain conductor.
2. the wafer scale construction method with inductance according to claim 1 is characterized in that, also comprises this first substrate of cutting and this second substrate, to form a plurality of chip-scale assembling structures with inductance.
3. the wafer scale construction method with inductance according to claim 2 is characterized in that, also comprises: respectively this chip-scale structure installing places a wireless transport module.
4. the wafer scale construction method with inductance according to claim 1 is characterized in that, also comprises forming a plurality of tin balls on this first metal layer.
5. the wafer scale construction method with inductance according to claim 1 is characterized in that this dielectric layer is a flexible substrate.
6. the wafer scale construction method with inductance according to claim 1 is characterized in that, also comprises: form a plurality of electronic components in this first substrate, respectively this inductance is by respectively this connection gasket and respectively this electronic component electric connection.
7. the wafer scale construction method with inductance according to claim 1 is characterized in that this first substrate has a first surface and a second surface, and this first surface joins with this connection gasket respectively, and this wafer scale construction method with inductance also comprises:
Form a plurality of electronic components in this second surface; And
Form a plurality of metal conduction bodies that penetrate this first substrate, respectively this metal conduction body electrically connects respectively this connection gasket of this first surface and respectively this electronic component of this second surface.
8. the wafer scale assembling structure with inductance is characterized in that, includes:
One first substrate;
A plurality of connection gaskets are positioned on this first substrate; And
One second substrate is positioned at respectively on this connection gasket, and this second substrate includes: a dielectric layer; One the first metal layer is positioned at the first surface of this dielectric layer, and this first metal layer includes this inductance; One second metal level is positioned at the second surface of this dielectric layer; A plurality of metal conduction bodies are arranged in a plurality of through holes of this dielectric layer, and respectively this metal conduction body and function is to connect this first metal layer and this second metal level; One first insulating barrier is positioned on this first metal layer; And one second insulating barrier, be positioned on this second metal level;
Wherein, respectively this connection gasket and second metal level join, and in order to this inductance is electrically connected to this first substrate, have the gap between this first substrate and this second substrate.
9. the wafer scale assembling structure with inductance according to claim 8 is characterized in that, also comprises a plurality of tin balls, is disposed on this first metal layer.
10. the wafer scale assembling structure with inductance according to claim 8 is characterized in that this dielectric layer is a flexible substrate.
11. the wafer scale assembling structure with inductance according to claim 10 is characterized in that this flexible substrate includes a polyimide base material or a polyester base material.
12. the wafer scale assembling structure with inductance according to claim 8 is characterized in that this first substrate also comprises a plurality of electronic components, respectively this inductance is by respectively this connection gasket and respectively this electronic component electric connection.
13. the wafer scale assembling structure with inductance according to claim 8 is characterized in that, this first substrate includes:
One first surface, this first surface joins with this connection gasket respectively;
One second surface, this second surface has a plurality of electronic components; And
A plurality of metal conduction bodies that penetrate this first substrate, respectively this metal conduction body electrically connects respectively this connection gasket of this first surface and respectively this electronic component of this second surface.
14. the wafer scale assembling structure with inductance according to claim 8 is characterized in that this wafer scale assembling structure also can form a plurality of chip-scale assembling structures through cutting.
15. the wafer scale assembling structure with inductance according to claim 14 is characterized in that, respectively this chip-scale assembling structure inductance element that is a wireless transport module.
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| CNB2006100722215A CN100514585C (en) | 2006-04-12 | 2006-04-12 | Wafer construction structure with the inductance and its construction method |
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|---|---|---|---|---|
| CN101471468B (en) * | 2007-12-27 | 2012-11-07 | 财团法人工业技术研究院 | Surface-shaped inductance coupling structure |
| JP6060872B2 (en) * | 2013-11-05 | 2017-01-18 | 日立金属株式会社 | Transmission module mounting structure |
-
2006
- 2006-04-12 CN CNB2006100722215A patent/CN100514585C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN101055844A (en) | 2007-10-17 |
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