CN100511978C - Transconductance amplifier, analog-to-digital converter and operating method thereof, and current generation method - Google Patents

Abstract

The present invention relates to transconductance amplifiers, in which the output current is related to the difference between two input voltages, and to the use of such transconductance amplifiers in analog-to-digital converters. The differential amplifier (300) is configured to provide an output current related to a difference between a first input voltage (302) and a second input voltage (304). The differential amplifier includes an input sampling capacitor (318) coupled to a first conductor of the input sampling capacitor; a current output (314) for generating the output current; and input switches (308, 310) for for selectively coupling a second conductor of the input sampling capacitor to a first input of the differential amplifier for receiving the first input voltage and to a second input of the differential amplifier for receiving the first Two input voltages. The differential amplifier is configured to couple the second conductor to one of the first and second inputs and apply a voltage to the first conductor in a first state, and to couple the second conductor to the first conductor in a second state. The second conductor is coupled to the other of the first and second inputs to provide a voltage change to the transconductance amplifier input based on the difference between the first and second input voltages.

Description

Differential amplifier, analog-to-digital converter and method of operation thereof, current generating method

technical field

The present invention relates generally to transconductance amplifiers, ie, amplifiers that generate an output current in response to an input voltage, and to analog-to-digital converters (ADCs) employing such amplifiers. More specifically, the present invention relates to transconductance amplifiers in which the output current depends on the difference between two input voltages, and to applications thereof.

Background technique

In many ADC designs, an analog input voltage is compared to a reference voltage (or multiple reference voltages) to produce a voltage output that can be used to generate a digital output code. Exemplary voltage comparators are described in US 6,150,851, US 6,356,148, US 6,249,181 and DRBeck and DJ Allstot, "An 8-bit, 1.8V, High Speed Analogue-to-digital Converter" ( http://students.washington.edu/ beckdo/Dapers/techcon2000.doc ) and P. Setty, J. Barner, J. Plany, H. Burger, and J. Sonntag, "A5.75b 350MSamples/S or 6.75b150MSamples/S reconfigurable/ADC for a PRML Read Channel" , Session 9 IEEE International Solid-State Circuit Conference 5-7 Feb. 1998 (ISSCC98). Sample and hold (S/H) circuits for ADCs are also known, as in US 6,169,427 and US 5,963,156 and N. Waltari and K. Halonen, "1.0-Volt, 9-bit Pipeline CMOS ADC", 26 ^th European As described in Solid-State Circuit Conference Stockholm, Sweden 19-21 September 2002, they both use conventional (voltage output) op amps with switched capacitor feedback. Also known are successive approximate register (SAR) analog-to-digital converters (see for example JLMcCreary and P Gray, IEEE JSSC SC-10, pp. 371-9, Dec 1975), which compare analog inputs to digital-to-analog converters (DAC) output, the DAC can employ a binary-weighted capacitor array to generate an analog output voltage using charge redistribution between the capacitors.

[3] The analog-to-digital converter described above uses voltage comparisons to generate a digital output. It will be appreciated that when comparing an input voltage to a reference voltage, only gain and not linearity is important, since it is only necessary to know whether the input is above or below the reference. However, it is also known to simplify ADC circuits by summing the currents produced by interpolating between reference voltages, and for this interpolated summation linearity is an important requirement. Interpolating ADCs are often used in low resolution high or medium speed applications. Figure 1 shows a general circuit diagram of an example stage of a current mode interpolating ADC. An example of an ADC with current-mode interpolation is described in M.P. Flynn and D.J. Alstot, "CMOS Folding A/DC Converters with Current-Mode Interpolation", IEEE JSSC vol.31, September 1996, pp. 1248-1257; M.P. Flynn and B. Sheahan , "A 400MSample/S, 6-bCMOS Folding and Interpolating ADC" IEEE JSSC, vol.33, December 1998, pp. 1932-1938; B-S Song, P.L.Rakers and S.F.Gilling, "A 1V, 6-b50MSamples/S Current Interpolating CMOS ADC", IEEE J. Solid-State Circuits, vol. 35, April 2000, pp. 647-651.

[4] Referring to Figure 1a, the general principle is to generate from a smaller set of reference voltages (two in Figure 1, VrefA and VrefB) by interpolating between outputs from a set of amplifiers (two in Figure 1) A plurality of comparison levels (five in Figure 1), each of said outputs representing the difference between the input signal and one of the references.

[5] In the interpolation stage 100 of FIG. 1a, the input voltage on line 102 is supplied to one input of a first 104 and a second 106 differential transconductance amplifier. A second input to first transconductance amplifier 104 is provided by a first reference voltage VrefA on line 108 and a second input to transconductance amplifier 106 is provided by a second reference voltage VrefB on line 110 . Each differential transconductance amplifier produces an output current proportional to the difference between the voltages on its two inputs, the ratio of the output current to the input voltage difference is called the transconductance. Amplifiers 104 and 106 are drawn as current sinking, but preferably their output currents can be of positive or negative polarity depending on the polarity of Vin-VrefA and Vin-VrefB, respectively.

[6] FIG. 1 b illustrates one possible implementation of transconductance amplifier 130 suitable for use with transconductance amplifiers 104 and 106 . The transconductance amplifier includes a pair of input transistors 132, 134 having inputs from Vin 102 and one of VrefA 108 and VrefB 110, respectively, and a common source connection connected to a constant current sink 136. The drain connections of transistors 132 and 134 are connected to respective input and output connections of a current mirror surrounded by dashed line 138 , and current output connection 140 is taken from the junction of the drain of transistor 134 and the output of current mirror 138 . Each of the transistors 132, 134 passes an incremental current given by its transconductance gm multiplied by the transistor's incremental gate input voltage such that the output current is given by Iout = Gm.(Vin-Vref), where the amplifier The transconductance Gm is equal to gm.

The output current from the transconductance amplifier 104 is input to or drives the first current mirror 112 and the output current from the transconductance amplifier 106 drives the second current mirror 114 . The current mirror 112 includes a plurality of constant current generators 112a-e. The voltage on line 116 sets the current through element 112a to be the same as the output current flowing into differential transconductance amplifier 104 in a conventional manner. This same drive voltage is also provided to elements 112b - e to provide a constant current output on lines 118a - d determined by the output current of transconductance amplifier 104 .

Figure Ic shows an example of a controllable current generator 150 suitable for use in the interpolating ADC stage 100 of Figure Ia. An input transistor 151 and a constant current sink 152 are connected in series between supply lines 154 , 156 , the connection between transistor 151 and current sink 152 providing a current output Iout 158 . The input transistor 151 has a control voltage Vc applied to its gate connection to provide a controlled unipolar current equal to the sum of the output current Iout and the current drawn by the constant current sink 152 . Thus, depending on the magnitude of the controlled unipolar current through input transistor 151, the output current can be of either polarity. For a given input control voltage Vc, the output current (or the output current of a plurality of matched controllable current generators) can be scaled by scaling the dimensions of the input (MOS) transistor 151 . Preferably, the current sink 152 is scaled at the same rate as to maintain a constant "zero current" point. In this way, a plurality of different scaled, matched controllable current generators can be set to have zero output current for substantially the same input control voltage and thereby provide zero output current substantially simultaneously.

Where the transistors comprising elements 112a and 112b are of the same physical size, the current on line 118a is substantially the same as the current through element 112a. The dimensions of the transistors comprising elements 112c, d, e are reduced to 0.75x, 0.5x and 0.25x the dimensions of element 112b such that currents of 0.75x, 0.5x and 0.25x the output current from transconductance amplifier 104 are respectively Provided on lines 118b, 118c and 118d. Typically the current mirror 112 is fabricated on an integrated circuit so that the transistors comprising the current mirror are matched. The current mirror 114 similarly includes elements 114a-e, such as bipolar or FET transistors, and operates in a corresponding manner to provide 1.0x, 0.75x, 0.5x, and 0.25x output current as the transconductance amplifier 106 on lines 120a-d, respectively current.

Current I1 on line 118a is provided to comparator 122a to generate digital output D1. Digital output D2 from comparator 122b is determined by the sum of the currents on lines 118b and 120d; output D3 from comparator 122c is determined by the sum of the currents on lines 118c and 120c; output D4 from comparator 122d is determined by the sum of the currents on lines 118c and 120c; 118d and 120d; and digital output D5 from comparator 122e is determined by the current on line 120a.

Denoting the output current of transconductance amplifier 104 as IA and the output current of transconductance amplifier 106 as _IB , _IA is proportional to the difference between Vin on line 102 and VrefA on line 108, while _IB is The difference between Vin and VrefB on line 110 is proportional. The summed intermediate current is proportional to the fraction of the difference between Vin and VrefA plus the fraction of the difference between Vin and VrefB. Mathematically:

I ₁ =I _A =G(Vin-VrefA)

I ₅ =I _B =G(Vin-VrefB)

I ₂ =0.75G(Vin-VrefA)+0.25G(Vin-VrefB)

Therefore I ₂ ∝Vin-(0.75VrefA+0.25VrefB)

and I ₂ ∝Vin-(3VrefA+VrefB)/4

In other words, these scaled currents produce an output current proportional to the remainder [Vin-Vth(i)]i=1...5, where:

Vth(1)=VrefA,

Vth(2)=(3.VrefA+VrefB)/4,

Vth(3)=(VrefA+VrefB)/2,

Vth(4)=(VrefA+3.VrefB)/4,

Vth(5)=VrefB.

It can be seen that in the case of Vin=Vth, the output current is zero, and for Vin>Vth, the output current is positive, and for Vin<Vth, the output current is negative. Thus, the output currents I1 to I5 will zero-cross when the input voltage is equal to the thresholds Vth(1), ..., N, where N = (2 + number of intermediate values), in this case 5 (ie 2 + 3 ). In the interpolation stage 100 of FIG. 1, the output currents I1 to I5 are applied to high input impedance comparators 122a to 122e, respectively, which make logic decisions at these thresholds. Thus, the signal level of the input voltage Vin between VrefA and VrefB is converted into a digital format output on lines D1 to D5 as a so-called thermometer code. This code is then converted into binary code by conventional means (not shown in Figure 1). This may include, for example, a priority coder, or alternatively, the functionality of the hardware may be specified in a hardware description language, such as Verilog(TM) or VHDL, allowing hardware synthesis tools to transcode functionality with other backend logic , such as error correction logic mixing.

Although only two reference voltages VrefA and VrefB are illustrated in FIG. 1 , more reference voltages can be used for multi (two) bit conversion. The reference voltage is typically derived from a resistor string, and those skilled in the art will appreciate that fewer taps are necessary on such a resistor string than a conventional/analog-to-digital converter, since fewer the reference voltage. Furthermore, the amplification of the residual signal also relieves the requirements on the comparator, and in particular its omitted input offset voltage and overdrive. Typically this saves the need for a pre-amplification stage before each comparator, so the overall circuit is simpler despite the addition of the current mirror and linear transconductance amplifier.

One application of an interpolating ADC is as the second stage of a two-stage analog-to-digital converter, such as the analog-to-digital converter 200 shown in FIG. 2 . In this ADC, an input voltage Vin on line 202 is provided to an M-bit ADC 204 which outputs the M most significant bits (MSBs) of the digitized signal on line 206 . This rough approximation to the input voltage Vin is converted back to an analog voltage by an M-bit digital-to-analog converter (DAC) 208 and subtracted from the original input signal by a subtractor 210 to leave a residual signal on line 212 . This residual signal is provided to an N-bit analog-to-digital converter 214 which produces the N least significant bits on line 216 which are combined with the MSB by appropriate logic in combiner 218 to provide a number having the desired total number of binary bits Output 220. An example of such a two-stage ADC is described in "A 3.3-V, 10-b, 25-MSample/s Two-Step ADC in 0.35-μm CMOS", Hendrik van der Ploeg and Robert Remmers, IEEE Journal of Solid State Circuits, Vol 34, No. 12, December 1999. Coarse and fine level conversion ranges can be overlapped to ease the constraints on the coarse level ADC.

It can be seen by inspection of FIG. 2 that the first stage ADC 204 must first make its decision, and then the output of the DAC 208 and the difference amplifier (difference amplifier) 210 before the second stage comparator associated with the ADC 214 can make its decision. The output must be built. Thus, the first stage must sample its input signal well before the decision time of the second stage. To avoid conversion errors, it has previously been necessary to precede such a two-stage ADC with a sample-and-hold circuit to keep the input constant between two sampling instants. This increases the complexity of the ADC, thereby increasing its cost, and also increases power consumption. It would therefore be desirable to be able to eliminate such sample and hold circuits, especially while maintaining the desired linearity for interpolation-type summation and other linear signal processing.

Contents of the invention

According to a first aspect of the present invention there is thus provided a differential amplifier configured to provide an output current related to the difference between a first input voltage and a second input voltage, the differential amplifier comprising an input sampling capacitor having two conductors; a transconductance amplifier having an input coupled to the first conductor of the input sampling capacitor and a current output adapted to generate the output current; and an input switch for selectively sampling the input a second conductor of the capacitor coupled to a first input of the differential amplifier for receiving the first input voltage and a second input of the differential amplifier for receiving the second input voltage; the differential amplifier is configured to couple the second conductor to one of the first and second inputs and apply a voltage to the first conductor in a first state, and couple the second conductor to The other of said first and second inputs is configured to provide a voltage change to said transconductance amplifier input based on said difference between said first and second input voltages.

Preferably, said output current depends substantially linearly on the difference between the first and second input voltages. This output current may be provided directly from the transconductance amplifier, or the current produced by the transconductance amplifier may be mirrored or used in some other way to provide the output current for the differential amplifier.

The input sampling capacitor allows an input voltage, say the first input voltage, to be sampled in the first state of the differential amplifier to set the charge on the input sampling capacitor. Then, when the second conductor of the input sampling capacitor is connected to another input voltage, say a second input voltage, the voltage difference between the inputs is passed to the input of a transconductance amplifier which provides a current output for direct or indirectly generate the output current from the differential amplifier. A controller can be used to control the sampling process. Assuming that the transconductance amplifier itself is linear, the differential amplifier is also substantially linear.

In operation, the first voltage is sampled onto the input capacitor at the end of the first state, but its value is held and subtracted from the second voltage during the second state. The output current resulting from the difference voltage can be sampled (via a subsequent comparator) at the end of the second state, giving the second voltage additional time to settle. This sample-and-hold action is particularly useful for two-stage ADCs, where the first voltage may be the raw input signal, and the second voltage is a reference voltage selected by a "coarse" ADC that also samples the input signal. Since the second, reference voltage is not needed until the start of the second state, the "coarse" ADC has time to settle, thereby avoiding the need for a separate sample and hold circuit.

In a modification to the differential amplifier, one or more additional input sampling capacitors may be provided. Such additional input sampling capacitors can be switched between two reference voltages, and where multiple differential amplifiers are employed, such as in a two-stage ADC, one of these reference voltages can be common to all differential amplifiers and be used by Another reference voltage applied to each differential amplifier can be tied to a corresponding point in the reference voltage ladder. In this way, the effective operating points of the differential amplifier can be spaced, eg, substantially equidistantly, to provide two or more output currents, which can be summed for use by an interpolating ADC. Each differential amplifier can be configured to generate multiple scaled output currents for use in current mode interpolation, for example.

It will be appreciated that the first conductor of the input sampling capacitor need not be connected to the input of the transconductance amplifier in the first state of the differential amplifier, and that it may be coupled to the input of the transconductance amplifier by a switch, for example. In a preferred embodiment, however, the voltage applied to the first conductor in the first state of the differential amplifier is a virtual ground voltage, i.e. for a differential transconductance amplifier, the voltage on one of the inputs is maintained by the closed feedback path to be equal to The (preferably fixed) voltage on the other differential input is the same. This may be provided by means of a switched DC feedback path from the output of the transconductance amplifier or a later stage such as a differential amplifier after an output driver device, eg a device providing mirrored or split output currents. In a preferred embodiment, the positive differential input of the transconductance amplifier is connected to a fixed reference voltage, such as ground, and the negative differential input of the transconductance amplifier is connected to the input sampling capacitor. Preferably, a low resistance switch, such as a FET switch, is then provided to couple the negative differential input to the current output of the differential amplifier. This virtual ground connection cancels the input offset voltage of the transconductance amplifier.

The voltage change provided to the input of the transconductance amplifier may be substantially equal to the difference between the first and second input voltages during the transition from the first to the second state of the differential amplifier, for example in the case of only a single input sampling capacitor or Where voltage changes can be scaled, for example where there is some charge sharing between two or more input sampling capacitors.

A differential differential amplifier can be constructed using a pair of the above differential amplifiers but along similar lines using a shared differential transconductance amplifier, so that in effect one input switch and a set of first and second input voltages are connected to the differential transconductance amplifier Each of the differential inputs (positive and negative) associated. In this way, the differential differential amplifier is responsive to a differential signal comprising two sets of voltage differences between two sets of said first and second input voltages. In general, a set of first input voltages will include positive and negative first input voltages and a set of second input voltages will include positive and negative second input voltages. As mentioned above, the circuit can be similarly extended by providing one or more additional sets of (differential) input sampling capacitors and/or adding additional (differential) transconductance amplifiers and/or mirroring Or provide multiple single-ended or differential outputs.

Thus, in the aspect concerned, the invention also provides a differential differential amplifier for providing an output current dependent on a differential signal at a differential input comprising two pairs of signal inputs, the Said differential signal comprises two voltage differences, the first being dependent on the difference between the first and second input voltages on a first of said pairs of signal inputs, the second being dependent on said pair of signal inputs The difference between the third and fourth input voltages on the second pair, the differential differential amplifier includes first and second input sampling capacitors, each having two conductors, respectively for the first and a second pair of signal inputs; a differential transconductance amplifier having a differential input coupled to said first and second input sampling capacitors and an output for generating said output current; a pair of input switches, a signal input There is one of each of the pairs for selectively coupling the first and second input sampling capacitors to one of the first and second input voltages and the third and fourth input one of the voltages; a pair of initialization switches for bringing the plates coupled to the first and second input sampling capacitors of the differential transconductance amplifier to an initial voltage; and a controller for controlling the input switch and the initialization switch to apply the differential signal to the differential transconductance amplifier.

The plates of the sampling capacitors can be brought to the same initial voltage or to different initial voltages, the output currents can include single-ended or differential output currents, and the circuit can likewise be expanded by providing additional pairs of sampling capacitors for additional differential Each additional pair of sampling capacitors has an associated pair of input switches used to determine the difference between a pair of input voltages.

According to another aspect of the present invention, there is provided an analog-to-digital converter comprising: at least one transconductance amplifier configured to provide a plurality of output currents at a plurality of outputs; and a plurality of comparators coupled to the plurality of transconductance amplifier outputs to provide a digital output; at least one switched input sampling capacitor coupled to an input of the transconductance amplifier; and at least one switch configured to alternately switch the input sampling capacitor Coupled to the first reference voltage and the analog voltage for conversion.

The analog-to-digital converter may comprise, for example, a current-mode interpolating or folding converter, which preferably comprises a plurality of stages. As previously described, by providing an input sampling capacitor and switches to alternately couple the capacitor to the analog and reference voltages for conversion, a sampling differential amplifier is provided which in an embodiment enables the elimination of existing sample and hold. In an embodiment, a pair of input sampling capacitors may be provided for each of a plurality of transconductance amplifiers to allow combinations of output currents with zero crossings at regular intervals of the input voltage threshold, thereby generating zero crossings Threshold voltage ladders for ease of use in generating digital outputs. In an embodiment, the digital output includes a thermometer code, which is converted to a binary representation.

An ADC may be used as the second stage of a two-stage ADC, where the first ADC provides a digital output to a first number of (most significant) bit precision to provide a rough approximation of the analog input signal. This rough approximation can then be used as a reference voltage for the input sampling capacitor in order to generate one or more least significant output bits of the two-stage analog-to-digital converter.

In accordance with related aspects of the present invention, there is provided a method of generating a current substantially linearly related to a voltage difference between a first and a second voltage using a circuit comprising a switch, a switched input capacitor and substantially In a linear transconductance amplifier, a first plate of the input capacitor is coupled to the input of the transconductance amplifier, and a second plate of the input capacitor is switchably coupled to first and second voltages, the method comprising: The second plate is coupled to the first voltage while maintaining the first plate at the reference voltage to charge the input capacitor; the second plate of the input capacitor is then coupled to the second voltage and the potential of the first plate is allowed to change by a value depending on the voltage The difference is by an amount such that the transconductance amplifier produces an output current that is substantially linearly related to the voltage difference.

When the input capacitor is connected to the first voltage and the reference voltage, it is charged, ie it is brought to a defined state of charge by the charge flowing onto or away from the capacitor. The voltage difference between the first and second voltages is then substantially passed to the input of the transconductance amplifier by connecting the second plate of the input capacitor to the second voltage.

In another aspect, the present invention provides a method of producing a current that is substantially linearly related to two voltage differences being a first voltage difference between a first and a second voltage and a third and a second voltage difference between a fourth voltage, the method employing a circuit comprising first and second switches, first and second switched input capacitors, and a substantially linear transconductance amplifier, the first input A first plate of the capacitor and a first plate of the second input capacitor are coupled together and to the input of the transconductance amplifier, a second plate of the first input capacitor is coupled to the first switch for switchably coupling to the second and a second voltage, and a second plate of a second input capacitor is coupled to a second switch for switchably coupling to a third and a fourth voltage, the method comprising: connecting the first and second input capacitors The second plates are coupled to the first and third voltages respectively while maintaining the first plates of the capacitor at the reference voltage to charge the input capacitors; the second plates of the first and second input capacitors are then coupled to the second and fourth voltages respectively and allow the charge on the first plate of the capacitor to be shared so that the potential of the first plate changes by an amount that is related to both the first and second voltage differences so that the transconductance amplifier produces a voltage that is substantially linearly related to both. The output current of the voltage difference.

The input capacitors can be of different sizes or values, thereby providing proportional scaling to the corresponding input voltage.

A differential amplifier configured to operate in accordance with these methods is also provided.

In a further aspect, the invention provides a method of operating a two-stage analog-to-digital converter comprising a first analog-to-digital converter for providing a coarse approximation to an analog input signal, and a second Two analog-to-digital converters comprising at least one differential amplifier configured to provide an output current relative to a difference between a first input voltage and a second input voltage, the differential amplifier comprising: a transconductance amplifier for providing the the output current to a comparator to provide a digital output; at least one switched input sampling capacitor coupled to the input of the transconductance amplifier; and at least one switch configured to alternately couple the input sampling capacitor to the The first and second input voltages, the method includes controlling the switch to couple the input sampling capacitor first to an analog voltage for conversion and then to the rough input signal approximation to provide a reference voltage.

Preferably, the differential amplifier output current is substantially linearly related to the difference between the first and second input voltages. More preferably, the method comprises using a plurality of differential amplifiers to compare the coarse input signal approximation to a plurality of reference levels, preferably by offsetting the reference levels of the differential amplifiers by using a second switched input sampling capacitor for each amplifier. proceed flat.

The invention also provides an analog-to-digital converter configured to operate according to the method.

Description of drawings

These and other aspects of the invention will now be further described, by way of example only, with reference to the accompanying drawings, in which:

Figures 1a to 1c show a general circuit diagram of an example stage of a current-mode interpolating analog-to-digital converter, an example of a differential transconductance amplifier and an example of a controllable current generator, respectively;

Figure 2 shows a typical two-stage analog-to-digital converter;

Figures 3a to 3d show a differential amplifier according to a first embodiment of the present invention, waveforms for the circuit of Figure 3a, a differential version of the amplifier of Figure 3a, and timing waveforms for the circuit of Figure 3c, respectively;

FIG. 4 shows a differential amplifier with multiple input capacitors according to a second embodiment of the invention;

FIG. 5 shows a differential amplifier comprising a plurality of transconductance amplifiers according to a third embodiment of the present invention;

Figure 6 shows a differential amplifier with mirrored outputs according to a fourth embodiment of the present invention;

FIG. 7 shows a differential amplifier with split current outputs according to a fifth embodiment of the present invention;

8 illustrates a current mode interpolating ADC including multiple sampling differential amplifiers according to an embodiment of an aspect of the present invention;

Figures 9a and 9b show a portion of a differential version of the interpolating ADC of Figure 8 and a differential input current comparator, respectively; and

Figure 10 shows an embodiment of a differential differential amplifier in accordance with an aspect of the present invention.

Detailed ways

Referring first to FIG. 3 a , a schematic circuit diagram of a differential amplifier 300 is shown. An input voltage Vin is provided on line 302 and a reference voltage Vref is provided on line 304 . The input sampling capacitor C1 306 has one plate coupled to a pair of switches S1 308, S2 310 that connect lines 302, 304 to capacitor 306, respectively. Switches 308 and 310 may be controlled to allow line 302 or line 304 to be connected to input sampling capacitor 306 and may comprise MOSFET or FET switches. The skilled person will appreciate that the illustration of switches 308 and 310 in Figure 3a is schematic and that other functionally equivalent switch configurations may be employed.

The other plate of input sampling capacitor 306 is coupled to the inverting input of differential transconductance amplifier 312 , which provides a current output Iout on line 314 . A third switch 316 is connected between the output line 314 and a node X 318 between the input sampling capacitor 306 and the inverting input of the transconductance amplifier 312. Likewise, switch S3 316 is controllable and may comprise a MOSFET or a FET. The non-inverting differential input of transconductance amplifier 312 is connected to a fixed potential, shown as ground potential Vgnd. Transconductance amplifier G1 312 has a transconductance of Gm. The three switches 308, 310 and 316 are controlled by a clock generator 322, as described in more detail below with reference to Figure 3b.

In many applications, differential amplifier 300 is implemented on an integrated circuit, which typically includes part of an analog-to-digital converter. The skilled person will appreciate that standard building blocks can be used for the various elements, and that transconductance amplifiers can be implemented, for example, using long-tailed bipolar or MOS pairs.

Referring now to Figure 3b, the circuit has two clock phases Phi1 and Phi2. Figure 3b shows the respective states 350, 352, 354 of switches S1 308, S2 310 and S3 316 and the respective voltages 356, 358 at node Y 317 and node X 318 during these two clock phases. During clock phase Phi1, switch S3 316 is closed to connect the output and (inverting) input of transconductance amplifier 312 together, so that the voltage at node X 318 is established to be equal to that on the inverting input 320 of transconductance amplifier 312 Same voltage, that is Vgnd. This is because node X 318 is a virtual ground, and while the skilled artisan will understand that in this case the voltage at node X is substantially the same as the voltage on the non-inverting input 320, in some embodiments this voltage may not be zero Volt.

Also during clock phase Phi1, switch S1 308 is closed to connect the left side of input sampling capacitor C1 306 (node Y) to Vin 302, and switch S2 310 is open. Thus, the voltage at node Y is equal to Vin. In the second clock phase Phi2, switch S3 316 is opened, switch S1 308 is opened and switch S2 310 is closed, thereby raising the voltage at node Y 317 by ΔV=Vref−Vin. This in turn raises the voltage at node X 318 from Vgnd by the same amount, resulting in an output current of Gmx(Vin−Vref), inverting because node X is coupled to the inverting input of transconductance amplifier 312. In a practical implementation, there is an additional capacitance associated with node X, such as the input capacitance of the transconductance amplifier 312, so the voltage step and resulting output current are attenuated. However, this is only equivalent to a reduction in Gm so that the output current is still proportional to the difference between Vin and Vref.

As shown in Figure 3b, it is preferred that switch S3 316 is turned off slightly before switch S1 308 to improve charge injection performance. Preferably there is also a slight underlap between S1 and S2 being closed to avoid a momentary conduction path between Vin and Vref, which would give avoidable load transients on the previous circuit that generated Vin and Vref .

Figure 3c shows one example of a differential implementation 370 of the differential transconductance amplifier 300 of Figure 3a, and Figure 3d shows timing waveforms for the circuit of Figure 3c.

In general terms, the differential circuit of Figure 3c corresponds to two matched circuits of the type shown in Figure 3a, although a single clock/timing generator 372 could be used to control both halves of the differential implementation 370. Otherwise, two circuits of the type shown in Figure 3a are used, from positive and negative differential inputs Vin 302a,b and Vref 304a,b respectively, one for providing positive Iout 314a and one for negative Iout 314b. In Fig. 3c, elements identical to those of Fig. 3a are indicated by the same reference numerals, "a" and "b" designating the positive and negative signal processing parts of the circuit, respectively.

Mathematically, taking the transconductance of amplifier 312a as Gm ⁺ and taking the transconductance of amplifier 312b as Gm ⁻ ,

Iout ⁺ ＝Gm ⁺ (Vin ⁺ -Vref ⁺ )

Iout ^- ＝Gm ^- (Vin ^- -Vref ^- )

dIout = Iout ⁺ -Iout ^-

＝Gm ⁺ (Vin ⁺ -Vref ⁺ )-Gm ^- (Vin ^- -Vref ^- )

And assume that in the case of Gm ⁺ =Gm ⁻ =Gm (meaning that the differential transconductance amplifiers G1 312a and G2 312b are substantially matched):

dIout=Gm(dVin-dVref)

where dVin=Vin ⁺ -Vin ^-

And dVref=Vref ⁺ -Vref ^-

In this way, common mode variations of Vin ⁺ , Vin ⁻ and/or Vref ⁺ , Vref ⁻ are substantially rejected, assuming that the positive and negative signal processing circuit portions of the differential differential amplifier implementation 370 are substantially symmetrical and matched.

The timing diagram shown in Figure 3d for the circuit of Figure 3c is very similar to that shown in Figure 3b for the circuit of Figure 3a, with waveforms 380, 382, 384, 386 and 388 corresponding to waveforms 350, 352 , 354, 356 and 358. Note however that waveforms 380, 382 and 384 refer to switches 1 and 4, switches 2 and 5 and switches 3 and 6 respectively rather than simply switches 1, 2 and 3 as in Fig. 3b. Apart from considering this difference of the two matched versions of the circuit of Fig. 3a providing a differential implementation of the circuit, the description of Fig. 3d corresponds to that already given for Fig. 3b and will not be repeated for brevity.

The skilled person will understand that variations are possible with respect to the circuit described with reference to Figures 3c and 3d. For example, transconductance amplifiers 312a and 312b may be implemented as a single fully differential transconductance amplifier.

Fig. 4 shows a second differential amplifier 400 which generalizes the switched input sampling capacitor concept shown in Fig. 3a. Elements identical to those of Figure 3a are indicated by the same reference numerals.

In FIG. 4 , an additional input sampling capacitor 406 is provided, which is also coupled to node 318 . The other plate of capacitor 406 is coupled to Vin2 402 via first switch S1a 408 and to Vref2 404 via S2a 410. Switches S1a 408 and S2a 410 operate synchronously with switches S1 308 and S2 310, respectively; the clock generator is not shown in FIG. 4 for simplicity. FIG. 4 does show the total parasitic capacitance on the inverting input of the transconductance amplifier (including the input capacitance of the transconductance amplifier 312 ) explicitly as lumped capacitor Cp 414 . Dashed line 412 connected to node X 318 indicates that the circuit of FIG. 4 can be extended by further adding input sampling capacitors and associated switches.

Ignoring the parasitic capacitance Cp for the moment, the total capacitance is C1+C2. The left-hand plate of C1 boosts the voltage Vref-Vin, while the left-hand plate of C2 boosts the voltage Vref2-Vin2. The total charge stored on the two capacitors is

(Vref-Vin)C1+(Vref2-Vin2)C2

which when shared across the total capacitance C1+C2 produces a voltage change ΔV given by

(C1+C2)ΔV=(Vref-Vin)C1+(Vref2-Vin2)C2

or

ΔV=[(Vref-Vin)C1+(Vref2-Vin2)C2]/(C1+C2)

When the parasitic capacitance Cp is non-zero, charge is shared across Cp such that the total effective capacitance is C1+C2+Cp. In this case, the voltage change dVin in Phi2 is given by

-dVin=-(Vx-Vgnd)

=[(Vin-Vref)C1+(Vin2-Vref2)C2]/(C1+C2+Cp)

and

Iout＝-G.dVin

Iout＝G[(Vin-Verf)C1+(Vin2-Vref2)C2]/(C1+C2+Cp) (Equation 1)

Cp is often voltage dependent, however in practical designs this dependence has been shown to be small enough that it is not a significant constraint on linearity.

Referring now to FIG. 5 , there is shown a third differential amplifier 500 generalized on the arrangement of FIG. 4 . Elements that are the same as those of FIG. 4 are indicated by the same reference numerals.

In FIG. 5, a plurality of transconductance amplifiers are provided, which are illustrated by a second differential transconductance amplifier G2 502 and an Nth differential transconductance amplifier GN 508. Transconductance amplifiers 502 and 508 have their inverting inputs connected to node X 318 and, in the illustrated embodiment, their non-inverting inputs connected to Vgnd 320 . Each additional transconductance amplifier has a corresponding current output 506, 512, and optionally, a closed loop feedback switch S32 504, S3N 510, establishing node X 318 as a virtual ground. It will be understood however that only one of the switches S31 316, S32 504 and S3N 510 is required.

Each of the differential transconductance amplifiers G1 , G2 , . . . GN may have a different transconductance to effectively provide a differential amplifier with multiple transconductances and multiple output currents at a fixed scaling or ratio to each other.

In the arrangement of Figure 6, the output 314 of the transconductance amplifier 312 is mirrored by the current mirror 602 to provide multiple outputs. The current mirror includes a plurality of current sinks 602a-d (alternatively, current sources may be employed) to provide up to N current outputs, three of which 604a-c are shown in FIG. 6 . Each current output is at a fixed ratio or multiple of the current lout on the transconductance amplifier output 314, and in this way the differential amplifier 600 can be provided with multiple outputs having different (total) transconductances. The multiple output current mirror 602 may be constructed in any conventional manner using different sized FETs or bipolar transistors or using multiple transistors to provide a current ratio other than 1:1. As shown in FIG. 6, switch S3 316 may be coupled directly to current output 314 of transconductance amplifier 312 or to one of current outputs 604a-c to output from the first stage or from one (or more or all) mirrors output to provide feedback. However, this depends on the polarity of the first stage transconductance, since there should be a general inversion to allow closure of S3 316 to create a virtual ground at node X 318.

FIG. 7 shows a fifth differential amplifier 700 again generalized on the arrangement of FIG. 4 , and again therein elements that are the same as those of FIG. 4 are indicated by the same reference numerals.

In the arrangement of FIG. 7, the output current Iout on the output 314 of the transconductance amplifier 312 is split by a plurality of transistors 702a-c into a plurality of output currents Iout1, Iout2, . . . , IoutN 704a-c. Transistors 702a-c are connected in parallel and have a common control connection 706; in the illustrated embodiment, the transistors comprise field effect transistors, preferably NMOS devices, with a common source connection to current output 314 and to common gate connection for the bias voltage. The drain connections of the transistors provide current outputs 704a-c.

To allow bidirectional output currents Iout1, Iout2, . is connected to the current output to subtract the added constant current before outputting Iout1 , Iout2 , . . . , IoutN.

As with the arrangement of Figure 6, the dimensions (or other parameters) of transistors 702a-c may be in a fixed ratio to produce output currents in a fixed ratio to each other. To this end, transistors 702a-c are preferably matched, for example by being fabricated on a common substrate. In this way, multiple different total transconductances can again be provided to the differential amplifier 700 . The current drawn by the constant current sink 708 will also be scaled by the same ratio, so the accompanying current sources mentioned above should also be scaled by the same ratio.

A differential output equivalent to each of the above differential amplifiers, specifically the differential amplifier circuits of FIGS. 4 to 7 and The differential amplifier of the interpolating ADC stage in Figure 8 below. This has been described with reference to FIG. 3 and will be readily understood by those skilled in the art.

FIG. 8 shows a current mode interpolating ADC 800 incorporating multiple differential amplifiers as described above. The switched input sampling capacitors in each of these differential amplifiers provide a relatively cheap and simple replacement for conventionally employed sample and hold circuits.

The ADC of Figure 8 provides 6-bit conversion precision and can be used, for example, as a 6-bit backend to follow a 10-bit pipeline, resulting in a 16-bit analog-to-digital converter.

Referring to FIG. 8, an analog input voltage Vin on line 802 is provided to an output of each of a flash ADC (flashADC) 804 and a plurality of transconductance difference amplifiers 816a-d, which in the illustrated example are four. Flash ADC 804 has eight coarse (MSB) comparators with thresholds at -7/8, -5/8, -3/8, -1/8, +1/8, +3/8 of the reference range , +5/8 and +7/8. These thresholds determine where the input voltage is centered at -8/8, -6/8, -4/8, -2/8, 0, +2/8, +4/8, +6/8, +8/8 one of the nine districts. Flash ADC 804 provides a digital output on line 806 , which is provided to combiner 808 and digital-to-analog converter 812 . The digital output includes a sign bit plus three additional bits to define a 2's complement number in the range [-4,+4] (not all 16 codes defined by 4 bits are used). Combiner 808 adds the MSB information from the flash ADC to the LSB information on bus 836 with an appropriate delay to provide a 6-bit output on bus 810 .

The most significant bit received by DAC 812 is converted back to an analog voltage VrefM on line 814, which is provided to a second input of each of transconductance differential amplifiers 816a-d. DAC 812 may include, for example, a multiplexer built from a plurality of transmission gates configured to select taps on the resistor string.

Possible VrefM voltages on line 814 are -8/8, -6/8, -4/8, -2/8, 0, +2/8, +4/8, +6/8 and +8 of the reference range /8, or equivalently -4/4, -3/4, -2/4, -1/4, 0, +1/4, +2/4, +3/4, and +4/4. It will be appreciated that the value of VrefM output by DAC 812 will be in the middle of the region of the reference range where flash ADC 804 determines that the input voltage on line 802 lies. The voltage VrefM is fed to the reference inputs of the four differential amplifiers 816a-d, i.e. the inputs corresponding to the input 304 of FIG. The input of the input 302 of the differential amplifier is shown.

The paired inputs 818a-d of each of the four differential amplifiers 816a-d thus correspond to the inputs 302 and 304 of the differential amplifier of FIG. Each of the differential amplifiers 816a-d also has a second pair of inputs 820a-d, which correspond to inputs 402 and 404 of the differential amplifier of FIG. Input pair 818 is connected to an input sampling capacitor 826 (C1 in FIG. 4) and input pair 820 is connected to a second input sampling capacitor 828 (C2 in FIG. 4). The transconductance amplifier sides of the two capacitors are connected together and to the inverting input of transconductance amplifier 830 (as shown in FIG. 4 ). The output of the transconductance amplifier 830 is mirrored or split as shown in FIG. 6 or 7, or multiple transconductance amplifiers may be employed as shown in FIG. 5 to provide multiple current outputs 832 to each of the differential amplifiers 816a-d. indivual. For example, differential amplifier 816a provides a current output with a ratio of 1.0:0.8:0.6:0.4:0.2. The current outputs from differential amplifiers 816a-d are summed as shown in FIG. 8 in a conventional manner such as that described with reference to FIG. 1 for an interpolating ADC. Multiple current outputs at a given scaling factor, eg 0.2, may be provided if the current output at that scaling factor is used more than once. This can be implemented by a conventional current mirror with one output transistor for each of the outputs 832 along line 832 as shown in FIG. 6 . Alternatively, arrangements such as those shown in Figures 5 and/or 7 may be employed. The clock generators that control the differential amplifiers 816a-d are not shown in FIG. 8 for simplicity.

Each pair of inputs 820a-d has a first input connected to a common reference voltage line 822 as shown at 0 volts and a second input connected to a corresponding second reference voltage line 824d-a. The second reference voltages on lines 824a-d form reference voltage steps, spaced apart by 5/16 of the reference range in the illustrated example. Thus, the reference voltages applied to each of differential amplifiers 816a-d are -8/16, -3/16, +2/16, and +7/16 of the reference range and vary linearly. Capacitor 826 (Cl in FIG. 4 ) of each differential amplifier has twice the value of capacitor 828 (C2 in FIG. 4 ). Choosing C1 greater than C2 reduces the attenuation in the signal path from Vin to the input of the transimpedance amplifier. This capacitor ratio of 1/2 sets the LSB transition range from -8/32 to +7/32 of the reference range, and due to double subtraction (i.e., since the differential amplifier output is also related to Vin-VrefM), this LSB transition range is given by is centered on an approximation of the input voltage VrefM. The input range extremes are +31/32 and -32/32 to give 64 codes, so that the LSB step size is 1/32 = ^1/25 although the converter shown is a 6 bit converter.

Current interpolation between the outputs 832 of the differential amplifiers 816a-d produces a range of currents with zero-crossing thresholds equivalent to one discrete LSB. For this, there are five weighted current mirrors between adjacent differential amplifiers, giving 16 output taps including terminals. The threshold determined by the current output of differential amplifier 816a alone is +7/32 of the reference range; the threshold determined by differential amplifier 816b alone is +2/32 of the reference range; the threshold determined by differential amplifier 816c is -3/32; And the threshold determined by the differential amplifier 816d is -8/32 of the reference range. Between each of these there are four intermediate thresholds, which are defined by quintupling the output current in a manner similar to the three intermediate thresholds defined by summing the quarters of the output current in the setup of FIG. 1 One of the summation formed. A zero-crossing comparator 834 on these 16 taps determines the difference (VrefM-Vin) that will lie within one of the 17 zones and provides a thermometer code output on bus 836 . The thermometer code is converted to regular binary code for combining with the MSB on bus 806 by combiner 808 . The use of current interpolation instead of resistive interpolation improves the linearity of the ADC by removing end effects due to mismatched impedances at the top and bottom of the resistively interpolated string.

The above discussion can be illustrated by an example. The differential amplifier 816a has a capacitor C2 828 that switches between +7/16 and 0 volts. Examination of Equation 1 shows that when capacitor C2 is half the value of C1 (capacitor 826), the voltage difference on input 820a effectively gives half the weight of the voltage difference on input 818a of differential amplifier 816a. Thus the zero-crossing threshold for differential amplifier 816a is shifted by +7/32. Since the voltage difference on input pair 820a actually has the opposite sign of the voltage difference on input pair 818a, the voltage Vin on line 802 must be +7/32 of the reference range above VrefM on line 814 for zero output current. It can thus be seen that "1.0 times" the output of differential amplifier 816a defines a threshold at +7/32 of the reference range. In a similar manner, "1.0 times" the output of differential amplifier 816b defines a threshold at +2/32 of the reference range. The +6/32 threshold is calculated by summing 0.8 of the current output of differential amplifier 816a and 0.2 of the current output of differential amplifier 816b according to the equation 0.8x(7/32)+0.2x(2/32)=6/32 limited. Other thresholds are similarly defined at 2/5, 3/5 and 4/5 of the difference between +7/32 and +2/32. Thresholds from +1/32 to -8/32 are defined in a corresponding manner.

Strictly speaking, only 8 comparators are needed to cover the full range between each VrefM, the additional comparators actually provide the extra MSB. However, it is preferable to provide additional comparators because they provide a margin for error in the comparator thresholds of the flash ADC 804. The 16 thresholds define 17 bins (cf. description above for flash ADC 804) and the 16 outputs from comparator 834 are preferably encoded as two's complement LSB values in the range [-8,+8], although Other protocols and ranges may be used in other embodiments. The complete digital output value can then be calculated simply by adding the two's complement MSB from the flash ADC 804 to the two's complement LSB from the second, interpolating ADC stage according to the following equation, appropriately adding the MSB Move left:

Output = 8 x MSB + LSB.

Adding the digital output signals from the two stages in this way automatically provides correction for conversion errors produced by the flash ADC 804, for example, due to offset voltages in the flash ADC comparators. Even if the digital output from the flash ADC 804 is "incorrect", the output from the DAC will still agree with that digital output, which will cause the reported second stage zone to change by an amount, whereby once the corresponding digital output When combined, the error of VrefM is automatically corrected. This LSB overrange accommodates the offset in the flash ADC comparator of approximately 1/16 of the (flash) reference range.

A further benefit of providing the required number of additional comparators beyond the required number of LSB precision is to provide a two-stage ADC 800 which, considered as a whole, has over-range capability. This is because the total digital output is spread over the range [-40, +40] for a total of 81 codes, since there are actually 8 additional codes provided by a second stage, differential amplifier based ADC at either end of the range. This is because the extremum codes from flash correspond to regions centered at +/- 8/8Vref, giving nominally 0/64 at the LSB level for nominal full-scale input, thus giving Vref at either end. 8 additional codes for . Of these codes, 64 may be considered "in range", which corresponds to an input lying within the reference range, and the rest may be considered "over range" codes. As mentioned above, where an ADC is used to provide a backend to a pipeline or other converter, this overrange capability can be used to correct for comparator offset voltage or other errors.

The setup of Figure 8 shows a single-ended rather than a differential analog-to-digital converter, but the skilled person will readily recognize that the architecture can be modified to routinely provide a differential implementation as shown in Figure 9a, Figure 9a A portion of a differential version 900 of the interpolating ADC of FIG. 8 is shown, wherein like elements to those of FIG. 8 are indicated by like reference numerals. A single-ended implementation has been described for ease of understanding of the invention, but in many instances a differential implementation is preferred because it can be used since the internal signal swing can be doubled for a fixed headroom and extraneous interfering signals are rejected. Enables an improvement in the signal-to-noise ratio.

Referring to FIG. 9a, a portion of one embodiment of a differential version 900 of the single-ended circuit of FIG. 8 is illustrated. Interpolating ADC 900 has differential voltage inputs Vin+ 802, Vin- 802', which are provided to input flash ADC 804' and pairs of transconductance difference amplifiers, one pair 816a, 816a' is shown. The flash ADC 804' drives a differential output DAC 812', which in turn drives a pair of differential amplifiers. A positive voltage input Vin+ 802 goes to the first 816a transconductance differential amplifier of the pair and a negative voltage input Vin- 802' goes to the second 816a' transconductance differential amplifier of the pair. The pair of transconductance differential amplifiers 816a, 816a' are substantially identical, with one outputting a positive current Iout+ and the other 816a' outputting a negative output current Iout-. The output currents of that pair and each other pair of output currents from the remaining pairs of transconductance differential amplifiers (not shown in Figure 9a) are provided to a set of differential input to the differential input of the current comparator 834'.

Positive and negative versions of the differential amplifier reference voltage are provided, one for each of each pair of differential amplifiers. Thus, for example, reference 824a at +7/16 of the reference range is provided to differential amplifier 816a and reference 824' at -7/16 of the reference range is provided to differential amplifier 816a'. Differential versions of each other reference voltage are provided to corresponding differential amplifiers of the other pairs of differential amplifiers. A common reference voltage 822 is provided to both the positive 816a and negative 816a' voltage-handling differential amplifiers and, in an embodiment, may be caused to drift since its voltage is the " common mode". In this setup, the reference voltage Vref of the single-ended version of the ADC of Figure 8 is replaced by a differential pair of reference voltages Vref+, Vref-, each having the same amplitude as the previous single-ended Vref. This has the effect of doubling the "full scale" input range (ie ignoring the overrange capability), because the full scale is extended to Vin+=+2.0 and Vin-=-2.0 instead of Vin=1.0, -1.0. However, the same full-scale range can be obtained by halving the reference voltage.

Figure 9b shows one implementation of a differential input current comparator 910 suitable for use in comparator bank 834' of differential interpolation ADC 900. The current comparator 910 has a pair of differential current inputs Iin+912, Iin-912', each connected to a corresponding resistor 914, 914', the other ends of which are connected together to a common mode voltage source VR 916 . The inputs 912, 912' are also connected to respective non-inverting and inverting inputs of a conventional differential input voltage comparator 918 which in turn provides an output 920. The skilled person will realize that the arrangement of Figure 9b can be modified to suit a particular application and/or to comply with bias constraints on the transconductance amplifier stage. For example, one or more common gate stages could be added in series with each input, or MOS resistors could be used for resistors 914, 914', or these resistors could be replaced with cross-coupled MOS transistors to increase the comparison voltage gain of the device.

Figure 10 shows an example of a differential differential amplifier suitable for use in the pair of positive 816a and negative 816a' differential amplifiers described above with reference to Figure 9a. Although the differential differential amplifier of FIG. 10 may be considered as a pair of differential amplifiers, it may be better to view the differential differential amplifier 1000 as a combination.

In summary, the differential differential amplifier 1000 of FIG. 10 is a combination of two single-ended differential amplifiers of the type shown in FIG. 4 and a differential transconductance amplifier similar to that shown in FIG. 1b. Thus in FIG. 4, the circuit on the left of line A'-A' corresponds to the input circuit of the differential amplifier embodiment in FIG. 4, as does the circuit on the right of line B'-B'. B is for the differential transconductance amplifier. Reference numerals for circuit parts correspond to those of FIG. 4 and for convenience, reference numerals for lines to which the differential differential amplifier is attached when used in the analog-to-digital converter of FIG. 9a are indicated in parentheses. In general terms, the combination of elements 1002, 1004, 1006 and 1014 and 1016 of Fig. 10 correspond to elements 136, 132, 134 and 138 of Fig. Ib, respectively.

The differential differential amplifier includes a current sink 1002 that is coupled to the source connections of a differential pair of input transistors 1004, 1006, each of which has a current sink connected to a respective (active load FET) transistor 1014, 1016. drain. In a generally similar manner to NMOS device 602 of FIG. 6, current through FETs 1014 and 1016 is mirrored by respective sets of scaled PMOS transistors 1018, 1020 to provide scaled differential (current) output sets. Corresponding switches 1008, 1010 are provided to transistors 1004, 1006, each corresponding to switch S3 316 of FIG. voltage), which is connected to ground in the illustrated embodiment. In Figure 10, switches S1, S2, S1a, S2a, 1008, and 1010 are controlled by a controller or clock generator (not shown in Figure 10 for simplicity) in a manner similar to that described above with reference to Figures 3b and 3d. to control.

In a first state or clock phase, switches S1 and S1a are closed to couple the first voltage input on lines 302 and 402 to one side of input sampling capacitors C1 and C2, and switches 1008 and 1010 are closed to allow these capacitors The other side of the V2 becomes the initial voltage either by sharing charge or by having its plate connected to a bias or virtual ground voltage. Then in a subsequent state or clock phase, these switches are both opened and switches S2 and S2a are closed to apply the second input voltage to capacitors C1 and C2 to switch between the first and second input voltages relative to each set The differential input voltage change of the difference is provided to the differential input of the transconductance amplifier.

In operation, the input stage of differential difference amplifier 1000 operates similarly to that of the differential amplifier of FIG. 54 . Thus, input A to the differential transconductance amplifier receives a change in voltage relative to the difference between Vin ⁺ and VrefM ⁺ plus an offset relative to the difference between the voltage on line 824a and the voltage on line 822 ( scaled by capacitor C2). Similarly, input B receives a change in voltage relative to the difference between Vin ⁻ and VrefM ⁻ plus an offset relative to the voltage difference between lines 824 a ′ and 822 (scaled by capacitor C2 ). The transconductance amplifier provides an output current dependent on the difference between the voltages at differential input nodes A and B and provides a differential output on load FETs 1014 and 1016 (which may be single-ended in other embodiments), these The output current is mirrored by sets of FETs 1018 and 1020, respectively. In other words, one of nodes A and B may be considered a positive differential input and the other a negative differential input, and the differential transconductance amplifier provides a differential output comprising opposite sign of the output current.

The skilled person will realize that many variations are possible with respect to the circuit of FIG. 10 . For example, the current mirror consisting of transistors 1014, 1018, 1016, 1020 could be replaced with an output stage similar to that shown in FIG. 7 including FET 702.

Additionally, or alternatively, elements 1002, 1004, and 1006 may be replicated along the lines shown in FIG. 5, and the PMOS current mirrors may be reduced in number or eliminated. Switches 1008 and 1010, shown connected to a bias voltage such as ground voltage, may alternatively be connected to a virtual ground, such as the respective gates of transistors 1014 and 1016 (switches 1008 and 1010 are then separated rather than connected together) . The skilled artisan will further appreciate that the common reference voltage line 822 may be any convenient bias voltage, and that in embodiments, the line may be allowed to drift (i.e. not be connected to any particular bias voltage), in which case Capacitor C2 406 will share charge when switch S2a 410 is closed (ie, turned on).

The requirements on a transconductance amplifier used in an interpolating ADC, such as ADC 800 of FIG. 8, are relatively modest. The accuracy of the converter depends on the accuracy of the two differential amplifiers with the minimum input signal. For the example of Fig. 8, only the amplifier involved in any decision will have at most about +/- 4/64 of the input voltage, and the resulting output only needs to be corrected to say 0.5LSB = 1/64. For this reason, in many of these applications, differential amplifiers do not require any feedback, nor do they have to be particularly high gain or low offset or precisely built differential amplifiers. Settling time issues are unlikely to occur for the output of the most critical differential amplifier when the output of that amplifier only has to settle to a small voltage because accuracy is only critical near the threshold point where the amplifier sees only small differential voltage. Thus, the differential amplifier can be small and simple, and the transconductance amplifier need only comprise a single long-tailed bipolar or MOS pair, as shown for example in Fig. 1b. Still, the differential amplifier is the most sensitive part of the design.

The gain from the ADC signal input line 802 to the input to the comparator 834 is typically on the order of Gm/Gout, where Gout is the output impedance at the scaled current output (which is reduced by the capacitive attenuation at the differential amplifier input capacitor network). is reduced). This is equivalent to a preamplifier ahead of the comparator that is often included in conventional ADCs, thus providing a large enough comparator overdrive to allow the use of simple comparator architectures such as simple differential latches, whereas No separate preamp stage is required.

The reference voltage for lines 824a-d can be generated by a resistor string, and preferably this is set to have a low enough impedance to provide the current needed to switch an input sampling capacitor (such as capacitor 828 in FIG. 8 ) without experience significant loading effects. It is further preferred that the second stage LSB overrange preparation is sufficient to overcome offset errors in the MSB (flash ADC) comparator.

No doubt many effective variations of the above circuit will occur to the skilled person. For example, switch S3 316 in the circuit of FIG. 3a may be connected to a reference voltage to set the charge on capacitor C1 306 rather than to the output 314 of transconductance amplifier 312, and optionally an additional switch may be inserted at node between X 318 and the inverting input of transconductance amplifier 312 (although this would effectively remove the auto-zero function of the circuit). Similarly, it is generally possible to swap current sources for sinks, and vice versa. It will be understood that the present invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art within the spirit and scope of the appended claims.

Claims (41)

1. differential amplifier, it is configured to provide the output current that depends on the difference between first input voltage and second input voltage, and this differential amplifier comprises:

The input sample capacitor, it has two conductors;

Trsanscondutance amplifier, the electric current output that it has the input of first conductor that is coupled to described input sample capacitor and is suitable for producing described output current; And

Input switch, be used for optionally second conductor of described input sample capacitor is coupled to first input of described differential amplifier so that receive described first input voltage, and be coupled to second input of described differential amplifier so that receive described second input voltage;

What described differential amplifier was configured under first state described second conductor is coupled to described first and second inputs imposes on voltage described first conductor in the lump, and under second open loop situations described second conductor is coupled to described first and second inputs another so that the described input to described trsanscondutance amplifier of the change in voltage that depends on the described difference between described first and second input voltages to be provided.

2. differential amplifier as claimed in claim 1, wherein said trsanscondutance amplifier comprise linear trsanscondutance amplifier, thereby make described differential amplifier output current be relevant to poor between first and second input voltages linearly.

3. differential amplifier as claimed in claim 1, wherein said trsanscondutance amplifier comprises differential trsanscondutance amplifier, and the described voltage that is applied under described first state to described first conductor is virtual ground voltage.

4. differential amplifier as claimed in claim 2, wherein said trsanscondutance amplifier comprises differential trsanscondutance amplifier, and the described voltage that is applied under described first state to described first conductor is virtual ground voltage.

5. differential amplifier as claimed in claim 1, wherein said trsanscondutance amplifier comprises the differential trsanscondutance amplifier with two differential inputs, and first of wherein said differential input is coupled to described first conductor and second of described differential input is coupled to the sampling capacitor reference voltage, and described differential trsanscondutance amplifier is configured to make the described first differential input to have and the identical voltage of the described second differential input under described first state of described differential amplifier.

6. differential amplifier as claimed in claim 2, wherein said trsanscondutance amplifier comprises the differential trsanscondutance amplifier with two differential inputs, and first of wherein said differential input is coupled to described first conductor and second of described differential input is coupled to the sampling capacitor reference voltage, and described differential trsanscondutance amplifier is configured to make the described first differential input to have and the identical voltage of the described second differential input under described first state of described differential amplifier.

7. as claim 5 or 6 described differential amplifiers, further comprise second switch, be used under described first state, providing the closed loop resistance feedback network to described differential trsanscondutance amplifier.

8. as claim 5 or 6 described differential amplifiers, further comprise second switch, it is configured to described first conductor switchably is coupled to the point that output drove by described trsanscondutance amplifier.

9. as claim 3,4,5 or 6 described differential amplifiers, comprise a plurality of differential trsanscondutance amplifiers, be used to provide a plurality of output currents, each described differential trsanscondutance amplifier all has a differential input that is coupled to described first conductor.

10. as any one described differential amplifier in the claim 1 to 6, further comprise:

Third and fourth input is used to receive third and fourth input voltage;

The second input sample capacitor, it has two second capacitor conductors; And

Second input switch;

First of the described second capacitor conductor is coupled to described first conductor and second of the described second capacitor conductor is coupled to described second input switch, described second input switch is configured to optionally described second conductor of described second capacitor is coupled to described the 3rd input and described the 4th input, thereby makes described output current further depend on poor between described third and fourth input voltage.

11. differential amplifier as claimed in claim 10, one of wherein said first and second voltages input comprises the input of first reference voltage, and one of described third and fourth voltage input comprises the input of second reference voltage.

12. as any one described differential amplifier in the claim 1 to 6, further comprise current mirror, its output that is coupled to described trsanscondutance amplifier is with the output current of Mirroring Mapping from described trsanscondutance amplifier.

13. differential amplifier as claimed in claim 12, wherein said current mirror are configured to provide with fixing mutual ratio a plurality of image releases of described differential amplifier output current.

14. any one the described differential amplifier as claim 1 to 6 further comprises a plurality of output transistors, is used to separate output current from described trsanscondutance amplifier so that a plurality of versions of described differential amplifier output current to be provided.

15. differential amplifier as claimed in claim 14, wherein said a plurality of output transistors have common bias voltage.

16. differential amplifier as claimed in claim 14, wherein said a plurality of output transistors are configured to make described a plurality of versions of described output current to have fixing mutual ratio.

17. differential amplifier as claimed in claim 15, wherein said a plurality of output transistors are configured to make described a plurality of versions of described output current to have fixing mutual ratio.

18. a differential differential amplifier, it comprises wherein each all as any one the described a pair of differential amplifier in the claim 1 to 6, be used to handle described first and second input voltages differential to and be used to provide differential output.

19. differential differential amplifier as claimed in claim 18, the trsanscondutance amplifier of each differential amplifier that wherein said differential amplifier is right is to share differential trsanscondutance amplifier, thereby a pair of differential amplifier of described differential differential amplifier has single, public differential trsanscondutance amplifier.

20. differential differential amplifier, be used to provide the output current of the differential wave that depends on the first differential input, the described first differential input comprises two pairs of signal inputs, described differential wave comprises two voltage differences, first voltage difference depends on poor between first and second input voltages on right the first couple of described signal input, second voltage difference depends on poor between third and fourth input voltage on right the second couple of described signal input, and described differential differential amplifier comprises:

The first and second input sample capacitors, each all has two conductors, is respectively applied for described first and second pairs of signals input;

Differential trsanscondutance amplifier, it has differential input that is coupled to the described first and second input sample capacitors and the output that is used to produce described output current;

A pair of input switch, it is right that each is used for a described signal input, is used for optionally the described first and second input sample capacitors being coupled respectively to one of described first and second input voltages and one of described third and fourth input voltage;

A pair of initialisation switch is used to make the plate of the described first and second input sample capacitors that are coupled to described differential trsanscondutance amplifier to be in initial voltage; And

Controller is used to control described input switch and described initialisation switch described differential wave being imposed on described differential trsanscondutance amplifier, and optionally with open loop situations or the described differential trsanscondutance amplifier of closed loop state of operation.

21. differential differential amplifier as claimed in claim 20, further comprise the third and fourth input sample capacitor, and second pair of input switch, be used for optionally the described third and fourth input sample capacitor-coupled to comprising the second right differential input of third and fourth signal input that is used for receiving respectively third and fourth voltage difference.

22. an interpolation analog-digital converter, it combines the differential amplifier according to one of claim 1 to 6, perhaps according to the differential differential amplifier of claim 20 or 21.

23. an analog-digital converter, it comprises:

At least one trsanscondutance amplifier, it is configured to provide a plurality of output currents in a plurality of outputs place;

A plurality of comparators, it is coupled to described a plurality of trsanscondutance amplifier output and is used to provide numeral output;

At least one switch input sample capacitor, it is coupled to the input of described trsanscondutance amplifier;

At least one selector switch, it is configured to described input sample capacitor alternately is coupled to first reference voltage and the aanalogvoltage that is used to change; And

At least one feedback switch, it is configured to the output of described trsanscondutance amplifier is coupled to the described input of described trsanscondutance amplifier when described input sample capacitor is coupled to the described aanalogvoltage that is used to change.

24. analog-digital converter as claimed in claim 23, it comprises:

The first and second input sample capacitors, its each all be coupled to the input of described trsanscondutance amplifier; And

First and second selector switches, described first selector switch is configured to the described first input sample capacitor alternately is connected to described first reference voltage and the described aanalogvoltage that is used to change, and described second selector switch is configured to the described second input sample capacitor alternately is connected to the second and the 3rd reference voltage.

25. analog-digital converter as claimed in claim 24, it comprises a plurality of described trsanscondutance amplifiers, its each all have the corresponding first and second input sample capacitors and first and second selector switches.

26. analog-digital converter as claimed in claim 25, one of the wherein said second and the 3rd reference voltage is public to described a plurality of trsanscondutance amplifiers, and wherein other the described second and the 3rd reference voltages of each described trsanscondutance amplifier are set to ladder.

27. analog-digital converter as claimed in claim 26, the electric current output of wherein said trsanscondutance amplifier is combined to provide a plurality of current signals to be used for described a plurality of comparator, and described current signal has zero crossing at the increment place that equates of described aanalogvoltage.

28. any one described analog-digital converter as claim 23 to 27, the wherein said aanalogvoltage that is used to change is a differential voltage, and wherein said analog-digital converter comprises the differential version with the right described trsanscondutance amplifier of differential input, each right input of described differential input all is coupled with described input sample capacitor and described selector switch, is used for converting described differential aanalogvoltage to number format.

29. two-stage analog-digital converter, it comprises first analog-digital converter, be used to provide rough approximation to analog input signal, and as any one described second analog-digital converter of claim 23 to 27, be used to provide one or more least significant digit carry-out bits to be used for described two-stage analog-digital converter, wherein said first reference voltage comprises the described rough approximation of described analog input signal.

30. two-stage analog-digital converter, it comprises first analog-digital converter, be used to provide rough approximation to analog input signal, and second analog-digital converter as claimed in claim 28, be used to provide one or more least significant digit carry-out bits to be used for described two-stage analog-digital converter, wherein said first reference voltage comprises the described rough approximation of described analog input signal.

31. one kind use a circuit to produce and first and second voltages between the method for electric current of voltage difference linear correlation, described circuit comprises switch, switch input capacitor and linear trsanscondutance amplifier, first plate of switch input capacitor is coupled to the input of trsanscondutance amplifier, second plate of switch input capacitor switchably is coupled to first and second voltages, and described method comprises:

Second plate of switch input capacitor is coupled to first voltage, by the output that first plate is coupled to described trsanscondutance amplifier first plate is maintained reference voltage simultaneously, so that the switch input capacitor is charged; Then

Second plate of switch input capacitor is coupled to second voltage and first plate of switch input capacitor and the output of trsanscondutance amplifier are disconnected, allow the electromotive force of first plate to change an amount that is relevant to described voltage difference so that described trsanscondutance amplifier produces the output current with described voltage difference linear correlation.

32. the method for the electric current of a generation and two voltage difference linear correlations, described two voltage differences are first voltage difference between first and second voltages and second voltage difference between third and fourth voltage, described method adopts a circuit, this circuit comprises first and second switches, the first and second switch input capacitors and linear trsanscondutance amplifier, first plate of the first switch input capacitor and first plate of second switch input capacitor are coupling in together and are coupled to the input of trsanscondutance amplifier, second plate of the first switch input capacitor is coupled to first switch and is used for switchably being coupled to first and second voltages, be used for switchably being coupled to third and fourth voltage and second plate of second switch input capacitor is coupled to second switch, described method comprises:

Second plate of the first and second switch input capacitors is coupled respectively to first and tertiary voltage, the output that is coupled to described trsanscondutance amplifier by first plate with the described first and second switch input capacitors simultaneously maintains reference voltage with first plate of the described first and second switch input capacitors, with to described first and second switch input capacitors charging; Then

Second plate of the first and second switch input capacitors is coupled respectively to the second and the 4th voltage, and the output of first plate of the described first and second switch input capacitors and described trsanscondutance amplifier disconnected, allow the electric charge on first plate of the described first and second switch input capacitors to be shared, depend on described both amounts of first and second voltage differences so that described trsanscondutance amplifier produces the output current that is linearly related to two described voltage differences so that the electromotive force of first plate changes one.

33. method as claimed in claim 32 further comprises by the electric capacity of the described first and second switch input capacitors of convergent-divergent accordingly and comes convergent-divergent first and second voltage differences.

34. method of operating the two-stage analog-digital converter, this two-stage analog-digital converter comprises first analog-digital converter, be used to provide rough approximation to analog input signal, with second analog-digital converter, it comprises at least one differential amplifier, be configured to provide the output current that depends on the difference between first input voltage and second input voltage, described differential amplifier comprises: trsanscondutance amplifier, be used to provide described output current to comparator so that numeral output is provided; At least one switch input sample capacitor, it is coupled to the input of described trsanscondutance amplifier; At least one feedback switch, it is configured to optionally the output of described trsanscondutance amplifier is coupled to the described input of described trsanscondutance amplifier; And at least one selector switch, it is configured to described input sample capacitor alternately is coupled to described first and second input voltages, and described method comprises:

Control described selector switch so that described input sample capacitor at first is coupled to the aanalogvoltage that is used to change;

Closed described feedback switch is to be coupled to the output of described trsanscondutance amplifier the described input of described trsanscondutance amplifier;

Control described selector switch, with described input sample capacitor-coupled to the described rough approximation of described analog input signal so that reference voltage to be provided; And

Disconnect described feedback switch.

35. method as claimed in claim 34, wherein the differential amplifier output current is linearly related to described poor between first and second input voltages.

36. as claim 34 or 35 described methods, wherein said second analog-digital converter comprises a plurality of described differential amplifiers, and described method comprises that further the described rough approximation a plurality of reference levels relatively that are identified for described analog input signal are so that used by described second analog-digital converter.

37. differential amplifier, be used to produce and first and second voltages between the electric current of voltage difference linear correlation, described differential amplifier comprises switch, switch input capacitor and linear trsanscondutance amplifier, first plate of switch input capacitor is coupled to the input of trsanscondutance amplifier, second plate of switch input capacitor switchably is coupled to first and second voltages, wherein

Second plate of switch input capacitor is set to optionally be coupled to first voltage, and first plate is set to be maintained at reference voltage so that the switch input capacitor is charged by the output that is coupled to described trsanscondutance amplifier simultaneously; And

Second plate of switch input capacitor is set to optionally be coupled to second voltage, and first plate of switch input capacitor is set to disconnect with the output of trsanscondutance amplifier, allows the electromotive force of first plate to change an amount that is relevant to described voltage difference so that described trsanscondutance amplifier produces the output current with described voltage difference linear correlation.

38. differential amplifier that is used to produce with the electric current of two voltage difference linear correlations, described two voltage differences are first voltage difference between first and second voltages and second voltage difference between third and fourth voltage, described differential amplifier comprises first and second switches, the first and second switch input capacitors and linear trsanscondutance amplifier, first plate of the first switch input capacitor and first plate of second switch input capacitor are coupling in together and are coupled to the input of trsanscondutance amplifier, second plate of the first switch input capacitor is coupled to first switch so that switchably be coupled to first and second voltages, and second plate of second switch input capacitor is coupled to second switch so that switchably be coupled to third and fourth voltage, wherein

Second plate of the first and second switch input capacitors is configured to optionally be coupled respectively to first and tertiary voltage, first plate of the first and second switch input capacitors is set to be maintained at reference voltage by the output that is coupled to described trsanscondutance amplifier simultaneously, so that the described first and second switch input capacitors are charged; And

Second plate of the first and second switch input capacitors is configured to optionally be coupled respectively to the second and the 4th voltage, and first plate of the first and second switch input capacitors is configured to disconnect with the output of described trsanscondutance amplifier, be shared with the electric charge on first plate that allows the first and second switch input capacitors, thereby the electromotive force that makes the plate of winning changes one and depends on described both amounts of first and second voltage differences, so that described trsanscondutance amplifier produces the output current that is linearly related to two described voltage differences.

39. differential amplifier as claimed in claim 38, wherein, the electric capacity of the described first and second switch input capacitors is scaled with described first and second voltage differences of convergent-divergent accordingly.

40. a two-stage analog-digital converter comprises:

First analog-digital converter is used to provide the rough approximation to analog input signal, and

Second analog-digital converter, it comprises at least one differential amplifier, and this differential amplifier is configured to provide the output current that depends on the difference between first input voltage and second input voltage, and described differential amplifier comprises:

Trsanscondutance amplifier, be used to provide described output current to comparator so that numeral output is provided;

At least one switch input sample capacitor, it is coupled to the input of described trsanscondutance amplifier;

At least one feedback switch, it is configured to optionally the output of described trsanscondutance amplifier is coupled to the described input of described trsanscondutance amplifier; And

At least one selector switch, it is configured to described input sample capacitor alternately is coupled to described first and second input voltages, wherein, in use,

Described selector switch is controlled as described input sample capacitor at first is coupled to the aanalogvoltage that is used to change; And

Described feedback switch is controlled as the described input of the output of described trsanscondutance amplifier being coupled to described trsanscondutance amplifier; Then,

Described selector switch be controlled as with described input sample capacitor-coupled to the described rough approximation of described analog input signal so that reference voltage to be provided; And

Described feedback switch is disconnected.

41. two-stage analog-digital converter as claimed in claim 40, wherein the output current of differential amplifier is linearly related to described poor between described first and second input voltages.

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