CN100511195C - Method for implementing two-dimensional data delivery using DMA controller - Google Patents
Method for implementing two-dimensional data delivery using DMA controller Download PDFInfo
- Publication number
- CN100511195C CN100511195C CNB2006100666643A CN200610066664A CN100511195C CN 100511195 C CN100511195 C CN 100511195C CN B2006100666643 A CNB2006100666643 A CN B2006100666643A CN 200610066664 A CN200610066664 A CN 200610066664A CN 100511195 C CN100511195 C CN 100511195C
- Authority
- CN
- China
- Prior art keywords
- register
- address
- source
- dma controller
- address register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
The invention discloses a method for using a DMA controller to realize two-dimension data transmission, which comprises a source address register, a target address register, a boundary register, and a step register. And the method comprises that the DMA controller reads a source address from the source address register, to obtain the data stored in the address and judge if the memory space is the last memory space, or else, according to the value in the step register, calculating the following accessed resource address to be stored in the source address register, if the memory space is the last memory space, jump to the next address of a first memory space to store the address into the source address register. The invention uses two-dimension skip to make DMA controller support two-dimension data transmission.
Description
Technical field
The present invention relates to dma controller method in a kind of computer technology, in particular a kind of method of utilizing dma controller to realize the 2-D data carrying.
Background technology
The basic framework of the dma controller of prior art (Direct Memory Access is hereinafter to be referred as DMA) as shown in Figure 1, it mainly is made up of four modules:
AHB is from the device interface module: this module functions is to be used for disposing dma controller, and external program can be provided with the registers group module of dma controller.
AHB main device interface module: this module can be finished to ahb bus and send address, data and control signal, realizes putting into destination address from the source address reading of data.
The registers group module: this module comprises source address register, target address register, control register and some other relevant register.The initial value of source address register is the start address in the source memory space that will visit, and in handling process, the source address that dma controller will be visited the next one is kept in this register; The initial value of target address register is the start address in the target memory space that will visit, and in handling process, the destination address that dma controller will be visited the next one is kept in this register; Control register is used for setting the DMA passage and enables or do not enable, and whether loads start address or the like automatically.
The passage priority block: this module is used to realize the priority judgement of a plurality of logical channels in the dma controller.When receiving the DMA application, this module will be judged the priority of passage, to determine by which passage being initiated to transmit under present case.
On the ahb bus of AMBA agreement, dma controller is as the main device appearance arranged side by side with arm processor, in most of the cases, dma controller can substitute arm processor and carry out data carrying work (comprise memory to memory, storer to peripherals, peripherals to the carrying of the data between storer and the peripherals), thereby guarantee that arm processor stays out of in the concrete data carrying work during executing instruction, thereby improve the work efficiency of arm processor.
The dma controller of widespread use generally all is the carrying of carrying out one-dimensional data on the ahb bus at present, the source address space or the target address space that are dma controller are one section continuous storage space, have only these main registers of source address register, target address register and control register in the registers group module of this dma controller, in the process of data carrying, only need the address value in source address register or the target address register be increased progressively, just can obtain the storage address that the next one will be visited.
Yet in the operating process of reality, the storage space that tends to occur deposit data is a discontinuous address space, such as time-multiplexed situation in the communication field widespread usage, this moment need be with a plurality of logical channels (a plurality of time slots, each logical channel correspondence a continuous memory address space) on the synthetic complete wireless data sequence of data set, perhaps with the data decomposition in the wireless data sequence on a plurality of logical channels, as shown in Figure 2.Obviously, prior art only supports the dma controller of one-dimensional data carrying can't finish this work.
Therefore, prior art awaits to continue to improve and development.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of method of utilizing dma controller to carry out the 2-D data carrying, overcomes the shortcoming that one-dimensional data carrying dma controller can only be carried the continuation address spatial data.
Technical scheme of the present invention comprises:
A kind of method of utilizing dma controller to realize the 2-D data carrying, described dma controller has source address register, target address register and control register, described dma controller also has source base address register, target base address register, limit register and stride register, and it may further comprise the steps:
A, give each register assignment, successively source address is set in described source address register and the described source base address register, destination address is set in described target address register and the described target base address register, the number and the degree of depth of storage space are set in the described limit register, and the stride of redirect is set in the described stride register;
B, described dma controller take out source address from source address register, obtain the data that preserve this address, and judge whether this storage space is last block storage space, if not, then according to the value in the stride register, calculate the source address that the next one will be visited, be stored in the source address register; If, then to jump to the next address in the first block storage space, this address is stored in the source address register;
Circulation step B carries out the data carrying.
Described method, wherein, also comprise step: C, carried last data in last block storage space, judge the automatic loading position in the control register, if be set to automatic loading, then redirect is the address value of preserving in the base address register of source automatically, and this value is saved in the source address register; If be not set to automatic loading, then handling process finishes.
A kind of method of utilizing dma controller to realize the 2-D data carrying provided by the present invention owing to adopt the method for two-dimentional redirect, has realized dma controller support 2-D data handling process.
Description of drawings
Fig. 1 is the basic framework synoptic diagram of the dma controller of prior art;
Fig. 2 is a plurality of logical channel data combination synoptic diagram in the time-division multiplex communication of prior art;
Fig. 3 is the two-dimentional redirect method of work synoptic diagram of the inventive method;
Fig. 4 is the two-dimentional redirect method of work data carrying process flow diagram of the inventive method.
Embodiment
Below in conjunction with accompanying drawing, will be described in more detail each preferred embodiment of the present invention.
The method of utilizing dma controller to realize the 2-D data carrying of the present invention, it adopts two-dimentional redirect mode, can be applied in time-multiplexed situation, its redirect mode as shown in Figure 3, except the original source address register of dma controller, target address register and control register, increase source base address register, target base address register, limit register, stride register in addition again.Being described below of each register:
The source base address register: this register initial value is the start address in the source memory space that will visit, in handling process, dma controller can not change the value in this register, after the data carrying is finished, if be provided with automatic loading position in control register, then dma controller copies the value in this register to source address register.
The target base address register: the initial value of this register is the start address in the target memory space that will visit, in handling process, dma controller can not change the value in this register, after the data carrying is finished, if be provided with automatic loading position in control register, then dma controller copies the value in this register to target address register.
Limit register: this register is used for setting the degree of depth (representing with row) in total how many piece source memory spaces (representing to be listed as) and these source memory spaces in Fig. 3 in Fig. 3.
The stride register: this register is used for being set in the stride of redirect between the two block storage spaces, and under normal conditions, this stride is that promptly the address in two block storage spaces is continuous with the deep equality of storage space.When the address in two block storage spaces was discontinuous, the value in the stride register and the degree of depth of storage space then were unequal.
The inventive method may further comprise the steps:
A, give register assignment, the number of source address, destination address, storage space and the stride of the degree of depth and redirect are set gradually in the relevant register.
B, when dma controller begins to carry data, at first from source address register, take out source address, obtain the data that preserve this address, judge then whether this storage space is last block storage space, if not, then, calculate the source address that the next one will be visited, be stored in the source address register according to the value in the stride register; If, then to jump to the next address in the first block storage space, this address is stored in the source address register.
Carrying and so forth, up to last data of having carried last block storage space, judge the automatic loading position in the control register this moment, if be set to automatic loading, then redirect is the address value of preserving in the base address register of source automatically, and this value is saved in the source address register; If be not set to automatic loading, then handling process finishes.Concrete data carrying flow process as shown in Figure 4.
By the method for above-mentioned two-dimentional redirect, just can reach the purpose of using dma controller to finish the 2-D data carrying.
Below lift the step that specific embodiment describes the inventive method:
Under the rate matching pattern of communication field, need be with the synthetic complete wireless data sequence of the data set in three time slots, three time slots mean that three source memory spaces are arranged, the start address of supposing the source memory space is 0x00000000, destination address is 0x10000000, the degree of depth in every block storage space is 10, and data width is 32, and the address between piece and the piece is spaced apart 0x04.
At first, give register assignment, with source address 0x00000000 write in source address register and the source base address register, destination address 0x10000000 writes in target address register and the target base address register, the storage space number is 3, the degree of depth is 10 to write limit register, and the stride 0x28 of redirect writes in the stride register.
Dma controller at first takes out source address 0x00000000 (row 1 row 1 in the corresponding diagram 3) from source address register, obtain the data that preserve this address, then according to the value 0x28 in the stride register, calculating the source address that the next one will visit is 0x00000028, is stored in the source address register.
Dma controller takes out source address 0x00000028 (row 2 row 1 in the corresponding diagram 3) from source address register, obtain the data that preserve this address, then according to the value 0x28 in the stride register, calculating the source address that the next one will visit is 0x00000050, is stored in the source address register.
Dma controller takes out source address 0x00000050 (row n capable 1 in the corresponding diagram 3) from source address register, obtain the data that preserve this address, because this address is the 3rd source memory space, be last piece source memory space, therefore next source address need jump to first source memory space, then source address is 0x00000004 (row 1 row 2 in the corresponding diagram 3), and this address is stored in the source address register.
Carrying and so forth, up to last data of having carried last block storage space (the capable n of row n in the corresponding diagram 3), judge the automatic loading position in the control register this moment, if be set to automatic loading, then redirect is the address value of preserving in the base address register of source automatically, and this value is saved in the source address register; If be not set to automatic loading, then handling process finishes.
To sum up; the inventive method has realized the handling process of the 2-D data of discontinuous storage data block; but should be understood that; above-mentioned explanation at specific embodiment is comparatively concrete; can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (2)
1, a kind of method of utilizing dma controller to realize the 2-D data carrying, described dma controller has source address register, target address register and control register, described dma controller also has source base address register, target base address register, limit register and stride register, said method comprising the steps of:
A, give each register assignment, successively source address is set in described source address register and the described source base address register, destination address is set in described target address register and the described target base address register, the number and the degree of depth of storage space are set in the described limit register, and the stride of redirect is set in the described stride register;
B, described dma controller take out source address from source address register, obtain the data that preserve this address, and judge whether this storage space is last block storage space, if not, then according to the value in the stride register, calculate the source address that the next one will be visited, be stored in the source address register; If, then to jump to the next address in the first block storage space, this address is stored in the source address register;
Circulation step B carries out the data carrying.
2, method according to claim 1 is characterized in that, also comprises step:
C, last data in last block storage space have been carried, judge the automatic loading position in the control register, if be set to automatic loading, then redirect is the address value of preserving in the base address register of source automatically, and this value is saved in the source address register; If be not set to automatic loading, then handling process finishes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100666643A CN100511195C (en) | 2006-04-17 | 2006-04-17 | Method for implementing two-dimensional data delivery using DMA controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100666643A CN100511195C (en) | 2006-04-17 | 2006-04-17 | Method for implementing two-dimensional data delivery using DMA controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101059784A CN101059784A (en) | 2007-10-24 |
| CN100511195C true CN100511195C (en) | 2009-07-08 |
Family
ID=38865894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100666643A Active CN100511195C (en) | 2006-04-17 | 2006-04-17 | Method for implementing two-dimensional data delivery using DMA controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100511195C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510183B (en) * | 2009-03-23 | 2011-05-11 | 华为技术有限公司 | Data transportation processing method and apparatus |
| TWI575384B (en) * | 2015-09-04 | 2017-03-21 | 慧榮科技股份有限公司 | Channels controlling device |
| CN108804356A (en) * | 2017-04-26 | 2018-11-13 | 上海寒武纪信息科技有限公司 | Data transmission device and method |
-
2006
- 2006-04-17 CN CNB2006100666643A patent/CN100511195C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101059784A (en) | 2007-10-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9734050B2 (en) | Method and system for managing background operations in a multi-layer memory | |
| US8873284B2 (en) | Method and system for program scheduling in a multi-layer memory | |
| US20080147994A1 (en) | Command scheduling method and apparatus of virtual file system embodied in nonvolatile data storage device | |
| US20140189205A1 (en) | Method and system for managing program cycles in a multi-layer memory | |
| US20140185376A1 (en) | Method and system for asynchronous die operations in a non-volatile memory | |
| US20140189206A1 (en) | Method and system for managing block reclaim operations in a multi-layer memory | |
| CN104090847A (en) | Address distribution method of solid-state storage device | |
| CN103809917A (en) | Method of scheduling tasks for memories and memory system thereof | |
| CN1766850A (en) | Memory card having a storage cell and method of controlling the same | |
| KR20180049148A (en) | Method and system for asynchronous die operations in a non-volatile memory | |
| KR20140050941A (en) | Method for managing data in non-volatile memory device | |
| CN109388486B (en) | Data placement and migration method for heterogeneous memory and multi-type application mixed deployment scene | |
| CN105117285B (en) | A kind of nonvolatile memory method for optimizing scheduling based on mobile virtual system | |
| CN110333827B (en) | Data loading device and data loading method | |
| US11488671B2 (en) | Method, associated memory device and controller thereof for performing programming management | |
| KR20130034450A (en) | Storage device and driving method thereof | |
| CN109656833A (en) | The NameSpace of the non-volatile formula memory of data memory device is planned | |
| CN101606136A (en) | Be embodied as light storage device or/and the computer peripheral equipment of moveable magnetic disc and its implementation by software emulation | |
| CN100511195C (en) | Method for implementing two-dimensional data delivery using DMA controller | |
| CN102279808A (en) | Method and device for managing video memory of embedded equipment | |
| CN101169737A (en) | Task switching control method and computer system | |
| US20070136549A1 (en) | Information processing apparatus, controller and file reading method | |
| CN101504632A (en) | DMA data transmission method and system, DMA controller | |
| CN101059785A (en) | Method for implementing two-dimensional data delivery using DMA controller | |
| CN110618872A (en) | Hybrid memory dynamic scheduling method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20071024 Assignee: SANECHIPS TECHNOLOGY Co.,Ltd. Assignor: ZTE Corp. Contract record no.: 2015440020319 Denomination of invention: Method for implementing two-dimensional data delivery using DMA controller Granted publication date: 20090708 License type: Common License Record date: 20151123 |
|
| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221111 Address after: 518055 Zhongxing Industrial Park, Liuxian Avenue, Xili street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Department of law, Zhongxing building, South hi tech Industrial Park, Nanshan District hi tech Industrial Park, Guangdong, Shenzhen Patentee before: ZTE Corp. |
|
| TR01 | Transfer of patent right |