CN100505765C - Method of multi-channel data processing - Google Patents
Method of multi-channel data processing Download PDFInfo
- Publication number
- CN100505765C CN100505765C CNB031012744A CN03101274A CN100505765C CN 100505765 C CN100505765 C CN 100505765C CN B031012744 A CNB031012744 A CN B031012744A CN 03101274 A CN03101274 A CN 03101274A CN 100505765 C CN100505765 C CN 100505765C
- Authority
- CN
- China
- Prior art keywords
- data
- processing
- channel
- module
- passage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A multi-channel data processing method features that the pulling mode to multi-channel data is designed as an event triggering mode, that is, there is no received data in all channels, the pulling process stops. When the data is received by one or more channel, the pulling process is triggered. During its synchronous processing, only one-class buffer of data is needed. Its advantages are low power consumption of data processing chip and simple processing process.
Description
Technical field
The present invention relates to data communication technology field, relate in particular to a kind of method that realizes that multi-channel data is handled.
Background technology
In data communication, often need handle the incidents such as transmission of interruption and each channel data.For communication system, be used to handle up TPC (through-put power control) data of the demodulation module reception of such data, and 8 interfaces are separate from 8 demodulation mouths.
The multichannel processing procedure that demodulation module adopted as shown in Figure 1, wherein, clk_dm0: represent the serial port clock signal of passage 0 in 8 paths, the clock of 8 passages is with homophase not frequently; Fsm_dm0: represent the demodulated frames frame head index signal of passage 0 in 8 paths, indicate new demodulated frames to send beginning, the minimum interval is 32cycle (clock cycle) between the signal fsm_dm0; Data_dm0: the demodulate frame data of expression passage 0 serial; Dm0～dm7 among the figure represents 8 passages of demodulation mouth respectively; Still carry out data processing at asynchronous clock domain separately at string and 8 passages of conversion portion, be that each circuit-switched data just becomes the data para_data_dm0 of 32 parallel bit wides to continuous 32 Bits Serial data by the shift register of 32 bit wides, therefore in 32 clock cycle of the minimum maintenance of signal para_data_dm0 that clock clk_dm0 rising edge is sampled and obtained.Data effective marker signal data_ready0 among the figure is the pulse signal of 2 clock cycle, adopting 2 clock cycle is to obtain this signal, continuous two signal data_ready0 32 clock cycle of minimum interval in order to guarantee can sample with out of phase synchronised clock cly_sys signal frequently with the clk_dm0 signal.
Synchronous Processing and data in Fig. 2 are separated packet portion, and the data of 8 passages also are to handle respectively.Data handling procedure to one tunnel is as follows: at first with synchronised clock clk_sys signal data_ready0 is adopted rising edge and handle back generation data input indicative signal data_ind0; Suppose that demodulate frame data successively receives always, promptly between double valid data, do not have at interval, because the phase difference between synchronised clock clk_sys and the clk_dm0 always is no more than the skew of a clock cycle near certain value, when differing of two clocks is smaller, when double interval 31cycle may appear in the index signal data_ind0 of synchronizing clock signals after synchronously, and during adjacent two 31cycle 33cycle will inevitably appear one time.
As shown in Figure 3, differ smaller at position 1clk_dm0 signal and clk_sys signal, jump the edge on the clock of clk_sys than jumping on the clock of clk_dm0 along Zao appearance, position 2clk_dm0 signal and clk_sys signal differ skew, jump the edge on the clock of clk_sys than jumping on the clock of clk_dm0 along late appearance, so double data_ind0 is spaced apart 31cycle between position 1 and the position 2, but in the position 2 and 3 of positions clock deviation how under normal circumstances no matter, the double interval of data_ind0 only may 31cycle can not occur again for 32cycle or 33cycle.The data that incident takes place in order to guarantee are not lost, partly need adopt the structure of level 2 cache memory that data are handled as data synchronization processing among Fig. 4, data cached data_para_dm0 and the status register of this buffer memory correspondence put 1 for the first time when the rising edge of clock signal clk_sys and data_ind0 are high level, when the state of level cache be 1 and also the state of L2 cache when being 0 the data conversion storage of level cache to L2 cache.After the data of a certain passage of inquiry gating of back, L2 cache buffer status clear 0.L2 cache partly is the output of this part, and its interface sequence is seen Fig. 3.
Data are separated the transmission frame format of packet portion according to demodulated frames, parse the data content and the address contents of up TPC data, its interface sequence such as Fig. 5.Because the transmission frame length of the demodulating data that receives is 32bit,, 8 tunnel independence demodulation are inserted the circuit-switched data that data transaction becomes loop control so need to produce 8 channel selecting signal dm_sel of a 32cycle circulation primary.The inquiry mode of 8 passages is inquiry mode completely, promptly no matter whether receives data, query script carries out all the time, and referring to Fig. 5, each 0-7cycle of dm_sel signal just inquires about multichannel, and the continuous processing cycle of each passage is fixed as 32cycle.
Therefore, no matter whether receive data in the multi-channel data processing method 6 that prior art adopted, query script carries out all the time, increases chip power-consumption; And in deal with data, 24 cycle of back are in idle condition to have only preceding 8 cycle (because having only 8 passages) in 32 cycle.In addition, the continuous-query processing cycle of each passage is fixed as 32cycle, thus comparatively complicated to the Synchronous Processing of data, must adopt the cache way of level 2 cache memory structure just can guarantee not obliterated data.
Summary of the invention
The purpose of this invention is to provide the method that a kind of multi-channel data is handled, with assurance the data that multichannel receives are handled reliably, and can be reduced the power consumption of data processing, the Synchronous Processing process of reduced data.
The object of the present invention is achieved like this: the method that a kind of multi-channel data is handled comprises:
A, when passage receives data, the channel status sign of this passage is set, specifically comprise: the serial data that this passage receives is gone here and there and conversion process, to convert parallel data to, rising edge at the system synchronization clock collects the processing sign that receives parallel data, receive parallel data, and the parallel data that receives is carried out level cache handle, again the data of handling through level cache are carried out data and unpack processing, produce the data processing sign, according to the channel status sign set of the data processing sign that produces, there are pending data to identify this passage with this passage;
B, generate data query process triggering signal, the multichannel data query process of this signal triggering according to the channel status of a plurality of passages sign;
C, the data that each passage is received are handled, and are upgraded the channel status sign of each passage.
Described step b comprises:
B1, generate data query process triggering signal according to the channel status of a plurality of passages sign, trigger multi-channel data query counts device and begin counting, the data query counter circulates in the number of channels scope and counts;
The channel number of the count value correspondence that b2, specified data query counts device are current, and this passage inquired about has judged whether the input data, if do not import data, and execution in step b3 then, otherwise, execution in step b4;
B3, the data query Counter Value is added 1, and continue execution in step b2;
B4, wait receive new data query process triggering signal, simultaneously execution in step c.
Described step c is: when next stage data processing sign is handled and provided to the data of passage reception, more the channel status of new tunnel identified, to identify pending data such as this passage does not exist.
In the described data query process, from inquire a certain passage have when receiving data to the required processing time of this each passage of passage poll-final be 3 clock cycle.
The device that a kind of multi-channel data is handled, its structure separates packet portion by string and conversion portion, Synchronous Processing and data and multichannel selects the processing section to form, the multi-channel data that receives is separated packet portion and multichannel through string and conversion portion, Synchronous Processing and data successively and is selected the processing section to finish processing to multi-channel data, and described multichannel selects the processing section further to comprise:
Channel status identification module: receive the channel data processing end signal that upper level data processing sign and trigger control module are sent, determine the channel status sign, and this channel status sign is sent to the gating module;
Gating module: receive a plurality of channel status signs that a plurality of channel status identification modules are sent, and determine the channel status information of gating according to the channel number information that the query counts module is sent, produce data query process triggering signal and export to trigger control module and query counts module respectively;
Query counts module: receive the data query process triggering signal that the gating module is sent, the passage of inquiry is counted, and need to determine the channel number information of gating to send to gating module and trigger control module respectively;
Trigger control module: the channel number information of the need gating that data query process triggering signal that reception gating module is sent and query counts module are sent, the passage of gating is carried out the inquiry and the processing of data, and pass through the more channel status sign of new tunnel of channel status identification module.
Described Synchronous Processing and data are separated packet portion and are further comprised:
Rising edge produces circuit: the data processing sign that receiving system clock signal and string and conversion portion are sent produces the data input indicative signal and gives one-level metadata cache processing module;
One-level metadata cache processing module: receive the data input indicative signal that rising edge produces circuit, and string and the data message sent of conversion portion, according to clock signal of system image data and carry out level cache and handle when the data input indicative signal is effective, simultaneously data input signal being latched a clock cycle obtains new data input signal, at last data and new data input signal is exported to data in the lump and separates packet handing module;
Data are separated packet handing module: receive one-level metadata cache processing module and send new data input signal and data and carry out data and unpack processing, and export to multichannel and select the processing section.
Described channel status identification module selects MUX and a register of 1 to form by two 2 that link to each other successively; The gating module is selected 1 MUX and forming with, not gate and two registers of linking to each other with its output by one 8; The query counts module selects 1 MUX, register and 18 input or door to form by two 2; Trigger control module selects 1 MUX and two 1 to 8 decoder to form by one 8.
By technique scheme as can be seen, the present invention has adopted the design philosophy of multi-channel data being handled by Event triggered, has reduced the power consumption when data processing chip carries out the multi-channel data processing; And what among the present invention multichannel data processing is adopted is the method that queuing is handled, the processed continuously long period of channel data is 24 clock cycle for 8 passages, thereby make the Synchronous Processing process of channel data more easy, only need that data are carried out level cache and handle and to meet the demands, reduced the data processing complex degree of data processing chip.
Description of drawings
Fig. 1 is the signal timing diagram of transmission frame;
Fig. 2 is the structural representation of existing multi-channel data processing unit;
Fig. 3 is existing Synchronous Processing and the schematic diagram that unpacks the processing section;
Fig. 4 is for existing Synchronous Processing and unpack the signal timing diagram that the processing section produces and exports;
Fig. 5 is the signal timing diagram that existing multichannel is selected the processing section;
Fig. 6 is the structural representation of multi-channel data processing unit among the present invention;
Fig. 7 is Synchronous Processing among the present invention and the schematic diagram that unpacks the processing section
Fig. 8 is for Synchronous Processing among the present invention and unpack the signal timing diagram that the processing section produces and exports;
Fig. 9 selects the structural representation of processing section for multichannel among the present invention;
Figure 10 selects the physical circuit schematic diagram 1 of processing section for multichannel among the present invention;
Figure 11 selects the physical circuit schematic diagram 2 of processing section for multichannel among the present invention;
Figure 12 selects the physical circuit schematic diagram 3 of processing section for multichannel among the present invention;
Figure 13 selects the physical circuit schematic diagram 4 of processing section for multichannel among the present invention;
Figure 14 selects the signal timing diagram of processing section for multichannel among the present invention.
Embodiment
Core concept of the present invention is the inquiry mode that the inquiry mode to multi-channel data is designed to Event triggered, promptly when each passage does not all have the data of reception, query script stops, when each passage receives data, triggering the multi-channel data query script begins, in the multi-channel data query script to the processing of ranking of the data of each passage, as shown in Figure 6, wherein the processing method and the prior art of string and conversion portion are identical, get final product but then only data are carried out level cache in the processing of Synchronous Processing part.
Now the invention will be further described in conjunction with the accompanying drawings, the device that multi-channel data of the present invention is handled, as Fig. 6, Fig. 7 and shown in Figure 9, comprise string and conversion portion, Synchronous Processing and data separate packet portion and multichannel is selected the processing section, the multi-channel data that receives is successively through string and conversion portion, Synchronous Processing and data are separated packet portion and multichannel and are selected the processing section to finish processing to multi-channel data, the present invention selects processing section and Synchronous Processing and data to separate packet portion at multichannel to have done improvement, wherein, select the processing section to be designed to multichannel queuing processing section described multichannel, this part further comprises:
Channel status identification module: receive the channel data processing end signal that upper level data processing sign and trigger control module are sent, determine the channel status sign, for example receive data then this channel status sign be set to 1, if receive that channel data is handled end signal then this channel status sign is set to 0, and this channel status sign is sent to the gating module;
Gating module: receive 8 channel status signs that 8 channel status identification modules are sent, and determine the channel status information of gating according to the channel number information that the query counts module is sent, produce data query process triggering signal and export to trigger control module and query counts module respectively, carry out the queuing of multi-channel data with the query processing process that triggers multi-channel data by trigger control module and handle, and count by the passage that the query counts module is inquired about the multi-channel data query script;
Query counts module: receive the data query process triggering signal that the gating module is sent, the passage of inquiry is counted, and need to determine the channel number information of gating to send to gating module and trigger control module respectively;
Trigger control module: the channel information of the gating that data query process triggering signal that reception gating module is sent and query counts module are sent, the passage of gating is carried out the inquiry and the processing of data, and pass through the more channel status sign of new tunnel of channel status identification module.
The improved essence of separating packet portion at Synchronous Processing and data is that promptly described Synchronous Processing and data are separated packet portion and further comprised to the wherein improvement of Synchronous Processing part:
Rising edge produces circuit: the data processing sign that receiving system clock signal and string and conversion portion are sent produces the data input indicative signal and gives one-level metadata cache processing module;
One-level metadata cache processing module: receive the data input indicative signal that rising edge produces circuit, and string and the data message sent of conversion portion, according to clock signal of system image data and carry out level cache and handle when the data input indicative signal is effective, simultaneously data input signal being latched a clock cycle obtains new data input signal, at last data and new data input signal are exported to data in the lump and separate packet handing module, because multichannel selection processing section is above-mentioned multichannel queuing processing section among the present invention, therefore, only need in the Synchronous Processing process, carry out the level cache processing and can guarantee that receiving data does not lose;
Data are separated packet handing module: receive one-level metadata cache processing module and send new data input signal and data and carry out data and unpack processing, and export to multichannel and select the processing section, the processing procedure of this module is identical with the processing procedure of prior art.
The device that multi-channel data of the present invention is handled specifically can pass through Figure 10, Figure 11, Figure 12 and circuit diagram shown in Figure 13 to be realized: referring to Figure 10, the present invention can adopt and select for two 21 MUX and a register as the channel status identification module, the channel status sign of recording channel, only provided a paths status indicator module among the figure, other paths status indicator module class seemingly, the Therefore, omited; Referring to Figure 11, adopt and select 1 MUX for one 8 and finish the function of gating module with, not gate and two registers; Referring to Figure 12, adopt the function of selecting for two 2 one Port Multiplier, register and one 8 input or door to finish the query counts module; Referring to figure, 3, adopt and select for one 81 MUX and two 1 to 8 decoder to finish trigger control module.
The embodiment of the method that multi-channel data of the present invention is handled such as Fig. 6, Fig. 7, Fig. 9, Figure 10, Figure 11, Figure 12 and shown in Figure 13, the sequential chart of each signal that relates in the method is referring to Fig. 8 and Figure 14, and this method specifically may further comprise the steps:
Step 1: the data that receive are handled by string and modular converter, and sent to Synchronous Processing and data parse module;
Step 2: when the rising edge of synchronizing clock signals clk_sys and pulse signal data_ind0 are high level, to data-signal data_para_dm0 sampling and make level cache and handle and obtain data-signal data_sync_dm0; Handy register latchs a bat with data input signal data_ind0 and obtains new data input signal data_sync_ind0 simultaneously, and this step is to finish by the rising edge generation circuit and the one-level metadata cache processing module of said apparatus;
Step 3: separate packet handing module by data then and this transmission frame is carried out data unpack processing; Its interface sequence as shown in Figure 8 owing to directly obtain, so just may be 31,32 or 33cycle for the interval of the continuous two groups of data of a certain passage by the data behind buffer memory through the one group of data that unpacks after the processing;
Step 4: behind the treatment step that process string and conversion, Synchronous Processing and data unpack, when having up TPC (transmitting power control) data to send, certain passage produces the pulse signal ut_readyx of a synchronised clock width, be the data effective index signals, wherein x represents corresponding port number, and provides corresponding data-signal data_utx and other information addrx of these data;
Referring to Fig. 7 and Fig. 8,8 circuit-switched data still are 8 the tunnel independently to export, adjacent two demodulated frames of a certain circuit-switched data may send continuously also and may send at interval, if send continuously, then the interval for the continuous two groups of data of a certain passage just may be 31,32 or 33cycle, this just requires the longest gap periods of the double processing in a certain road in 8 road independent datas to finish in the time less than 32 cycle, because begin to this passage poll-final when a certain passage has the data of reception from inquiring, the required processing time of each passage is 3 cycle, as shown in figure 14, so 8 paths are finished dealing with and needed 8*3=24cycle at most, the longest gap periods of the double processing of a certain circuit-switched data is 24cycle; If the time of 8 passages of a circular treatment is during more than or equal to 32cylce, when the data of 8 passages receive and a certain passage when receiving data continuously simultaneously, and receive continuously data the continuous two groups of data of that passage be spaced apart 31cycle, just can obliterated data;
Step 5: produce 8 passages channel status sign separately according to 8 passages data effective index signal ut_readyx separately, and generate data query process triggering signal according to the channel status of 8 passages sign and trigger the multi-channel data query script, when promptly receiving the demodulate frame data of up TPC, the data query process triggering signal triggering query counts module that is generated after treatment by pulse signal ut_readyx begins the queuing work of treatment, and according to count value 8 various states of passage is carried out one group of output signal that gating produces multichannel queuing processing section;
The detailed process of step 5 is as follows: if 8 passages receive data without any a passage, be that free of data query script triggering signal triggers the multi-channel data query script, then trigger control module and the inoperation of query counts module is to reduce the power consumption of data processing chip; After data processing chip resets, when some or several passages have data, the query counts device of query counts module is then pressed the sequential loop counting of 0 ~ 7 (totally 8 passages) under the driving of data query process triggering signal, query script just begins to handle one by one by 0 ~ 7 order from passage 0, and determine whether to receive data according to the channel status of this channel data treatment state of the expression in the status register of each passage correspondence sign, be the channel status sign of expression data processing state as the register state0_ut ~ state7_ut among Figure 10;
When receiving data, be that a certain road signal is 1 o'clock among data effective index signal ready0_ut ~ ready7_ut, then the channel status sign of a corresponding paths puts 1 among channel status sign State0_ut ~ state7_ut, represents that there are pending data in this passage; Data processing end when this passage, be that a certain road signal is 1 o'clock among data processing end signal clr0_ut ~ clr7_ut, and when providing next stage and handle sign ut_ready, it is clear 0 that the channel status of respective channel identifies, and that represents this passage does not exist pending data;
The query counts device of query counts module is in 0 ~ 7 scope inside counting, when the value of query counts device is represented the state of x passage is inquired about during for x under the triggering of data query process triggering signal as the output signal cnt_out_ut of register among Figure 12; If have at least one to be 1 in the channel status of 8 the passage correspondences sign, then among Figure 12 signal cnt_active_ut to equal 1 (be that any equals 1 among state0_ut ~ state7_ut among Figure 12, then cnt_active_ut equals 1), and the state state_ut of current count value correspondence is that 0 hour counter adds 1; If the channel status of 8 passage correspondences sign is the value of 0 hour counter and remains unchanged.
Method of counting provided by the present invention has guaranteed that the value of counter before the data of a certain passage do not provide next stage processing sign is constant.After data processing chip resets, after a certain passage sent data-triggered query counts device, counter was since 0 counting, and the channel status of query counts value respective channel sign, if 8 paths (0 ~ 7) do not receive data, counter remains 0 so.After if data processing chip resets, the x passage no longer receives data after receiving data and providing the data effective index signal for a long time, and then counter count down to x from 0, and keeps this count value.Receive data up to next time, counter just begins to begin to continue to count the channel status sign and the data of inquiring about respective channel by circular order.As shown in figure 13, according to the value of query counts device the channel status sign of 8 passages is selected, and 8 selected one state to produce to go up the pulse signal ut_ready that jumps along triggering by this, promptly next stage is handled sign; This pulse signal identifies clear 0 with the channel status of respective channel when triggering the next stage incident.Select 1 circuit-switched data is selected 1 circuit-switched data simultaneously from 8 tunnel Input Address signal addrx control information according to this count value from 8 road input data signal data_utx simultaneously.If the passage of back does not receive data, the value of counter will keep up to receiving new data so.Under the triggering of incident, handle and be the technical scheme that multi-channel data provided by the present invention is handled according to constantly circulate data that each passage is received of said process.
Claims (6)
1, a kind of method of multi-channel data processing is characterized in that comprising:
A, when passage receives data, the channel status sign of this passage is set, specifically comprise: the serial data that this passage receives is gone here and there and conversion process, to convert parallel data to, rising edge at the system synchronization clock collects the processing sign that receives parallel data, receive parallel data, and the parallel data that receives is carried out level cache handle, again the data of handling through level cache are carried out data and unpack processing, produce the data processing sign, according to the channel status sign set of the data processing sign that produces, there are pending data to identify this passage with this passage;
B, generate data query process triggering signal, the multichannel data query process of this signal triggering according to the channel status of a plurality of passages sign;
C, the data that each passage is received are handled, and are upgraded the channel status sign of each passage.
2, the method for multi-channel data processing according to claim 1 is characterized in that described step b comprises:
B1, generate data query process triggering signal according to the channel status of a plurality of passages sign, trigger multi-channel data query counts device and begin counting, the data query counter circulates in the number of channels scope and counts;
The channel number of the count value correspondence that b2, specified data query counts device are current, and this passage inquired about has judged whether the input data, if do not import data, and execution in step b3 then, otherwise, execution in step b4;
B3, the data query Counter Value is added 1, and continue execution in step b2;
B4, wait receive new data query process triggering signal, simultaneously execution in step c.
3, the method for multi-channel data processing according to claim 1, it is characterized in that described step c is: when next stage data processing sign is handled and provided to the data of passage reception, more the channel status of new tunnel identifies, to identify pending data such as this passage does not exist.
4, the method handled of multi-channel data according to claim 1 is characterized in that in the described data query process, from inquire a certain passage when the data of reception are arranged to the required processing time of this each passage of passage poll-final be 3 clock cycle.
5, a kind of device of multi-channel data processing, its structure separates packet portion by string and conversion portion, Synchronous Processing and data and multichannel selects the processing section to form, the multi-channel data that receives is separated packet portion and multichannel through string and conversion portion, Synchronous Processing and data successively and is selected the processing section to finish processing to multi-channel data, it is characterized in that
Described multichannel selects the processing section further to comprise:
Channel status identification module: receive the channel data processing end signal that upper level data processing sign and trigger control module are sent, determine the channel status sign, and this channel status sign is sent to the gating module;
Gating module: receive a plurality of channel status signs that a plurality of channel status identification modules are sent, and determine the channel status information of gating according to the channel number information that the query counts module is sent, produce data query process triggering signal and export to trigger control module and query counts module respectively;
Query counts module: receive the data query process triggering signal that the gating module is sent, the passage of inquiry is counted, and need to determine the channel number information of gating to send to gating module and trigger control module respectively;
Trigger control module: the channel number information of the need gating that data query process triggering signal that reception gating module is sent and query counts module are sent, the passage of gating is carried out the inquiry and the processing of data, and pass through the more channel status sign of new tunnel of channel status identification module;
Described Synchronous Processing and data are separated packet portion and are further comprised:
Rising edge produces circuit: the data processing sign that receiving system clock signal and string and conversion portion are sent produces the data input indicative signal and gives one-level metadata cache processing module;
One-level metadata cache processing module: receive the data input indicative signal that rising edge produces circuit, and string and the data message sent of conversion portion, according to clock signal of system image data and carry out level cache and handle when the data input indicative signal is effective, simultaneously data input signal being latched a clock cycle obtains new data input signal, at last data and new data input signal is exported to data in the lump and separates packet handing module;
Data are separated packet handing module: receive one-level metadata cache processing module and send new data input signal and data and carry out data and unpack processing, and export to multichannel and select the processing section.
6, multi-channel data processing unit according to claim 5 is characterized in that: the channel status identification module selects MUX and a register of 1 to form by two 2 that link to each other successively; The gating module is selected 1 MUX and forming with, not gate and two registers of linking to each other with its output by one 8; The query counts module selects 1 MUX, register and 18 input or door to form by two 2; Trigger control module selects 1 MUX and two 1 to 8 decoder to form by one 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031012744A CN100505765C (en) | 2003-01-17 | 2003-01-17 | Method of multi-channel data processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031012744A CN100505765C (en) | 2003-01-17 | 2003-01-17 | Method of multi-channel data processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1518312A CN1518312A (en) | 2004-08-04 |
| CN100505765C true CN100505765C (en) | 2009-06-24 |
Family
ID=34281392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031012744A Expired - Fee Related CN100505765C (en) | 2003-01-17 | 2003-01-17 | Method of multi-channel data processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100505765C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103163407B (en) * | 2011-12-13 | 2016-08-24 | 浙江明凯照明有限公司 | A kind of test the conversion method of multiple TCH test channels in system |
| CN105472780B (en) * | 2015-12-28 | 2019-02-22 | 深圳市金溢科技股份有限公司 | A kind of data transmission method and Wide Area Netweork base satation of Wide Area Netweork base satation |
| CN110855894B (en) * | 2019-12-05 | 2020-12-15 | 中科微至智能制造科技江苏股份有限公司 | Image data acquisition method and device |
| CN111858630B (en) * | 2020-07-10 | 2022-06-17 | 山东云海国创云计算装备产业创新中心有限公司 | Data processing method, device and equipment and readable storage medium |
-
2003
- 2003-01-17 CN CNB031012744A patent/CN100505765C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1518312A (en) | 2004-08-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103297055A (en) | Device for achieving multipath serial ADC synchronization by adopting FPGA | |
| CN103141066A (en) | Transmission circuit, reception circuit, transmission method, reception method, communication system and communication method therefor | |
| CN104950770A (en) | Controllable high-speed multi-channel signal acquisition control circuit system and control method thereof | |
| CN110401824A (en) | KVM optical transmission system, the tandem type optical transmitter and receiver, optical interface card of multiplexing | |
| CN104536924A (en) | Multi-channel delay deviation correction method and device for board-level high-speed transmission bus | |
| CN101179372B (en) | Link frame synchronization system and method of digital communication system | |
| US20130208812A1 (en) | High-speed interface for ancillary data for serial digital interface applications | |
| CN100505765C (en) | Method of multi-channel data processing | |
| US5020057A (en) | Easy detection of head position of information data via reception processing unit in synchronous multiplex transmission apparatus | |
| CN112543025B (en) | High-speed serial AD sampling and data processing system and method based on matrixing | |
| JP4544858B2 (en) | Network and method utilizing multiphase encoding protocol | |
| CN105718401B (en) | The multiplexing method and system of a kind of multichannel SMII signals to MII signals all the way | |
| CN102946293A (en) | DS (data strobe) encoding based parallel reception method and device thereof | |
| US20080247496A1 (en) | Early HSS Rx Data Sampling | |
| CN113806277B (en) | FPGA and DSP data transmission system based on SRIO protocol | |
| CN105007151A (en) | High/low-speed bus communication method and device | |
| CN100481913C (en) | Device of asynchronous acquisition for image in real time | |
| CN100533414C (en) | Control system and method of multipath input data | |
| CN106374932A (en) | Decoder and decoding method of dual-mode UHF-RFID reader-writer | |
| CN105389155A (en) | Method and system for receiving TDM audio data by using SPI interface | |
| CN1355631A (en) | Circuit and method for frame location search and code stream conversion | |
| CN201323566Y (en) | Clock recovering system | |
| CN109862210B (en) | Acquisition and receiving system for multi-path and multi-spectral-band serial image data | |
| JP2689508B2 (en) | Multiple information transmission processor for digital protection relay system | |
| CN101630995B (en) | Method for detecting link rate of Ethernet with RMII interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090624 Termination date: 20200117 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |