CN100505300C - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
CN100505300C
CN100505300C CNB2006100738035A CN200610073803A CN100505300C CN 100505300 C CN100505300 C CN 100505300C CN B2006100738035 A CNB2006100738035 A CN B2006100738035A CN 200610073803 A CN200610073803 A CN 200610073803A CN 100505300 C CN100505300 C CN 100505300C
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Prior art keywords
electrode
semiconductor substrate
semiconductor device
backplate
pad
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CN1841767A (en
Inventor
久保博稔
白旗由香利
松本成仁
山室正伦
龟山工次郎
梅本光雄
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/351—Thermal stress

Abstract

This invention relates to a semiconductor device and the method to fabricate the same. Said semiconductor device(20A) in which emitter pad electrodes(23E) connected to an active region(21), collector(23C) and base pad electrodes(23B) are formed on a surface of a semiconductor substrate(25). Furthermore, on a back surface of the semiconductor substrate(25), a backside electrode(26) is formed. Moreover, the emitter pad electrodes (23E)connected to a grounding potential are connected to the backside electrode(26) through feedthrough electrodes(24A) penetrating the semiconductor substrate(25) in a thickness direction.

Description

Semiconductor device and manufacture method thereof
Technical field
The present invention relates to semiconductor device and manufacture method thereof, particularly relate to semiconductor device and manufacture method thereof with the through electrode that connects Semiconductor substrate.
Background technology
Be provided with the circuit arrangement 100 (for example with reference to following patent documentation 1) of existing semiconductor devices 105 in the stereogram explanation with reference to Figure 13.
Circuit arrangement 100 is formed in bonding land (ラ Application De) 112 the mounted on surface that is disposed at central portion the structure of semiconductor device 105.To go between 101B and lead-in wire 101D of 112 two ends derives outside from the bonding land.And then 112 both sides are provided with lead-in wire 101A and 101C in the bonding land.In addition, circuit arrangement 100 integral body are covered by sealing resin 104.
Semiconductor device 105 is a bipolar transistor at this, is formed with emitter electrode, collector electrode and base electrode on its surface.The collector electrode that is formed at semiconductor device 105 surfaces is connected with lead-in wire 101A with lead-in wire 101C via metal fine 103 with base electrode.In addition, the emitter electrode of semiconductor device 105 is connected with bonding land 112 via metal fine 103.At this, two emitter electrodes that are formed at semiconductor device 105 surfaces are connected with bonding land 112 via metal fine 103.In addition, for obtaining voltage gain and current gain, emitter electrode is connected with earthing potential.
Patent documentation 1: the spy opens the 2004-102345 communique
But, in the interior circuit arrangement 100 that is provided with above-mentioned semiconductor device 105, having with semiconductor device 105 and compare, bonding land 112 increases and hinders the problem of circuit arrangement 100 miniaturizations.Specifically, for the emitter electrode with semiconductor device 105 is connected with bonding land 112, and must be in the bonding land 112 periphery guarantee to be used for the zone of wire-bonded metal fine 103.Therefore, be under the situation of 0.3mm * 0.3mm at the planar dimension of semiconductor device 105, the planar dimension of bonding land 112 need be more than or equal to about 1.5mm * 1.5mm.That is, the area that need make bonding land 12 is about 25 times of semiconductor device 105 of institute's mounting, and this has hindered the miniaturization of circuit arrangement 100 integral body.
In addition, have and on metal fine 103, produce the stray inductance composition, make the problem of the high frequency characteristics deterioration of semiconductor device 105.The size of the stray inductance that is produced by metal fine 103 is directly proportional with the length of metal fine 103, is inversely proportional to the thickness of metal fine 103.Therefore, for example if adopt diameter 25 μ m, the long and thin metal fine rule 103 of length 1mm then produces big stray inductance, and the high frequency characteristics of semiconductor device 105 is worsened.Particularly, under the situation of the semiconductor device 105 that moves with high frequency, owing to stray inductance makes high frequency characteristics worsen significantly more than or equal to 1GHz.
Summary of the invention
The present invention puts in view of the above problems and constitutes, and its main purpose is to provide a kind of semiconductor device and manufacture method thereof, helps the miniaturization of device integral body and stray inductance is reduced.
Semiconductor device of the present invention is characterized in that, has: a plurality of pad electrodes, and it is formed at the surface of Semiconductor substrate, is electrically connected with active region; Backplate, it is located at the back side of described Semiconductor substrate; Through electrode, it connects described Semiconductor substrate along thickness direction, and described pad electrode is connected with described backplate, and the described pad electrode of at least one that is connected with earthing potential is connected with described backplate via described through electrode.
In addition, semiconductor device of the present invention is characterized in that, a plurality of described pad electrodes are connected with described backplate via described through electrode.
Semiconductor device of the present invention is characterized in that, forms bipolar transistor at described active region, and the described pad electrode that will be connected with the emitter region of described bipolar transistor is connected with described backplate via described through electrode.
Semiconductor device of the present invention is characterized in that, forms MOSFET at described active region, and the described pad electrode that will be connected with the source region of described MOSFET is connected with described backplate via described through electrode.
Semiconductor device of the present invention, it is characterized in that, the described backplate of described Semiconductor substrate is fixed on the conductive component as bonding land (ラ Application De shape), and the described pad electrode that is connected with earthing potential is connected with described conductive component with described backplate via described through electrode.
Semiconductor device of the present invention is characterized in that, other pad electrode that is not connected with earthing potential is electrically connected with other conductive component via metal fine.
Semiconductor device of the present invention is characterized in that, described backplate directly contacts with the back side of described Semiconductor substrate, and it is idiostatic making described through electrode and described Semiconductor substrate.
Semiconductor device of the present invention is characterized in that, a plurality of backplates are formed at the back side of described Semiconductor substrate, and each described backplate is electrically connected with described pad via described through electrode.
Semiconductor device of the present invention is characterized in that, described backplate utilization covers the dielectric film and the insulation of described semiconductor substrate at the described Semiconductor substrate back side.
Semiconductor device of the present invention is characterized in that, the whole described pad electrode that is connected with described active region is connected with described backplate via described through electrode.
Semiconductor device of the present invention, it is characterized in that, described active region is formed on the inside of separated regional area surrounded, and described through electrode is formed on the through hole inside of the described Semiconductor substrate of perforation in the described separated region outside, and described through electrode contacts with the inwall of described through hole.
In addition, semiconductor device of the present invention is characterized in that, has: Semiconductor substrate, and it has the semiconductor layer that has formed active element; First electrode, it is electrically connected with a diffusion zone of described active element; Pad electrode, itself and described first electrode constitute one, extend to be provided with around Semiconductor substrate; Through electrode, it is located at the lower floor of described pad electrode, extends to the back side of Semiconductor substrate from semiconductor layer surface; Backplate, it is electrically connected with described through electrode, is located at the back side of Semiconductor substrate.
Semiconductor device of the present invention is characterized in that, described active element is BIP type or MOS transistor npn npn, and described first electrode that is electrically connected with the diffusion zone of ground connection is electrically connected with two through electrodes at least.
The manufacture method of semiconductor device of the present invention is characterized in that, has: the operation that is formed with source region at semiconductor substrate surface; Form the operation of the pad that is electrically connected with described active region at described semiconductor substrate surface; Formation will be positioned at the operation of the through hole of the described Semiconductor substrate perforation below the described pad; Form the operation of the backplate that is electrically connected with described pad via the through electrode that is formed at described through hole inside at the described Semiconductor substrate back side, the outside of the separated region that forms surrounding described active region forms described through hole, and the direct butt of inwall of described through electrode and described through hole is formed.
In addition, the invention provides the manufacture method of semiconductor device, it is characterized in that, described separated region has groove structure, locos oxide film or PN junction separated structures.
According to semiconductor device of the present invention, the pad electrode that can will be formed at semiconductor substrate surface via the through electrode of perforation Semiconductor substrate is connected with the backplate that is formed at the Semiconductor substrate back side.Therefore, can not use metal fine and pad electrode is connected with outside via through electrode and backplate.Thus, the bonding land miniaturization that semiconductor device is installed can be arrived the degree identical with semiconductor device, and the also miniaturization of device integral body of establishing semiconductor device in making.
In addition, according to semiconductor device of the present invention, can use and compare the short and thick through electrode in path with metal fine pad electrode is connected with the outside.Thus, even, also can reduce stray inductance, therefore, high frequency characteristics is improved with under the situation for example more than or equal to the semiconductor device of the high frequency of 1GHz action.
In addition,, separate, through electrode can be formed directly in the through hole that connects Semiconductor substrate by active region being carried out element by separated region according to the manufacture method of semiconductor device of the present invention.That is, do not need to use methods such as thermal oxidation method that insulation processing is carried out in through hole inside.Therefore, the heating process of thermal oxidation method of at high temperature heating Semiconductor substrate etc. can be saved, therefore, rate of finished products can be improved.
Description of drawings
Fig. 1 is the figure of expression semiconductor device of the present invention, (A) is stereogram, (B) is profile;
Fig. 2 is the figure of expression semiconductor device of the present invention, (A) is stereogram, (B) is profile;
Fig. 3 is the figure of expression semiconductor device of the present invention, (A) is stereogram, (B) is plane graph;
Fig. 4 is the figure of expression semiconductor device of the present invention, (A) is profile, (B) is plane graph, (C) is profile;
Fig. 5 (A) is the equivalent circuit diagram of semiconductor device of the present invention, (B) is the chart of expression analog result;
Fig. 6 is the figure of the manufacture method of expression semiconductor device of the present invention, (A)～(D) is profile;
Fig. 7 is the figure of the manufacture method of expression semiconductor device of the present invention, and (A) reaching (B) is profile;
Fig. 8 is the figure of the manufacture method of expression semiconductor device of the present invention, and (A) reaching (B) is profile;
Fig. 9 is the figure of the manufacture method of expression semiconductor device of the present invention, (A)～(C) is profile;
Figure 10 is the figure of expression semiconductor device of the present invention, (A) is stereogram, (B) is plane graph;
Figure 11 is the figure of expression semiconductor device of the present invention, (A) is stereogram, (B) is profile, (C) is profile;
Figure 12 is the figure of expression semiconductor device of the present invention, and (A) reaching (B) is profile;
Figure 13 is the stereogram of the existing circuit arrangement of expression.
Symbol description
10A～10E circuit arrangement
11A～11D lead-in wire
12 bonding lands (ラ Application De)
14 sealing resins
15 immobilization materials
16 substrates
20A, 20B, 20C semiconductor device
21 active regions
22 wirings again
23 pad electrodes
23E emitter pad electrode
23C collector electrode pad electrode
23B base stage pad electrode
The 24A through electrode
The 24B through hole
25 Semiconductor substrate
26 backplates
The 27E emitter electrode
The 27C collector electrode
The 27B base electrode
28 silicon semiconductor substrate
29 accept oxidation film layer
30 N ++The type epitaxial loayer
31 N -The type epitaxial loayer
32 oxide-films
33 grooves
34 base regions
36 emitter regions
37 collector regions
38 dielectric films
Embodiment
(first execution mode)
In the manner, has the structure of the semiconductor device of the through electrode that connects Semiconductor substrate with reference to Fig. 1 figure～5 explanations.
Be provided with the structure of the circuit arrangement 10A of semiconductor device 20A of the present invention in illustrating with reference to Fig. 1.Fig. 1 (A) is the stereogram of circuit arrangement 10A, and Fig. 1 (B) is the profile of semiconductor device 20A.
With reference to Fig. 1 (A),, be provided with semiconductor device 20A in lead frame type circuit arrangement 10A at this.Specifically, on the bonding land 12 that is disposed at central portion, be fixed with semiconductor device 20A.In addition, 12 end extends to the outside with two lead-in wire 11D and lead-in wire 11B from the bonding land.In addition, be provided with lead-in wire 11A and lead-in wire 11C near bonding land 12.Bonding land 12 and lead-in wire 11A etc. are one of the conductive component example.As conductive component, also can be the conductive pattern shown in Fig. 2 (A) and Fig. 2 (B).
12 top is fixed with semiconductor device 20A via conductivity adhesivess such as scolding tin in the bonding land.Four pad electrodes 23 are formed at the top at semiconductor device 20A, and at this, two pad electrodes 23 are electrically connected with bonding land 12 via through electrode 24A.In addition, other two pad electrodes 23 are connected with lead-in wire 11A, 11C via metal fine 13 respectively.
The through electrode 24A that is located on the semiconductor device 20A also can be made of the membranaceous metal that is formed in the through hole that Semiconductor substrate 25 is connected.In addition, also can be by filled with metal such as scolding tin, W, Cu or A1 are formed through electrode 24A in through hole.
Lead-in wire 11A is connected with the pad electrode 23 of semiconductor device 20A via metal fine 13 with lead-in wire 11C.At this, the pad electrode 23 that is connected with collector electrode and base electrode is connected with lead-in wire 11C with lead-in wire 11A via metal fine 13.
Sealing resin 14 is exposed under the outside state integral sealing in a part that makes lead-in wire 11A, 11B, 11C, 11D.
With reference to Fig. 1 (B), secondly the semiconductor device 20A on the bonding land 12 is fixed in explanation.This semiconductor device 20A is formed with active region 21 on the surface of Semiconductor substrate 25.At this, active region 21 normally forms the zone of active elements such as transistor or diode.Be formed with at active region 21 under the situation of bipolar transistor, form collector region, base region, emitter region.In addition, form under the situation of MOSFET, form area of grid, source region, drain region at active region 21.In addition, on active region 21, also can form IC and LSI.And the pad electrode 23 that is electrically connected with diffusion zone on being formed at this active region 21 is via 22 surfaces that are formed on Semiconductor substrate 25 of connecting up again of extending around above-mentioned active region 21.In addition, at the back side of Semiconductor substrate 25, on a part, form backplate 26 at least.At this, because the back side applied flexibly and be emitter electrode, so on whole, be formed with backplate 26.In addition, form the through electrode 24A that connects Semiconductor substrate 25 along thickness direction, make it arrive the back side of pad electrode 23.
At this, also can carry out insulation processing to the back side of Semiconductor substrate 25.In addition, through electrode 24A and Semiconductor substrate 25 also can insulate by the Si oxide-film that for example thermal oxidation or CVD obtain.
In addition, the backplate 26 of semiconductor device 20A is fixed on the surface of bonding land 12 via immobilization material 15.Immobilization material 15 can adopt scolding tin and conductive paste etc.At this, because bonding land 12 is fixed potential (GND or Vcc), so pad electrode 23 is connected with fixed potential.Thus, desirable electrode stable current potential can be fixed on, therefore, the transistorized action stabilisation that is formed on the active region 21 can be made.
For example, emitter, collector electrode, base electrode are connected with lead-in wire via metal fine at present.But formation can not be ignored the size of the impedance of metal fine.In the present invention, owing to replace metal fine to adopt through electrode 24A, therefore, its path is also short, and impedance is reduced.And, even flow through under the situation of big electric current,, can reduce the impedance in the path that is connected with emitter electrode as long as increase the diameter of through electrode 24A.Therefore, compare, its characteristic is significantly improved with the encapsulation that is connected emitter electrode by metal fine.
With reference to Fig. 2, next illustrates the circuit arrangement 10B of alternate manner and the structure of 10C.Fig. 2 (A) is the profile with circuit arrangement 10B of circuitry substrate 19, and Fig. 2 (B) is the profile with the circuit arrangement 10C that is embedded to conductive pattern 18A, 18B in the sealing resin 14.
With reference to Fig. 2 (A), in circuit arrangement 10B, the conductive pattern 18A, the 18B that are formed at circuitry substrate 19 surfaces are electrically connected with semiconductor device 20A.As circuitry substrate 19, the substrate and the ceramic substrate that can all adopt flex plate or printed substrate etc. to constitute by resin.The conductive pattern 18A that is formed at circuitry substrate 19 surfaces is connected with semiconductor device 20A via metal fine 13.Conductive pattern 18B is connected with the backplate 26 of semiconductor device 20A via immobilization materials such as scolding tin 15.In addition, conductive pattern 18A, 18B are connected with the conductive pattern that is formed at circuitry substrate 19 back sides via the through hole that is formed on the circuitry substrate 19.In addition, form sealing resin 14, to cover semiconductor device 20A and metal fine 13 on the surface of circuitry substrate 19.
In circuit arrangement 10B, needn't use metal fine that conductive pattern 18B is connected with semiconductor device 20A by adopting through electrode 24A, therefore, can make the size of conductive pattern 18B be reduced to equal extent with semiconductor device 20A.Therefore, the overall dimensions of circuitry substrate 19 can be reduced.
With reference to Fig. 2 (B), in circuit arrangement 10C, the conductive pattern 18A, the 18B that are embedded in the sealing resin 14 are electrically connected with semiconductor device 20A.Conductive pattern 18A, 18B imbed in the sealing resin 14 under the state that the back side is exposed.In addition, the conductive pattern 18A that exposes from sealing resin 14, the back side of 18B except that the part that forms scolder, cover by coated with resin 45.In addition, conductive pattern 18A is separated by separating tank 44 with conductive pattern 18B.This structure can followingly realize, for example pastes patterns such as lead frame on flex plate, installs, molded, then flex plate peeled off.In addition, can followingly realize, prepare the Cu paper tinsel, the prominent shape ground of conductive pattern is residual and etch partially, to install, molded, the back side of the above-mentioned Cu paper tinsel of etching then is so that the sealing resin of filling in the groove that has etched partially exposes.
Secondly, the structure of semiconductor device 20A is described with reference to Fig. 3 and Fig. 4.Fig. 3 (A) is the stereogram of semiconductor device 20A, and Fig. 3 (B) is the plane graph of the semiconductor device 20A that sees from the top.Fig. 4 (A) is the profile of semiconductor device 20A, and Fig. 4 (B) is the plane graph of the mode pattern of expression active region 21.The structure of the semiconductor device 20B of Fig. 4 (C) expression alternate manner.
With reference to Fig. 3 (A) and Fig. 3 (B), the central portion on Semiconductor substrate 25 surfaces is formed with source region 21.And the periphery on Semiconductor substrate 25 surfaces is formed with collector electrode pad electrode 23C, base stage pad electrode 23B and emitter pad electrode 23E.Each pad electrode and active region 21 22 are connected by connecting up again.
At this, because semiconductor device 20A is used in earthed-emitter circuit, so emitter pad electrode 23E is connected with backplate 26 via through electrode 24A.Therefore, when semiconductor device 20A was used in grounded-base circuit, base stage pad electrode 23B was connected with backplate 26 via through electrode 24A.In addition, when semiconductor device 20A was used in rgounded-collector circuit, collector electrode pad electrode 23C was connected with backplate 26 via through electrode 24A.In the manner, adopt through electrode 24A to reduce impedance.In addition, owing to adopt two through electrode 24A, so through electrode 24A becomes connection arranged side by side, its impedance reduces by half.That is, if an electrode is connected side by side via n (more than three or three) through electrode 24A, then impedance becomes 1/n.
In addition, on active region 21, also can form bipolar transistor for example MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) in addition.At this moment, the pad electrode that is connected with earthing potential (any in drain electrode, source electrode or the gate electrode) is connected with backplate 26 via through electrode 24A.When particularly using circuit arrangement 20 in the big source ground circuit of gain, the pad that is connected with source electrode is connected with backplate 26 via through electrode 24A.At this,, can reduce impedance by adopting a plurality of through electrode 24A.
Describe the active region 21 that is formed with active element in detail with reference to Fig. 4 (A).Top at P type semiconductor substrate 42 is provided with N + Type embedding layer 43, and form N thereon -Type epitaxial loayer 31 (semiconductor layer).And then at N -The surface of type epitaxial loayer 31 forms P +Type extrinsic base zone 34A, P type activate base region 34B, N +Type collector contact zone 37.In addition, be formed with N type emitter region 35 (diffusion zone) on the top of activating base region 34B.In addition, N +Type collector contact zone 37 is from N -The surface of type epitaxial loayer 31 is formed into N + Type embedding layer 43.
Groove 33 is from N -The surface of type epitaxial loayer 31 extends to P type semiconductor substrate 42, and portion is embedded with oxide-film 32 within it.Be surrounded by source region 21 and form the separated region that constitutes by groove 33, active region 21 elements are separated.At this, by the groove structure active region 21 is separated, but also can separate active region 21 is separated by LOCOS (Local Oxidation of Silicon) oxide-film or PN junction.In addition, form the structure that oxide-film is also imbedded polysilicon therein, also can carry out element and separate by surface at groove 33.
Emitter pad electrode 23E (first electrode) is formed at the position in the outside of groove 33, is connected with backplate 26 via through electrode 24A.
Through electrode 24A connects P type semiconductor substrate 42, N by being embedded to - Type epitaxial loayer 31 and oxide-film 32 and electric conducting material in the through hole that forms constitutes.By through electrode 24A emitter pad electrode 23E is connected with backplate 26.Through electrode 24A can form by the electroplated film that becomes one with backplate 26.This electroplated film is formed at the back side of the sidewall and the P type semiconductor substrate 42 of through hole.In addition, be formed with the side wall insulating film 41 that constitutes by silicon oxide film etc. in the side of through electrode 24A.
P type semiconductor substrate 42 is owing to separate with active region 21 by groove 33, embedding layer 43, so also can not form side wall insulating film 41 between P type semiconductor substrate 42 and through electrode 24A.For example, forming the P that connects epitaxial loayer 31 +Type separated regions etc., and P type semiconductor substrate 42 is fixed as GND when emitter electrode is fixed as current potential beyond the GND, need dielectric film.That is, at the current potential of P type semiconductor substrate 42 and emitter electrode not simultaneously, need side wall insulating film 41.
At this, also can form through electrode 24A by alloys such as filling scolding tin, W, Cu or A1 in through hole or metal.Particularly when forming the through electrode 24A that is made of Cu, preferably the voltage barrier film that is made of Ti/TiN laminated film, Ta/TaN laminated film is protected the surface of through hole.
Backplate 26 forms at the back side of P type semiconductor substrate 42, and 24A is connected with through electrode.Backplate 26 and P type semiconductor substrate 42 insulate via dielectric film when Semiconductor substrate 42 is not separated with active region 21 electricity.In addition, Semiconductor substrate 42 and active region 21 are by groove 33 and P type semiconductor substrate 42 and N +When type embedding layer 43 electricity separate, also can make the directly back side of contact P type semiconductor substrate 42 of backplate 26.
By backplate 26 is directly contacted with P type semiconductor substrate 42, can reduce the parasitic capacitance that produces between P type semiconductor substrate 42 and the through electrode 24A.Specifically, if it is side wall insulating film 41 that insulator is set, then produce the parasitic capacitance that potential difference causes between P type semiconductor substrate 42 and through electrode 24A.By the backplate 26 that is electrically connected with through electrode 24A is directly contacted with P type semiconductor substrate 42, can make through electrode 24A and P type semiconductor substrate 42 for idiostatic, and above-mentioned parasitic capacitance is reduced.
Further specify the structure of active region 21 with reference to Fig. 4 (B).In addition, Fig. 4 (A) is the cross section of A-A ' line of Fig. 4 (B).At this, in by groove 33 area surrounded, be formed with active region 21.In the inside of active region 21, lengthways form two emitter regions 35, and form activation base region 34B, make it surround this emitter region 35.Therefore, emitter electrode 27E is formed by two broach, 22 is connected with the emitter pad electrode 23E of the upper left and bottom right of chip via connecting up integratedly from this emitter electrode 27E again.On the other hand, base electrode 27B and extrinsic base zone 34A contacts, and as being formed by two broach with emitter electrode 27E alternate configurations, 22 is connected with the base stage pad electrode 23B of chip lower-left via connecting up again.In addition, collector electrode 27C contacts with the collector contact zone 37 that arrives embedding layer 43, forms in the left side of active region 21.And collector electrode 27C is connected via the 22 collector electrode pad electrode 23C upper right with being formed at chip that connect up again.
In the present embodiment, pad electrodes such as emitter pad electrode 23E are arranged on the outside as the groove 33 of separated region.It is the reasons are as follows:
The first, even form through electrode 24A in emitter, base stage, collector region, these regional width also can be for 1 μ m or below it.The problem of the contraposition when therefore, producing formation through electrode 24A etc.The second, if on active region 21 or near it, dispose pad electrode, then on element, produce parasitic capacitance etc.Therefore, form enough big pad electrode, form through electrode 24A, obtain all good structure of manufacture method and characteristic at its back side by the outside at separated region.
The structure of the semiconductor device 20B of alternate manner is described with reference to Fig. 4 (C).The basic structure of semiconductor device 20B is identical with above-mentioned semiconductor device 20A, and difference is to have omitted side wall insulating film 41 (with reference to Fig. 4 (A)).
Specifically, the inwall of through hole 24B is not covered by side wall insulating film 41 as described above.Therefore, the direct butt of sidewall of the through electrode 24A that constitutes by electric conducting materials such as copper and the through hole 24B that constitutes by semiconductor.Thus, can make the designs simplification of semiconductor device 20B.In addition, owing to can save the operation of making side wall insulating film 41, the manufacturing cost of semiconductor device 20B is reduced.
The active region 21 that is formed with bipolar transistor is surrounded by groove 33, separates with other regional electricity.In addition, through electrode 24A is positioned at by the outside of groove 33 area surrounded.Therefore, active region 21 is separated by groove 33 electricity with through electrode 24A.Thus, even through electrode 24A and Semiconductor substrate 42 direct butts, active region 21 and through electrode 24A can short circuits yet.
Secondly, be illustrated as the effect of confirming the manner and the analog result of carrying out with reference to Fig. 5.Fig. 5 (A) is provided with the equivalent electric circuit as the circuit arrangement of the semiconductor device 20A of bipolar transistor in being.Fig. 5 (B) is the chart of the frequency characteristic of expression semiconductor device.
With reference to Fig. 5 (A), and produce stray inductance in the path that each electrode of the bipolar transistor that uses is connected in earthed-emitter circuit.At this, making the stray inductance in the path that is connected with base electrode is Lb, and making the stray inductance in the path that is connected with collector electrode is Lc, and the stray inductance that makes the path that is connected with emitter electrode is Le.In addition, between transistorized each electrode, produce the parasitic capacitance of regulation.
In the manner, replace the metal fine that is connected with the emitter pad electrode by using the through electrode 24A that connects Semiconductor substrate, above-mentioned Le is reduced.At this, will use the Le of the conventional example of metal fine to be assumed to be 1.0nH, with the Le that uses the manner of through electrode 24A be assumed to be existing half be 0.5nH.In addition, the value that makes other stray inductance and parasitic capacitance is identical in conventional example and the manner, measures the variation of forward transmission gain with respect to frequency change.
With reference to Fig. 5 (B) analog result of being undertaken by above-mentioned condition is described.The transverse axis of this chart is represented frequency, and the longitudinal axis is represented forward transmission gain.The result who is undertaken by existence conditions is illustrated by the broken lines, and the result who is undertaken by the application's condition is represented by solid line.
Can understand from this chart, use the semiconductor device of the manner that through electrode is arranged particularly to have the conventional example of metal fine to compare in high-frequency region and use, forward transmission gain increases.Specifically, be the lower frequency region of 100MHz in frequency, the transmission gain of the semiconductor device of the manner and existing roughly the same (about 30dB).And when frequency rose, the manner and existing transmission gain all reduced.This be because, corresponding to the increase of frequency, above-mentioned parasitic capacitance and stray inductance increase.But, use the semiconductor device of the manner that through electrode is arranged to compare with conventional example, with the increase of frequency, the reduction of transmission gain is little.For example at the frequency band of 1GHz (1000MHz), the transmission gain of the manner is better than the conventional example of 2～2.5dB degree.Therefore, the semiconductor device of the manner particularly can improve its characteristic at high-frequency region.
The following describes the advantage of the manner.
With reference to Fig. 3, in the manner, be connected with backplate 26 by the emitter pad electrode 23E that will be connected with earthing potential via through electrode 24A, can reduce the stray inductance in the path that is connected with emitter electrode.
Specifically, emitter pad electrode 23E is connected with the bonding land that is positioned at backplate 26 belows (not shown) via through electrode 24A.Therefore, emitter electrode 23E is connected with the shortest path that connects Semiconductor substrate 25 with not shown bonding land.In addition, through electrode 24A compares with metal fine, and its diameter is very thick.Specifically, the diameter of metal fine is 20 μ m, and length is 1mm, and the diameter of through electrode 24A is 70 μ m, and length is 150 μ m.As mentioned above, the size of stray inductance is directly proportional with path, is inversely proportional to the pathway thickness.Thus, compare, in the manner,, the stray inductance in the path that is connected with emitter electrode is significantly reduced by using the short and thick through electrode 24A in path with the conventional example of using metal fine to be connected.Therefore, particularly when semiconductor device 20A carried out switch in 1GHz and the high frequency more than the 1GHz, the characteristic of using through electrode 24A to obtain was improved effect and is become big.
Also can use through electrode 24A that the pad electrode (collector electrode pad electrode 23C or base stage pad electrode 23B) beyond the emitter pad electrode 23E is connected with backplate 26.But when via through electrode 24A collector electrode pad electrode 23C being connected with backplate 26, then the length of the wiring that is connected with collector electrode increases, and the parasitic capacitance between collector electrode, base stage increases, and makes the high frequency characteristics deterioration.Equally also we can say, base stage pad electrode 23B is connected with backplate 26 via through electrode 24A.Therefore, as mentioned above, use through electrode 24A to connect emitter pad electrode 23E, other base stage pad electrode 23B preferably uses metal fine to be connected with outside with collector electrode pad electrode 23C.
And then with reference to Fig. 1, according to the manner, because semiconductor device 20A reduces bonding land 12 relatively, so can be with circuit arrangement 10A integral miniaturization.Specifically, the pad electrode 23 that is formed at semiconductor device 20A surface is connected via the through electrode 24A that connects Semiconductor substrate 25 with bonding land 12.That is, not relying on metal fine is connected pad electrode 23 with bonding land 12.Therefore, need be in the bonding land 12 surfaces be provided for the zone of wire-bonded metal fine.Thus, can make the size of bonding land 12 and semiconductor device 20A roughly the same.In fact, the offset when considering fixing semiconductor device 20A makes bonding land 12 bigger slightly than semiconductor device 20A.For example, the length of side L1 of semiconductor device 20A is 0.3mm, and a length of side L2 of bonding land 12 is about 0.4mm.Therefore, compare with conventional example, the length of side that can make bonding land 12 is about 1/3.
(second execution mode)
Secondly, with reference to the manufacture method of the semiconductor device 20A of the structure of Fig. 6～Fig. 8 key diagram 4 (A) expression.The method of the active region 21 that formation is made of bipolar transistor at first, is described with reference to Fig. 6.
With reference to Fig. 6 (A), at first, P type semiconductor substrate 42 surfaces about thickness 600 μ m are provided with N by ion implantation +Type embedding layer 43.And then on P type semiconductor substrate 42, form N -Type epitaxial loayer 31.N -The thickness of type epitaxial loayer 31 is about 1.5 μ m.Then, by with whole oxidation, at N -Form the oxide-film 32 of about 0.05 μ m thickness above the type epitaxial loayer 31.
With reference to Fig. 6 (B), secondly, encirclement is scheduled to the active region that forms and is formed groove 33, at these groove 33 inner filling oxide-films.At this, utilize photoetching technique selectively to remove oxide-film 32 and the N that forms groove 33 places -Type epitaxial loayer 31.CF is used in removing of oxide-film 32 4Class gas carries out.N -The dry-etching of removing by having used halogen gas of type epitaxial loayer 31 carries out.Groove 33 needs to arrive P type semiconductor substrate 42.The concrete degree of depth of groove 33 for example is about 3.5 μ m.After forming groove 33,, imbed the inside of groove 33 by oxide-film 32 by carrying out oxidation processes.At this, also can replace groove 33, separate by locos oxide film or PN junction.
With reference to Fig. 6 (C), secondly, by ion injection formation collector contact zone 37, extrinsic base zone 34A and activation base region 34B.Collector contact zone 37 is formed into N + Type embedding layer 43 adopts phosphorus (P) as ion species.In addition, inject, form P by carrying out ion +Type extrinsic base zone 34A and P type activate base region 34B.Adopt boron (B) as forming extrinsic base zone 34A and activating the ion species that base region 34B will inject.
With reference to Fig. 6 (D), secondly,, the peristome about diameter 0.5 μ m is set by oxide-film 32 parts are removed, form emitter electrode 27E, base electrode 27B and collector electrode 27C.At this, emitter region 35 forms by making the arsenic ion diffusion in the polysilicon that constitutes emitter electrode 27E.The following formation of these electrodes is piled up Ti, Pt and Au in turn by vacuum evaporation, is etched with to obtain desirable shape.Emitter electrode 27E forms as emitter pad electrode 23E in the outside of groove 33.In addition, collector electrode 27C also forms as collector electrode pad electrode 23C in the outside of groove 33.In addition, not shown among the figure, but base electrode 27B also forms as the base stage pad electrode in the outside of groove 33.After forming each electrode, for the protection wiring portion covers each electrode by dielectric film.
In addition, after above-mentioned operation finishes, carry out etching, the thickness of P type semiconductor substrate 42 is become about 100 μ m.
In the above description, be formed with active region, but also can be formed with source region at the semiconductor substrate surface of non-doping on the surface of P type semiconductor substrate 42.At this moment, the semiconductor substrate surface of non-doping is covered by silicon oxide film, is formed with source region on the semiconductor layer that is piled up on this silicon oxide film.
Secondly, with reference to Fig. 7 and Fig. 8, the operation of using through electrode 24A that emitter pad electrode 23E is connected with backplate 26 is described.
With reference to Fig. 7 (A), at first, the back side of P type semiconductor substrate 42 is covered by resist 40, resist 40 will with the corresponding area part ground opening in emitter welding disking area 23E below.
With reference to Fig. 7 (B), secondly, be mask with resist 40, with P type semiconductor substrate 42 dry-etchings such as grade, form about thickness 70 μ m thus, the through hole 24B about length 150 μ m.As the etching gas that uses in the dry-etching, use and contain SF at least 7, O 2Or C 4F 8Gas.By this operation, through hole 24B is exposed at the back side of emitter pad electrode 23E.The concrete shape of through hole 24B both can also can be flat column for cylindric.In addition, the formation of through hole 24B also can use Wet-type etching or laser to carry out.
At this, if with grinding back surface, plasma etching or etching solution (ウ エ Star ト) combination, attenuate Semiconductor substrate 42 and form through hole 24B then can shorten etching period.For example, grind by grinding back surface from the back side and to cut Semiconductor substrate 42, if by plasma or etching solution remove grind cut formed concavo-convex.In addition, also can only remove Semiconductor substrate 42 from the back side by Wet-type etching or plasma etching.
With reference to Fig. 8 (A), secondly, at the sidewall formation side wall insulating film 41 of through hole 24B.The material of side wall insulating film 41 can adopt silicon oxide film, silicon nitride film or resin molding.By cover the sidewall of through hole 24B by side wall insulating film 41, can make electric conducting material and P type semiconductor substrate 42 insulation of filling in through hole 24B.
In the manufacture method of side wall insulating film 41, at first, utilize by SiO 2The dielectric film that film and SiN film constitute covers the whole back side of the P type semiconductor substrate 42 that comprises through hole 24B inwall.These dielectric films are for example formed by plasma CVD.In addition, by this dielectric film being removed,, the dielectric film of other parts is removed at the remaining side wall insulating film 41 of sidewall of through hole 24B by anisotropic etching.That is, the dielectric film that covers the emitter pad electrode 23E back side and P type semiconductor substrate 42 back sides is removed.In addition, under the situation that makes predetermined backplate that forms and 42 insulation of P type semiconductor substrate, also can be at the remaining oxide-film in the back side of P type semiconductor substrate 42.
With reference to Fig. 8 (B), secondly, form metal film with the inwall of covering through hole 24B and the back side of P type semiconductor substrate 42.The metal film that is formed at through hole 24B inside constitutes through electrode 24A, and the metal film that is formed at P type semiconductor substrate 42 back sides constitutes backplate 26.The formation of through electrode 24A and backplate 26 can be undertaken by plating processing or sputter.Handling by plating when forming backplate 26, at first, the inculating crystal layer (not shown) that constitutes by the Cu of the hundreds of nm degree of thickness in whole formation at the back side of the inwall of through hole 24B and P type semiconductor substrate 42.At this, preferred electroless plating applies.Secondly, by carrying out, form at the back side of the inwall of through hole 24B and P type semiconductor substrate 42 by thickness and count the metal film that the Cu of μ m degree constitutes the electrolysis plating of this inculating crystal layer as electrode.Thus, form the backplate 26 that is electrically connected with emitter pad electrode 23E via through electrode 24A.
At this, the inside of through hole 24B is handled the Cu form and is imbedded fully by plating, but this imbed also can be incomplete.That is, also can the cavity be set in the inside of through hole 24A.In addition, the method beyond also can being handled by plating be that sputtering method etc. forms backplate 26.
In addition, also can form through electrode 24A by the metal material beyond the electroplated film.That is,, also can form through electrode 24A by in through hole 24B, imbedding metals such as scolding tin, W, Cu or Al.
After above-mentioned operation finishes, by utilizing line each layer on p N-type semiconductor N substrate 42 and top thereof cut apart, finish semiconductor device 20A shown in Figure 3.In addition, via little chip bonding, wire-bonded, resin-sealed operation, finish circuit arrangement 10A shown in Figure 1.
In the above description, through electrode 24A only is formed on the below of emitter pad electrode 23E, but when collector electrode pad electrode 23C also is connected with backplate 26, below collector electrode pad electrode 23C through electrode 24A is set also.At this moment, also backplate 26 is patterned into the pattern of regulation.
In addition, in the above description, backplate 26 directly with the back side butt of Semiconductor substrate 41, but also can cover, in this dielectric film surface formation backplate 26 by the back side of dielectric film with Semiconductor substrate 42.
(the 3rd execution mode)
In the present embodiment, with reference to the manufacture method of the semiconductor device 20B of the structure shown in Fig. 9 key diagram 4 (C).The manufacture method of the manner second execution mode with above-mentioned basically is identical, and difference is that the inwall at through hole 24B does not form side wall insulating film.
Specifically, with reference to Fig. 9 (A), at first, form the active region 21 that for example constitutes by bipolar transistor.And then, form groove 33 by being surrounded by source region 21, thus active region 21 elements are separated.Except that groove 33, also can use PN junction separation and locos oxide film to carry out the separation of active region 21.In addition, form the electrode that is connected with each zone that constitutes source region 21 on the surface of oxide-film 32.At this, emitter pad electrode 23E and collector electrode pad electrode 23C are formed at the outside by groove 33 area surrounded on oxide-film 32.
With reference to Fig. 9 (B), secondly, form the through hole 24B that connects P type semiconductor substrate 42 grades.The back side of P type semiconductor substrate 42 is except that the zone of predetermined formation through hole 24B, and the resist 40 that is used as the etch resistant mask covers.Under this state,, form the through hole 24B that connects P type semiconductor substrate 42, epitaxial loayer 31 and oxide-film 32 by from back side dry-etching P type semiconductor substrate 42.By this operation, through hole 24B is exposed at the back side of emitter pad electrode 23E.
With reference to Fig. 9 (C), secondly, form through electrode 24A in the inside of through hole 24B, form backplate 26 at the back side of P type semiconductor substrate 42.In the manner, because being insulated film, the inwall of through hole 24B covers, so the electric conducting materials such as copper of formation through electrode 24A are direct and the inwall butt of through hole 24B.In other words, through electrode 24A and P type semiconductor substrate 42 and epitaxial loayer 31 conductings.But active region 21 is separated by groove 33 elements as mentioned above, and through electrode 24A is positioned at the outside of groove 33.Therefore, do not cover even the side of through electrode 24A is not insulated film, through electrode 24A and active region 21 can short circuits yet.
By above-mentioned operation, the semiconductor device 20B of the structure of shop drawings 4 (C) expression.
According to the manner, owing to do not form the dielectric film that is made of silicon oxide film etc. at the inwall of through hole 24B, the operation that therefore can form this dielectric film is omitted, and can improve rate of finished products.
Specifically, form in the situation of silicon oxide film, form oxide-film by thermal oxidation method or CVD method at the inwall of through hole 24B.But, in these methods that form oxide-film, P type semiconductor substrate 42 is heated to for example about 1000 ℃.Therefore, because P type semiconductor substrate 42 is exposed under the excessive temperature, thereby, produced the problem that emitter pad electrode 23E etc. peels off from oxide-film 32 to being formed at the electrode effect thermal stress of substrate surface.
In the manner, owing to do not form dielectric film, therefore, the process number of the heating of following above-mentioned thermal oxidation method etc. is reduced at the inwall of through hole 24B.Therefore, owing to can prevent the deterioration of emitter pad electrode 23E that thermal stress causes etc., so the raising of the rate of finished products of manufacturing process.In addition, owing to subdue process number, thus also can reduce manufacturing cost.
(the 4th execution mode)
In the present embodiment, the semiconductor device 20C of alternate manner is described and has the structure of the circuit arrangement of this device with reference to Figure 10～Figure 12.Here among Shuo Ming the semiconductor device 20C, a plurality of pad electrodes that are formed at Semiconductor substrate 25 surfaces are connected with the backplate that is formed at Semiconductor substrate 42 back sides via through electrode 24A.In addition, form a plurality of backplates at the back side of Semiconductor substrate 25.
The structure of semiconductor device 20C is described with reference to Figure 10.Figure 10 (A) is the stereogram of semiconductor device 20C, and Figure 10 (B) is the plane graph of the semiconductor device 20C that sees from the back side.
With reference to Figure 10 (A), the basic structure of semiconductor device 20C is identical with semiconductor device 20A shown in Figure 3, and difference is that each pad electrode that is formed at Semiconductor substrate 25 surfaces is connected with backplate via through electrode 24A.
Collector electrode pad electrode 23C, the base stage pad electrode 23B and the emitter pad electrode 23E that are formed at Semiconductor substrate 25 back sides are connected with the backplate that is formed at Semiconductor substrate 25 back sides via through electrode 24A respectively.According to this structure, can save metal fine, Semiconductor substrate 25 is installed.
With reference to Figure 10 (B), be formed with collector electrode backplate 26C, base stage backplate 26B and emitter backplate 26E at the back side of Semiconductor substrate 25.Collector electrode backplate 26C is connected with the collector electrode pad electrode 23C that is formed at Semiconductor substrate 25 surfaces via through electrode 24A.Base stage backplate 26B is connected with the base stage pad electrode 23B that is formed at Semiconductor substrate 25 surfaces via through electrode 24A.Emitter backplate 26E is connected with two emitter pad electrode 23E that are formed at Semiconductor substrate 25 surfaces via through electrode 24A.
Collector electrode backplate 26C and base stage backplate 26B are disposed near the relative mutually bight.Like this, separate with base stage backplate 26B, can guarantee both insulation by making collector electrode backplate 26C.
Emitter backplate 26E extends to relative bight continuously from a bight at Semiconductor substrate 25 back sides.And emitter backplate 26E compares with other backplate, and its area forms significantly.Form emitter backplate 26E by the earth, can reduce stray inductance.
With each backplate and Semiconductor substrate 25 insulation the time, dispose the insulating barrier that constitutes by oxide-film, nitride film or insulative resin at the back side of Semiconductor substrate 25, and dispose each backplate above the dielectric film at this.In addition, when on each backplate, adhering to scolding tin,, backplate is partly exposed got final product as long as the back side of Semiconductor substrate 25 is covered by anti-scolder agent.
Further specify the structure of semiconductor device 20C with reference to Figure 11.Figure 11 (A) is the stereogram of semiconductor device 20C, and Figure 11 (B) is the profile of B-B ' line of Figure 11 (A), and Figure 11 (C) is the profile of C-C ' line of Figure 11 (A).
With reference to Figure 11 (B), base stage backplate 26B and collector electrode backplate 26C are by dielectric film 38 and 42 insulation of P type semiconductor substrate.At this, dielectric film 38 is made of the film that silicon oxide film, silicon nitride film, resin molding etc. have insulating properties.In addition, the through electrode 24A that is connected with base stage backplate 26B and collector electrode backplate 26C is by side wall insulating film 41 and 42 insulation of P type semiconductor substrate.According to such structure, the insulation of the other parts of collector electrode backplate 26C and base stage backplate 26B and semiconductor device 20C prevents interelectrode short circuit.
On the other hand, do not form dielectric film 38 at the back side of the P type semiconductor substrate 42 in the zone that forms emitter backplate 26E.That is, emitter backplate 26E directly contacts the two conducting with the back side of P type semiconductor substrate 42.Therefore, if emitter backplate 26E is connected with earthing potential, then P type semiconductor substrate 42 also is connected with earthing potential.At this, emitter backplate 26E also can be insulated with the back side of P type semiconductor substrate 42 by dielectric film 38.That is, the whole backplates that are formed at Semiconductor substrate 42 back sides also can be passed through dielectric film 38 and Semiconductor substrate 42 insulation.
At this, active region 21 is separated by groove 33, but need make each electrode (emitter electrode, collector electrode and base electrode) mutually insulated.Therefore, under the situation that is provided with emitter electrode, collector electrode and base electrode, at least two electrodes need to use dielectric film 38 and side wall insulating film 41 to carry out insulation processing as mentioned above.
With reference to Figure 11 (C), emitter backplate 26E is connected with emitter pad electrode 23E above being formed at oxide-film 32 via two through electrode 24A.Among the figure, the inwall of through hole 24A is covered by side wall insulating film 41, but also this side wall insulating film 41 can be saved.
At this, when semiconductor device 20C is used in grounded collector, base stage backplate 26B and emitter backplate 26E by dielectric film 38 etc. and with the back side insulation of Semiconductor substrate 25.In addition, in this case, collector electrode backplate 26C also can be formed directly into the back side of Semiconductor substrate 25.
In addition, when semiconductor device 20C was used in base earth, collector electrode backplate 26C and emitter backplate 26E were by the back side insulation of dielectric film 38 with Semiconductor substrate 25.In addition, in this case, base stage backplate 26B also can be formed directly into the back side of Semiconductor substrate 25.
With reference to Figure 12, secondly, be provided with the circuit arrangement 10D of above-mentioned semiconductor device 20C, the structure of 10E in the explanation.
The structure of circuit arrangement 10D with circuitry substrate 19 is described with reference to Figure 12 (A).In circuit arrangement 10D, be formed with conductive pattern 18A, 18B on circuitry substrate 19 surfaces.And the emitter backplate 26E that is positioned at the semiconductor device 20C back side is connected with conductive pattern 18A via scolding tin etc.In addition, the base stage backplate 26B that is positioned at the semiconductor device 20C back side is connected with conductive pattern 18B.In addition, not shown among the figure, but the collector electrode backplate also is connected with the conductive pattern that is formed at circuitry substrate 19 back sides.Other structure of circuit arrangement 10D is identical with the circuit arrangement 10B shown in Fig. 2 (A).In circuit arrangement 10D, become the structure of saving metal fine.
With reference to Figure 12 (B), in circuit arrangement 10 (E), the conductive pattern 18A, the 18B that imbed in the sealing resin 14 are connected with the electrode that is formed at the semiconductor device 20C back side via scolding tin.Specifically, base stage backplate 26B is connected with conductive pattern 18A, and emitter backplate 26E is connected with conductive pattern 18B.Other structure of circuit arrangement 10E is identical with the circuit arrangement 10C shown in Fig. 2 (B).

Claims (14)

1, a kind of semiconductor device is characterized in that, has: a plurality of pad electrodes, and it is formed at the surface of Semiconductor substrate, is electrically connected with active region; Separated region, it forms the described active region around described Semiconductor substrate; Backplate, it is located at the back side of described Semiconductor substrate; Through electrode, it connects described Semiconductor substrate along thickness direction, described pad electrode is connected with described backplate, and, be arranged on the outside of described separated region;
The described pad electrode of at least one that is connected with earthing potential is connected with described backplate via described through electrode.
2, semiconductor device as claimed in claim 1 is characterized in that, forms bipolar transistor at described active region, and the described pad electrode that will be connected with the emitter region of described bipolar transistor is connected with described backplate via described through electrode.
3, semiconductor device as claimed in claim 1 is characterized in that, forms MOSFET at described active region, and the described pad electrode that will be connected with the source region of described MOSFET is connected with described backplate via described through electrode.
4, semiconductor device as claimed in claim 1, it is characterized in that, the described backplate of described Semiconductor substrate is fixed on the conductive component as the bonding land, and the described pad electrode that is connected with earthing potential is connected with described conductive component via described through electrode and described backplate.
5, semiconductor device as claimed in claim 4 is characterized in that, other pad electrode that is not connected with earthing potential is electrically connected with other conductive component via metal fine.
6, semiconductor device as claimed in claim 1 is characterized in that, described backplate directly contacts with the back side of described Semiconductor substrate, makes described through electrode and described Semiconductor substrate become idiostatic.
7, semiconductor device as claimed in claim 1 is characterized in that, a plurality of backplates are formed at the back side of described Semiconductor substrate, and each described backplate is electrically connected with described pad via described through electrode.
8, semiconductor device as claimed in claim 7 is characterized in that, described backplate utilization covers the dielectric film and the insulation of described Semiconductor substrate at the described Semiconductor substrate back side.
9, semiconductor device as claimed in claim 1 is characterized in that, the whole described pad electrode that is connected with described active region is connected with described backplate via described through electrode.
10, semiconductor device as claimed in claim 1 is characterized in that, described through electrode is formed at the inside of the through hole of the described Semiconductor substrate of perforation outside the described separated region, and described through electrode contacts with the inwall of described through hole.
11, a kind of semiconductor device is characterized in that, has: Semiconductor substrate, and it has the semiconductor layer that has formed active element; First electrode, it is electrically connected with a diffusion zone of described active element; Pad electrode, itself and described first electrode constitute one, extend to be provided with around Semiconductor substrate; Through electrode, it is located at the lower floor of described pad electrode, extends to the back side of Semiconductor substrate from semiconductor layer surface; Backplate, it is electrically connected with described through electrode, is located at the back side of Semiconductor substrate.
12, semiconductor device as claimed in claim 11 is characterized in that, described active element is BIP type or MOS transistor npn npn, and described first electrode that is electrically connected with the diffusion zone of ground connection is electrically connected with two through electrodes at least.
13, a kind of manufacture method of semiconductor device is characterized in that, has: the operation that is formed with source region at semiconductor substrate surface; Form the operation of the pad that is electrically connected with described active region at described semiconductor substrate surface; Formation will be positioned at the operation of the through hole of the described Semiconductor substrate perforation below the described pad; Form the operation of the backplate that is electrically connected with described pad via the through electrode that is formed at described through hole inside at the described Semiconductor substrate back side,
The outside of the separated region that forms surrounding described active region forms described through hole, makes the direct butt of inwall of described through electrode and described through hole and forms.
14, the manufacture method of semiconductor device as claimed in claim 13 is characterized in that, described separated region has groove structure, locos oxide film or PN junction separated structures.
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