CN100495579C - Shift register, shift register array and display device - Google Patents
Shift register, shift register array and display device Download PDFInfo
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- CN100495579C CN100495579C CNB2006101543053A CN200610154305A CN100495579C CN 100495579 C CN100495579 C CN 100495579C CN B2006101543053 A CNB2006101543053 A CN B2006101543053A CN 200610154305 A CN200610154305 A CN 200610154305A CN 100495579 C CN100495579 C CN 100495579C
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Abstract
This invention relates to a display device composed of one displacement register array, which comprises several displacement registers, at least one displacement registers composed of first transistor tube, one second transistor and one third transistor and one drive circuit, wherein, the first transistor tube grating electrode receives one input signal; the second one is coupled to the second electrode of first transistor tube to generate one output signal; the first electrode of second one receives one time signals and the third on to pull down voltage level and the drive circuit determines the switch status of third transistor tube.
Description
Technical field
The present invention relates to a kind of shift register, shift register array and display device; Be particularly related to a kind of shift register, shift register array and display device of utilizing input, output and clock signal to cause the change (stress) of transistor characteristic to reduce internal transistor to be in long-term bias voltage.
Background technology
Most at present LCD all are provided with gate drivers (gate driver) and source electrode driver (source driver) outside panel, in order to produce grid impulse signal (gate pulse signal) and data-signal (data signal).Yet because the cost of this mode is higher, other alternative thereby generation for example, are made the gate drivers of being made up of shift register on glass substrate, and this is so-called integration driving circuit.
Active matrix liquid crystal display now (Active Matrix Liquid Crystal Display is called for short AMLCD) the amorphous silicon film transistor technologies that adopt more.Under this technology, shift register is set on glass substrate has many shortcomings.For example, after panel was lighted, shift register usually can cause the panel performance unusual because being in long-term bias voltage.
Fig. 1 has described No. 2004/0046792 disclosed shift register 1 of patent disclosure case of the U.S., and there are many disappearances in this design.At first, Node B is responsible for going up except needs drive the transistor 104 of pulling work, also must driving transistors 102 and transistor 103.Because the load of Node B is overweight, has postponed the output of shift register 1.Moreover, in order to make node A usefulness preferably being arranged, transistor 101 needs greater than 1:16 with the size of transistor 102.Thus, the V of transistor 101
GSApproximate V
ON-V
OFFThis high cross-pressure causes the electrorheological that flows through transistor 101 big, causes node A to be in the state of long-term bias voltage.In addition, because the voltage of node E is higher than 0V, also cause transistor 101 to be in the state of long-term bias voltage easily.Above-mentioned design disappearance causes using the panel proper operation for a long time of this type of shift register 1.
Fig. 2 is the clock figure of the shift register of depiction 1, and wherein, CKV represents positive phase clock; CKVB represents inversion clock; GOUT[N-1], GOUT[N] and GOUT[N+1] representative shift register output signal not at the same level respectively.N-1 is the previous stage of N, and N is the previous stage of N+1, and N is this grade shift register shown in Figure 1.The desirable clock that Node B in the signal C representative graph 1 is required.As seen from Figure 2, signal C can be by CKV, GOUT[N-1] and GOUT[N] institute forms.Yet the aforementioned biasing problem of mentioning can cause signal C distortion, causes the life-span of shift register to shorten.
If the material of display panels is an amorphous silicon, then the circuit design of shift register more must be considered the biasing problem that transistor bears, and makes the running time of display panels unaffected.Fig. 3 describes No. 2004/0165692 disclosed shift register 3 of patent disclosure case of the U.S., and this shift register 3 also fails to overcome this problem.In this design, because the voltage height of node D, so the bias voltage that makes transistor 301 be born is excessive, life-span thereby shorten, and then make the life-span of shift register and panel shorten.
In sum, existing shift register design, the bias voltage that its inner transistor bears is all too high, not only postpones output time, also shortens the life-span of panel simultaneously.Hereat, how to reduce the bias voltage that transistor bore of shift register, still be utmost point problem to be studied.
Summary of the invention
A purpose of the present invention is to provide a kind of shift register.This shift register comprises a first transistor, a transistor seconds, one the 3rd transistor and one drive circuit.This first transistor has a grid, one second utmost point and one first utmost point, and this grid of this first transistor and this first utmost point receive an input signal.This transistor seconds has a grid, one second utmost point and one first utmost point, this grid of this transistor seconds is coupled to this second utmost point of this first transistor, this of this transistor seconds second utmost point produces an output signal, and this of this transistor seconds first utmost point receives one first clock signal.The 3rd transistor is in order to the voltage level of this grid of this transistor seconds of leaving behind.This driving circuit in response to this input signal and this output signal to determine the 3rd transistorized on off state.
Another object of the present invention is to provide a kind of shift register array, this shift register array has the shift-register circuit of a plurality of serial connections.At least one shift-register circuit comprises a first transistor, a transistor seconds, one the 3rd transistor and one drive circuit.This first transistor has a grid, one second utmost point and one first utmost point, and this grid of this first transistor and this first utmost point receive an input signal.This transistor seconds has a grid, one second utmost point and one first utmost point, this grid of this transistor seconds is coupled to this second utmost point of this first transistor, this of this transistor seconds second utmost point produces an output signal, and this of this transistor seconds first utmost point receives one first clock signal.The 3rd transistor is in order to the voltage level of this grid of this transistor seconds of leaving behind.This driving circuit in response to this input signal and this output signal to determine the 3rd transistorized on off state.
Another purpose of the present invention is to provide a kind of display device, and this display device comprises an array of display and a shift LD array.This array of display has a plurality of pixels.This shift LD array has a plurality of shift registers, and each shift register is in order to drive a pixel of this array of display, and at least one shift register comprises a first transistor, a transistor seconds, one the 3rd transistor and one drive circuit.This first transistor has a grid, one second utmost point and one first utmost point, and this grid of this first transistor and this first utmost point receive an input signal.This transistor seconds has a grid, one second utmost point and one first utmost point, this grid of this transistor seconds is coupled to this second utmost point of this first transistor, this of this transistor seconds second utmost point produces an output signal, and this of this transistor seconds first utmost point receives one first clock signal.The 3rd transistor is in order to the voltage level of this grid of this transistor seconds of leaving behind.This driving circuit in response to this input signal and this output signal to determine the 3rd transistorized on off state.
By above-mentioned arrangement, the present invention can reduce the load of the bootstrap voltage of shift register, producing better usefulness, and then prolongs life-span of liquid crystal panel.
Behind the embodiment of consulting accompanying drawing and describing subsequently, this technical field has knows that usually the knowledgeable just can understand other purposes of the present invention, and technological means of the present invention and enforcement aspect.
Description of drawings
Fig. 1 is a synoptic diagram of describing existing shift register;
Fig. 2 is the clock figure of the shift register of depiction 1;
Fig. 3 is a synoptic diagram of describing existing shift register;
Fig. 4 A is a display panel of describing first embodiment;
Fig. 4 B is a shift LD array of describing first embodiment;
Fig. 4 C is a shift register of describing first embodiment;
Fig. 5 describes employed voltage sequential chart;
Fig. 6 is the positive phase clock figure that describes to use;
Fig. 7 A is a magnitude of voltage sequential chart of describing the grid that pulls up transistor of prior art;
Fig. 7 B is a magnitude of voltage sequential chart of describing the grid that pulls up transistor of first embodiment;
Fig. 8 is a shift register of describing second embodiment;
Fig. 9 A describes the magnitude of voltage sequential chart of first embodiment at node N2; And
Fig. 9 B describes the magnitude of voltage sequential chart of second embodiment at node N2.
The reference numeral explanation
1: shift register
101: transistor 102: transistor
103: transistor 104: transistor
A: Node B: node
E: node
3: shift register
301: transistor D: node
4: display panel
46: shift LD array 47: data drive circuit
48: gate driver circuit 49: array of display
491: 43: the N levels of pixel shift register
42: the second driving circuits of 41: the first driving circuits
401: the first transistor 402: transistor seconds
404: the four transistors of 403: the three transistors
406: the six transistors of 405: the five transistors
408: the eight transistors of 407: the seven transistors
414: the four transistors of 409: the nine transistors
416: the six transistors of 415: the five transistors
418: the eight transistors of 417: the seven transistors
421: the 11 transistors of 419: the nine transistors
423: the 13 transistors of 422: the ten two-transistors
424: the 14 transistors
N5: node
8: shift register
82: the second driving circuits of 81: the first driving circuits
820: the ten transistors of 810: the ten transistors
N2: node N3: node
Embodiment
The objective of the invention is to reduce the load of the bootstrap voltage of shift register, producing better usefulness, and then prolong the life-span of liquid crystal panel.Moreover,, can use twin-stage phase inverter (dual stage inverter) to reduce transistorized operating current based on the present invention, and the executive component that adds the transistor discharge, to increase circuit design in the life-span on glass.
The first embodiment of the present invention is a display device.This display device comprises a display panel 4 to be described as Fig. 4 A, and it has an array of display 49, a gate driver circuit 48 and a data drive circuit 47.This array of display 49 comprises a plurality of pixels 491.Fig. 4 B describes the shift LD array 46 that this gate driver circuit 48 is comprised.This shift LD array 46 has a plurality of shift registers, and each grade shift register is output as the input of next stage shift register.It is that this technical field person knows that binding between those shift registers is closed, so seldom give unnecessary details.Each shift register is in order to drive a row pixel of this array of display.For example, N level shift register 43 is in order to drive N row pixel.
Fig. 4 C describes the N level shift register 43 of present embodiment.This shift register 43 comprises a first transistor 401, one transistor seconds 402, two the 3rd transistors 403 and 413, two the 4th transistors 404 and 414, two the 5th transistors 405 and 415, two the 6th transistors 406 and 416, two the 7th transistors 407 and 417, two the 8th transistors 408 and 418, two the 9th transistors 409 and 419, the 11 transistor 421, the tenth two-transistor 422, the 13 transistor 423, and 1 the 14 transistor 424.
The first transistor 401 is the input end of N level shift register 43, and transistor seconds 402 is pulling up transistor of N level shift register 43.Node N5 is equivalent to the Node B among Fig. 1 among Fig. 4 C, is the gate terminal that pulls up transistor.In addition, N-1 represents the input signal of N level shift register 43 among the figure, that is comes from the output of N-1 level shift register, corresponds to the ST of Fig. 4 B.N represents the output of N level shift register.On behalf of positive clock signal and XCK, CK represent the inversion clock signal.
Before the detailed binding of describing between each transistor, the principle that explanation earlier links.See also Fig. 1 and Fig. 2, Node B is 104 the grid of pulling up transistor, the signal C that its required clock is Fig. 2.Because the shortcoming of Fig. 1 design is the overload of Node B, so the load that focuses on alleviating Node B of the present invention.The CKV of Fig. 2, GOUT[N-1] and GOUT[N] correspond to CK, N-1 and the N of Fig. 4 C.
In the present embodiment, the 3rd transistor 403 and the 3rd transistor 413 are in order to the voltage level of the grid of drop-down transistor seconds 402.The 4th transistor 404, the 5th transistor 405, the 6th transistor 406, the 7th transistor 407, the 8th transistor 408 and the 9th transistor 409 form one drive circuit 41, in order to determine the on off state of the 3rd transistor 403.The 4th transistor 414, the 5th transistor 415, the 6th transistor 416, the 7th transistor 417, the 8th transistor 418 and the 9th transistor 419 form another driving circuit 42, in order to determine the on off state of the 3rd transistor 413.This first driving circuit 41 in response to input signal N-1, output signal N, and an inversion clock signal XCK to drive the 3rd transistor 403; And this second driving circuit 42 in response to input signal N-1, output signal N, and a positive clock signal C K to drive the 3rd transistor 413.
In the present embodiment, all transistors all are the N transistor npn npns, all have a grid, one first utmost point and one second utmost point.Wherein, the first very drain electrode, and second source electrode very.The grid of the first transistor 401 and first utmost point receiving inputted signal N-1, the grid of transistor seconds 402 is coupled to second utmost point of the first transistor 401, second utmost point of transistor seconds 402 produces output signal N, first utmost point of transistor seconds 402 receives positive clock signal C K, the grid of the 3rd transistor 403 is coupled to driving circuit 41, second utmost point of the 3rd transistor 403 is coupled to a power supply VSS, and first utmost point of the 3rd transistor 403 is coupled to the grid of transistor seconds 402.Second utmost point that the grid of another the 3rd transistor 413 is coupled to another driving circuit 42, the three transistors 413 is coupled to power supply VSS, and first utmost point of the 3rd transistor 413 is coupled to the grid of transistor seconds 402.
The structure of first driving circuit 41 then is described in detail in detail.Second utmost point of the 4th transistor 404 is coupled to the grid of the 3rd transistor 403, and first utmost point of the 4th transistor 404 receives inversion clock signal XCK.The grid receiving inputted signal N-1 of the 5th transistor 405, second utmost point of the 5th transistor 405 is coupled to power supply VSS, and first utmost point of the 5th transistor 405 is coupled to the grid of the 3rd transistor 403.The grid of the 6th transistor 406 receives output signal N, and second utmost point of the 6th transistor 406 is coupled to power supply VSS, and first utmost point of the 6th transistor 406 is coupled to the grid of the 3rd transistor 403.The grid of the 7th transistor 407 and first utmost point receive inversion clock signal XCK, and second utmost point of the 7th transistor 407 is coupled to the grid of the 4th transistor 404.The grid receiving inputted signal N-1 of the 8th transistor 408, second utmost point of the 8th transistor 408 is coupled to power supply VSS, and first utmost point of the 8th transistor 408 is coupled to the grid of the 4th transistor 404.The grid of the 9th transistor 409 receives output signal N, and second utmost point of the 9th transistor 409 is coupled to power supply VSS, and first utmost point of the 9th transistor 409 is coupled to the grid of the 4th transistor 404.First utmost point of the 4th transistor 404 and the grid of the 7th transistor 407 and first utmost point all receive inversion clock signal XCK, and the positive clock signal C K that is received with first utmost point of transistor seconds 402 is anti-phase.
The structure of another driving circuit 42 then is described in detail in detail.Second utmost point of the 4th transistor 414 is coupled to the grid of the 3rd transistor 413, and first utmost point of the 4th transistor 414 receives positive clock signal C K.The grid receiving inputted signal N-1 of the 5th transistor 415, second utmost point of the 5th transistor 415 is coupled to power supply VSS, and first utmost point of the 5th transistor 415 is coupled to the grid of the 3rd transistor 413.The grid of the 6th transistor 416 receives output signal N, and second utmost point of the 6th transistor 416 is coupled to power supply VSS, and first utmost point of the 6th transistor 416 is coupled to the grid of the 3rd transistor 413.The grid of the 7th transistor 417 and first utmost point receive positive clock signal C K, and second utmost point of the 7th transistor 417 is coupled to the grid of the 4th transistor 414.The grid receiving inputted signal N-1 of the 8th transistor 418, second utmost point of the 8th transistor 418 is coupled to power supply VSS, and first utmost point of the 8th transistor 418 is coupled to the grid of the 4th transistor 414.The grid of the 9th transistor 419 receives output signal N, and second utmost point of the 9th transistor 419 is coupled to power supply VSS, and first utmost point of the 9th transistor 419 is coupled to the grid of the 4th transistor 414.First utmost point of the 4th transistor 414 and the grid of the 7th transistor 417 and first utmost point all receive positive clock signal C K, and the positive clock signal C K that is received with first utmost point of transistor seconds 402 is a homophase.
The grid of the 11 transistor 421 is coupled to the output terminal (not illustrating) of a N+1 level shift register, and second utmost point of the 11 transistor 421 is coupled to power supply VSS, and first utmost point of the 11 transistor 421 is coupled to the grid of transistor seconds 402.The grid of the tenth two-transistor 422 receives inversion clock signal XCK, and second utmost point of the tenth two-transistor 422 is coupled to power supply VSS, and first utmost point of the tenth two-transistor 422 is coupled to second utmost point of transistor seconds 402.The grid of the 13 transistor 423 is coupled to the grid (not illustrating) of the 3rd transistor 413, and second utmost point of the 13 transistor 423 is coupled to power supply VSS, and first utmost point of the 13 transistor 423 is coupled to second utmost point of transistor seconds 402.The grid of the 14 transistor 424 is coupled to the output terminal (not illustrating) of N+1 level shift register, and second utmost point of the 14 transistor 424 is coupled to power supply VSS, and first utmost point of the 14 transistor 424 is coupled to second utmost point of transistor seconds 402.
By among Fig. 4 C as can be known, the node N5 of present embodiment only must driving transistors 402, so its higher voltage level can be provided, makes that its output is comparatively stable, undelayed phenomenon.Because comparatively stable, the life-span of display device is prolonged.
Below prior art that analysis chart 1 is described and the analog result of utilizing the shift register array of first embodiment.Both shift register arrays respectively contain 22 grades of shift registers, the power supply V that both first order shift registers all use Fig. 5 to be described
StValue triggers.Simultaneously, both positive clock signal C K positive phase clock of all using Fig. 6 and being described.
Fig. 7 A and Fig. 7 B represent the shift register array of the prior art and first embodiment respectively when above-mentioned power values and clock, the gate voltage values that pulls up transistor of level V shift register, that is the magnitude of voltage of the node N5 of first embodiment.Comparison diagram 7A and Fig. 7 B as can be known, compared to prior art, the grid that pulls up transistor of first embodiment has the higher voltage value, particularly dotted line 71 and 72 parts of enclosing in the drawings.This result be because of the load of the gate terminal that pulls up transistor of first embodiment less.
In addition, measure the output voltage values of the level V shift register of shift LD array, that is the magnitude of voltage of the node N of first embodiment can get, prior art required on the time of drawing be t
r=6.81us, drop-down time t
f=4.7us and maximum voltage value is 24.48V.First embodiment required on the time of drawing be t
r=4.78us, drop-down time t
f=4.03us and maximum voltage value is 25.86V.By these numerals as can be known, first embodiment required on draw time and drop-down time all shorter, and the highest magnitude of voltage is also higher.
By Fig. 7 A, 7B and the numeral of measuring gained as can be known, owing to use input signal, output signal, reach the required signal of clock signal supply driving circuit, the gate terminal load that pulls up transistor of first embodiment is less, so can make the usefulness preferably that pulled up transistor, also make the output of shift register preferable simultaneously.
The second embodiment of the present invention also is a display device, be in the structure of shift register different with first embodiment.Fig. 8 describes the shift register 8 of second embodiment.In more detail, shift register 8 is that with the difference of shift register 4 first driving circuit 81 of shift register 8 more comprises 1 the tenth transistor 810, and second driving circuit 82 more comprises another the tenth transistor 820.This 2 the tenth transistor 810 and 820 is respectively in order to reduce the voltage of node N2 and node N3.Its principle is that the voltage of node N2 and N3 is produced by the 7th transistor 407 and the 7th transistor 417, so its signal is roughly identical with inversion clock signal XCK and positive clock signal C K.Hereat, add anti-phase transistor respectively, can increase its discharge path at this two nodes place.
This 2 the tenth transistor 810 and 820 is all the N transistor npn npn, all has a grid, one first utmost point and one second utmost point.Wherein, the first very drain electrode, and second source electrode very.Particularly, the grid of the tenth transistor 810 receives positive clock signal C K, and second utmost point of the tenth transistor 810 is coupled to power supply VSS, and first utmost point of the tenth transistor 810 is coupled to the grid of the 4th transistor 404.The inversion clock signal XCK that the positive clock signal C K that grid received of the tenth transistor 810 and the 4th transistor 404 are received is anti-phase.The grid of the tenth transistor 820 receives inversion clock signal XCK, and second utmost point of the tenth transistor 820 is coupled to power supply VSS, and first utmost point of the tenth transistor 810 is coupled to the grid of the 4th transistor 414.The inversion clock signal XCK that the positive clock signal C K that grid received of the tenth transistor 820 and the 4th transistor 414 are received is for also anti-phase.
Below will analyze the analog result of the shift register array of first embodiment and second embodiment.Both shift register arrays respectively contain 22 grades of shift registers, the power supply V that both first order shift registers all use Fig. 5 to be described
StValue.Simultaneously, both positive clock signal C K positive phase clock of all using Fig. 6 and being described.
Fig. 9 A and Fig. 9 B represent that respectively the level V shift register of shift LD array of the shift LD array of first embodiment and second embodiment is at the magnitude of voltage of node N2.By among the figure as can be known, the node N2 of second embodiment has lower magnitude of voltage, especially dotted line 922 part of enclosing and relative dotted line 921 part of enclosing, and dotted line 924 part of enclosing and relative dotted line 923 part of enclosing, its difference is more remarkable.In addition, in the drop-down part of waveform, second embodiment more can be controlled at it below 0V compared to first embodiment, such as dotted line 925 and dotted line 926 the circle part, and shown in dotted line 927 and 928.
In addition, measure the shift LD array the level V shift register output voltage values as can be known, first embodiment required on the time of drawing be t
r=4.78us, drop-down time t
f=4.03us and maximum voltage value is 25.86V.Second embodiment required on the time of drawing be t
r=4.7us, drop-down time t
f=3.95us and maximum voltage value is 25.88V.The latter, have the discharge transistor shift register required on draw time and drop-down time all shorter, and the highest magnitude of voltage is also higher.
Be stressed that at this N transistor npn npn among first embodiment and second embodiment is all replaceable to be the P transistor npn npn.When transistor is the P type, first source electrode very, and the second very drain electrode.
In sum, use the configuration mode of the shift register of first embodiment, that is utilize the signal source of different signal combination, can reduce the required bias voltage that bears of transistor as driving circuit.In addition, add arresting element the tenth transistor 810 and 820,, can reduce the voltage of the part of nodes of driving circuit as the description of second embodiment.By these two kinds of modes, the present invention has strengthened the usefulness of integral shift register, and the panel life-span of the shift register of feasible this kind of use design is increased.
Only the foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any ripe personage in this skill all can be under the situation of know-why of the present invention and spirit, and the foregoing description is made amendment and changed.Therefore the scope of the present invention should be listed as claim of the present invention.
Claims (16)
1. shift register comprises:
One the first transistor has a grid, one second utmost point and one first utmost point, and wherein, this grid of this first transistor and this first utmost point receive an input signal;
One transistor seconds, have a grid, one second utmost point and one first utmost point, wherein, this grid of this transistor seconds is coupled to this second utmost point of this first transistor, this of this transistor seconds second utmost point produces an output signal, and this of this transistor seconds first utmost point receives one first clock signal;
One the 3rd transistor is in order to the voltage level of this grid of this transistor seconds of leaving behind; And
One drive circuit, respond this input signal and this output signal to determine the 3rd transistorized on off state, wherein, the 3rd transistor has a grid, one second utmost point and one first utmost point, the 3rd transistorized this grid is coupled to this driving circuit, the 3rd transistorized this second utmost point is coupled to a power supply, and the 3rd transistorized this first utmost point is coupled to this grid of this transistor seconds.
2. shift register as claimed in claim 1, this driving circuit comprises:
One the 4th transistor has a grid, one second utmost point and one first utmost point, and the 4th transistorized this second utmost point is coupled to the 3rd transistorized this grid, and the 4th transistorized this first utmost point receives a second clock signal;
One the 5th transistor, have a grid, one second utmost point and one first utmost point, the 5th transistorized this grid receives this input signal, and the 5th transistorized this second utmost point is coupled to this power supply, and the 5th transistorized this first utmost point is coupled to the 3rd transistorized this grid; And
One the 6th transistor, have a grid, one second utmost point and one first utmost point, the 6th transistorized this grid receives this output signal, and the 6th transistorized this second utmost point is coupled to this power supply, and the 6th transistorized this first utmost point is coupled to the 3rd transistorized this grid.
3. shift register as claimed in claim 2, this driving circuit more comprises:
One the 7th transistor has a grid, one second utmost point and one first utmost point, and the 7th transistorized this grid and this first utmost point receive this second clock signal, and the 7th transistorized this second utmost point is coupled to the 4th transistorized this grid;
One the 8th transistor, have a grid, one second utmost point and one first utmost point, the 8th transistorized this grid receives this input signal, and the 8th transistorized this second utmost point is coupled to this power supply, and the 8th transistorized this first utmost point is coupled to the 4th transistorized this grid; And
One the 9th transistor, have a grid, one second utmost point and one first utmost point, the 9th transistorized this grid receives this output signal, and the 9th transistorized this second utmost point is coupled to this power supply, and the 9th transistorized this first utmost point is coupled to the 4th transistorized this grid.
4. shift register as claimed in claim 3, wherein, this driving circuit more comprises 1 the tenth transistor, the tenth transistor has a grid, one second utmost point and one first utmost point, the tenth transistorized this grid receives one the 3rd clock signal, the tenth transistorized this second utmost point is coupled to this power supply, and the tenth transistorized this first utmost point is coupled to the 4th transistorized this grid.
5. shift register array has the shift-register circuit of a plurality of serial connections, and at least one shift-register circuit comprises:
One the first transistor has a grid, one second utmost point and one first utmost point, and wherein, this grid of this first transistor and this first utmost point receive an input signal;
One transistor seconds, have a grid, one second utmost point and one first utmost point, wherein, this grid of this transistor seconds is coupled to this second utmost point of this first transistor, this of this transistor seconds second utmost point produces an output signal, and this of this transistor seconds first utmost point receives one first clock signal;
One the 3rd transistor is in order to the voltage level of this grid of this transistor seconds of leaving behind; And
One drive circuit, respond this input signal and this output signal to determine the 3rd transistorized on off state, wherein, the 3rd transistor has a grid, one second utmost point and one first utmost point, the 3rd transistorized this grid is coupled to this driving circuit, the 3rd transistorized this second utmost point is coupled to a power supply, and the 3rd transistorized this first utmost point is coupled to this grid of this transistor seconds.
6. shift register array as claimed in claim 5, this driving circuit comprises:
One the 4th transistor has a grid, one second utmost point and one first utmost point, and the 4th transistorized this second utmost point is coupled to the 3rd transistorized this grid, and the 4th transistorized this first utmost point receives a second clock signal;
One the 5th transistor, have a grid, one second utmost point and one first utmost point, the 5th transistorized this grid receives this input signal, and the 5th transistorized this second utmost point is coupled to this power supply, and the 5th transistorized this first utmost point is coupled to the 3rd transistorized this grid; And
One the 6th transistor, have a grid, one second utmost point and one first utmost point, the 6th transistorized this grid receives this output signal, and the 6th transistorized this second utmost point is coupled to this power supply, and the 6th transistorized this first utmost point is coupled to the 3rd transistorized this grid.
7. shift register array as claimed in claim 6, this driving circuit more comprises:
One the 7th transistor has a grid, one second utmost point and one first utmost point, and the 7th transistorized this grid and this first utmost point receive this second clock signal, and the 7th transistorized this second utmost point is coupled to the 4th transistorized this grid;
One the 8th transistor, have a grid, one second utmost point and one first utmost point, the 8th transistorized this grid receives this input signal, and the 8th transistorized this second utmost point is coupled to this power supply, and the 8th transistorized this first utmost point is coupled to the 4th transistorized this grid; And
One the 9th transistor, have a grid, one second utmost point and one first utmost point, the 9th transistorized this grid receives this output signal, and this transistorized this second utmost point of is coupled to this power supply, and the 9th transistorized this first utmost point is coupled to the 4th transistorized this grid.
8. shift register array as claimed in claim 7, wherein, this driving circuit more comprises 1 the tenth transistor, the tenth transistor has a grid, one second utmost point and one first utmost point, the tenth transistorized this grid receives one the 3rd clock signal, the tenth transistorized this second utmost point is coupled to this power supply, and the tenth transistorized this first utmost point is coupled to the 4th transistorized this grid.
9. shift register array as claimed in claim 5, wherein, this input signal is the output signal of the shift register of previous stage.
10. shift register array as claimed in claim 5, wherein, this output signal is the input signal of the shift register of back one-level.
11. a display device comprises:
One array of display has a plurality of pixels; And
One shift LD array has a plurality of shift registers, and each shift register is in order to drive a pixel of this array of display, and at least one shift register comprises:
One the first transistor has a grid, one second utmost point and one first utmost point, and wherein, this grid of this first transistor and this first utmost point receive an input signal;
One transistor seconds, have a grid, one second utmost point and one first utmost point, wherein, this grid of this transistor seconds is coupled to this second utmost point of this first transistor, this of this transistor seconds second utmost point produces an output signal, and this of this transistor seconds first utmost point receives one first clock signal;
One the 3rd transistor is in order to the voltage level of this grid of this transistor seconds of leaving behind; And
One drive circuit, respond this input signal and this output signal to determine the 3rd transistorized on off state, wherein, the 3rd transistor has a grid, one second utmost point and one first utmost point, the 3rd transistorized this grid is coupled to this driving circuit, the 3rd transistorized this second utmost point is coupled to a power supply, and the 3rd transistorized this first utmost point is coupled to this grid of this transistor seconds.
12. display device as claimed in claim 11, this driving circuit comprises:
One the 4th transistor has a grid, one second utmost point and one first utmost point, and the 4th transistorized this second utmost point is coupled to the 3rd transistorized this grid, and the 4th transistorized this first utmost point receives a second clock signal;
One the 5th transistor, have a grid, one second utmost point and one first utmost point, the 5th transistorized this grid receives this input signal, and the 5th transistorized this second utmost point is coupled to this power supply, and the 5th transistorized this first utmost point is coupled to the 3rd transistorized this grid; And
One the 6th transistor, have a grid, one second utmost point and one first utmost point, the 6th transistorized this grid receives this output signal, and the 6th transistorized this second utmost point is coupled to this power supply, and the 6th transistorized this first utmost point is coupled to the 3rd transistorized this grid.
13. display device as claimed in claim 12, this driving circuit more comprises:
One the 7th transistor has a grid, one second utmost point and one first utmost point, and the 7th transistorized this grid and this first utmost point receive this second clock signal, and the 7th transistorized this second utmost point is coupled to the 4th transistorized this grid;
One the 8th transistor, have a grid, one second utmost point and one first utmost point, the 8th transistorized this grid receives this input signal, and the 8th transistorized this second utmost point is coupled to this power supply, and the 8th transistorized this first utmost point is coupled to the 4th transistorized this grid; And
One the 9th transistor, have a grid, one second utmost point and one first utmost point, the 9th transistorized this grid receives this output signal, and the 9th transistorized this second utmost point is coupled to this power supply, and the 9th transistorized this first utmost point is coupled to the 4th transistorized this grid.
14. display device as claimed in claim 13, wherein, this driving circuit more comprises 1 the tenth transistor, the tenth transistor has a grid, one second utmost point and one first utmost point, the tenth transistorized this grid receives one the 3rd clock signal, the tenth transistorized this second utmost point is coupled to this power supply, and the tenth transistorized this first utmost point is coupled to the 4th transistorized this grid.
15. display device as claimed in claim 11, wherein, this input signal is the output signal of the shift register of previous stage.
16. display device as claimed in claim 11, wherein, this output signal is the input signal of the shift register of back one-level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101543053A CN100495579C (en) | 2006-09-20 | 2006-09-20 | Shift register, shift register array and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101543053A CN100495579C (en) | 2006-09-20 | 2006-09-20 | Shift register, shift register array and display device |
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| Publication Number | Publication Date |
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| CN1953101A CN1953101A (en) | 2007-04-25 |
| CN100495579C true CN100495579C (en) | 2009-06-03 |
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| CNB2006101543053A Active CN100495579C (en) | 2006-09-20 | 2006-09-20 | Shift register, shift register array and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI338900B (en) | 2007-08-07 | 2011-03-11 | Au Optronics Corp | Shift register array |
| KR102167138B1 (en) | 2014-09-05 | 2020-10-16 | 엘지디스플레이 주식회사 | Shift register and display device using the sane |
| TWI616860B (en) * | 2017-06-27 | 2018-03-01 | 友達光電股份有限公司 | Gate driving circuit and operating method thereof |
| CN107610668B (en) * | 2017-10-20 | 2019-05-24 | 深圳市华星光电半导体显示技术有限公司 | A kind of GOA circuit and liquid crystal display panel, display device |
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| CN1953101A (en) | 2007-04-25 |
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