CN100483438C - Distant contactless IC card read/write implement and method therefor - Google Patents
Distant contactless IC card read/write implement and method therefor Download PDFInfo
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- CN100483438C CN100483438C CNB2006100235534A CN200610023553A CN100483438C CN 100483438 C CN100483438 C CN 100483438C CN B2006100235534 A CNB2006100235534 A CN B2006100235534A CN 200610023553 A CN200610023553 A CN 200610023553A CN 100483438 C CN100483438 C CN 100483438C
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Abstract
This invention relates to one remote non-contact IC read card tool and its method, wherein, the device comprises the following parts: base band data process unit, micro controller, PLL frequency integration super high frequency signal circuit module, power control circuit unit, emission power amplifying unit and base band signal process circuit, wherein, the base band data process unit is of FPGA base band process unit composed of front and back link to realize read card communication agreement and frame process and system time sequence control. This invention progress adopts FPGA chip by use of inner programmable logic materials.
Description
Technical field
The present invention relates to a kind of distant contactless IC card read/write facility and method thereof, relate in particular to and a kind ofly be used for uhf band (distant contactless IC card read/write facility and the method thereof of 902MHz～928MHz) are with the supporting use of remote non-contact read-write antenna.
Background technology
At present, remote contactless card reader generally is made up of power supply unit, base band data processing unit, state indicating member, RS232 communication interface, microcontroller, PLL frequency synthesis ultra-high frequency signal circuit module, power control circuit unit, emissive power amplifier circuit unit, base band signal process circuit (comprising the amplification and the ASK modulation of signal), mixting circuit, directional coupler as shown in Figure 1.Wherein, the base band data processing unit is to be made of codec chip, finishes coding of baseband data and decoding; Power supply unit generally is made up of the voltage stabilizing chip, for system's each several part circuit provides suitable supply voltage value; The state indicating member is used for the various duties of indication mechanism; The RS232 communication interface is used for and compunication; Microcontroller is finished systemic-function control and sequential control; PLL frequency synthesis ultra-high frequency signal circuit module produces the ASK modulation that the emission carrier signal is used for baseband signal; Emissive power is regulated in the power control circuit unit; The emissive power amplifier circuit unit amplifies radiofrequency signal, makes the signal of emission to provide enough electromagnetic energies for electronic tag; The base band signal process circuit comprises that signal amplifies conditioning and ASK modulation, generally is made up of mimic channel; Mixting circuit separates radiofrequency signal and intermediate-freuqncy signal; Directional coupler separates the signal that transmits and receives, and prevents that powerful transmitting from entering receiving circuit and influence the processing of received signal.
Because the base band data processing unit adopts conventional codec chip to constitute, therefore, circuit form is generally all complicated, cause the renewal change of system debug test difficulty, design proposal also difficult, and system realizes that cost is higher.
The following defective of the general existence of above-mentioned system:
1, circuit complexity, poor stability, reliability is not high: owing to adopt too much IC to constitute the functional unit circuit, make Circuits System complicated, test brings difficulty to circuit debugging, so the product design cycle is generally longer.
2, system realizes that cost is higher: the application-specific integrated circuit price is more expensive at present, adopts too much application-specific integrated circuit in system, obviously increases the design cost of system.
3, system upgrade upgrades difficulty: at present, technology innovation speed is too fast, and the user is also more and more higher to the requirement of system.But in system, adopt too much special chip, make the upgrading of system upgrade the whole hardware scheme of necessary change.
The two-phase space code (FMO) that relates in this instructions is abbreviated as " FMO ".
Summary of the invention
At above-mentioned technical matters, the invention provides a kind of distant contactless IC card read/write facility and method thereof.
For reaching above-mentioned purpose, the present invention adopts following technical scheme:
A kind of distant contactless IC card read/write facility, comprise base band data processing unit, microcontroller, PLL frequency synthesis ultra-high frequency signal circuit module, power control circuit unit, emissive power amplifier circuit unit, base band signal process circuit (comprising the amplification and the ASK modulation of signal), mixting circuit and directional coupler, described base band data processing unit is a FPGA base band data processing unit, comprise that forward link and back are to link, be used to realize the processing of Card Reader communication protocol and frame, and the sequential control of system.
Wherein, described back comprises to link:
The FMO decoder module is used to receive the FMO code stream and is decoded into binary data stream;
The anticollision module is used for carrying out the identification of multiple electronic label when the FMO code stream that receives can not be correctly decoded into binary data stream;
The frame processing module is used for that described binary data stream is carried out frame and handles,
Checking code generator is used for the binary data stream of frame processing procedure is carried out verification.
Wherein, described forward link comprises,
The frame processing module is used to receive MCU and sends to the order data frame of FPGA and carry out the frame processing, extracts and form the pairing binary data stream of data command that will send to electronic tag;
Checking code generator generates check code to the binary data stream in the frame processing procedure, and this check code adds the binary data stream end to and sends to electronic tag together;
The baseband coding module comprises pulse-spacing coding (Pulse Interval coding is called for short the PIE sign indicating number) module and Manchester's cde module, according to the type of electronic tag, selects the respective coding module to encode;
Wherein, described checking code generator preferably adopts the CRC check code generator.
The present invention also provides a kind of distant contactless IC card read/write method, comprises the base band data treatment step, and described base band data treatment step is a FPGA base band data treatment step, comprises that forward link step and back are to the link step.
Wherein, described forward link steps in sequence comprises:
(1) utilize the frame processing module, reception MCU sends to the order data frame of FPGA and information in the frame is extracted, and is formed for discerning the pairing binary data stream of data command of electronic tag;
(2) utilize checking code generator that the binary data stream in the frame processing procedure is generated check information, and in frame is handled, this check information is added to described binary data stream end and send to electronic tag together;
(3) carry out baseband coding, comprise pulse-spacing coding and Manchester's cde,, select the respective coding module that described binary data stream is encoded according to the type of electronic tag;
Wherein, described back comprises to the link steps in sequence:
(1) utilizes the FMO decoder module, receive the FMO data stream and be decoded into binary data stream;
(2) when the FMO code stream that receives can not be correctly decoded into binary data stream, start the anticollision module and carry out the identification of multiple electronic label;
(3) utilize checking code generator that binary data stream is carried out verification;
(4) utilizing the frame processing module that described binary data stream is carried out message structure handles.
Wherein, in the described anticollision step,, adopt dynamic slot ALOHA searching algorithm if when electronic tag is category-A (Type A); When if electronic tag is category-B (Type B), adopt binary search algorithm.
Wherein, described method of calibration is preferably CRC check.
Technical solution of the present invention, adopt fpga chip, by programming, utilize its inner abundant programmable logic resource, realize the processing of defined Card Reader communication protocol of ISO/IEC18000-6 standard and frame thereof, realize the sequential control of system, microcontroller is freed from the sequential control of complexity, bring into play its system's control action better, the operation of assurance system is normal.This programme can improve the stability of distant contactless IC card read/write facility, simplifies the design of Circuits System.
Description of drawings
Fig. 1 is the synoptic diagram of existing general remote contactless card reader.
Fig. 2 is the synoptic diagram of distant contactless IC card read/write facility of the present invention.
Fig. 3 is the forward link synoptic diagram that card reader arrives electronic tag in the FPGA base band data processing unit of the present invention.
Fig. 4 is that electronic tag arrives the back to the link synoptic diagram of card reader in the FPGA base band data processing unit of the present invention.
Fig. 5 is the process flow diagram that the present invention realizes the Manchester's cde that the Type B of ISO/IEC18000-6 standard adopts.
Fig. 6 is the process flow diagram that the present invention realizes the pulse-spacing coding that the Type A of ISO/IEC18000-6 standard adopts.
Fig. 7 is a FMO bit stream data form example schematic of the present invention.
Fig. 8 is the synoptic diagram that FMO code stream decoding that how FPGA of the present invention returns electronic tag becomes the base band binary data.
Fig. 9 is the process flow diagram for dynamic slot ALOHA algorithm.
Figure 10 is the synoptic diagram that FPGA realizes Cyclic Redundancy Code (CRC-16) generator.
Embodiment
As shown in Figure 2, a kind of distant contactless IC card read/write facility, with the supporting use of remote non-contact read-write antenna, it comprises FPGA base band data processing unit, power supply unit, the state indicating member, the RS232 communication interface, microcontroller, PLL frequency synthesis ultra-high frequency signal circuit module, the power control circuit unit, the emissive power amplifier circuit unit, base band signal process circuit (comprising the amplification and the ASK modulation of signal), mixting circuit, directional coupler, described FPGA base band data processing unit, be used to realize the processing of defined Card Reader communication protocol of ISO/IEC18000-6 standard and frame, also realize the sequential control of system.
Wherein, FPGA base band data processing unit comprises that card reader arrives the forward link of electronic tag (as shown in Figure 3) and electronic tag arrives the back to link (as shown in Figure 4) of card reader.
Described forward link comprises frame processing module, CRC check code generator, pulse-spacing coding module, Manchester's cde module, receive the order data frame of MCU transmission when FPGA base band data processing unit after, extract and form binary data stream through the frame processing module, then according to the type of electronic tag, carry out respective coding, if the category-A label just passes through the pulse-spacing coding module coding if the category-B label is just encoded by the Manchester's cde module.Information via ASK modulation back behind the coding is launched by antenna.
Wherein Manchester's cde flow process as shown in Figure 5, concrete steps are described below:
1) the encoded binary data stream is wanted in input;
2) judge that the level value that will encode is low level or high level; If high level then produces the rising edge saltus step in half bit position; If low level then produces the negative edge saltus step in half bit position;
3) repeating step 2), finish until Manchester's cde.
Wherein the pulse-spacing coding flow process as shown in Figure 6, concrete steps are described below:
1) forms frame initial (SOF) sign of PIE code stream, and obtain to want the encoded binary data stream;
2) judge that the level value that will encode is low level or high level; If high level, the waveform of formation level " 1 "; If low level, the waveform of formation level " 0 ";
3) repeating step 2), up to finishing;
4) frame end (EOF) sign of formation PIE code stream finishes coding.
Described back comprises FMO decoder module, anticollision module, frame processing module, CRC check code generator to link.Convert the FMO code stream to after the information via ASK demodulation that electronic tag returns, receive FMO code stream and decoding by the FMO decoder module, represent not take place collision when the FMO code stream that receives can be correctly decoded into binary data stream, binary data stream sends MCU to after being processed into frame data by the verification of CRC check code generator and by the frame processing module; When the FMO code stream that receives can not be correctly decoded into binary data stream, collision took place in expression, start the identification that the anticollision module is carried out multiple electronic label this moment, after handling by the verification of CRC check code generator and through the frame of frame processing module afterwards, frame data send MCU to.
Wherein, the data layout of FMO sign indicating number meets the ISO/IEC18000-6 standard; FMO decoding is meant by to the FPGA programming, utilizes the inner abundant programmable logic resource of fpga chip, receives and separate to read the represented binary message of FMO code stream.Fig. 7 is the FMO coded format of byte 0xB1=10110001, and the FMO code stream has two kinds of forms (a, b among the figure), gets the state which kind of form depends on the front.
FMO code stream decoding and anticollision treatment scheme as shown in Figure 8, concrete steps are described below:
1) the FMO code stream that receives;
2) do you judge that half bit position took place along saltus step? if then this bit is judged to level " 0 " (being that the NRZ sign indicating number is 0 binary number); If not, then this bit is judged to level " 1 " (being that the NRZ sign indicating number is 1 binary number);
3) repeating step 2) be decoded as binary data up to whole FMO sign indicating numbers;
4) judge whether to take place collision, if then start anti-collision algorithm;
5) finish anticollision after, carry out frame and handle.
Wherein, the distant contactless IC card read/write facility adopt the correctness of Cyclic Redundancy Code (CRC-16) checking data communication.As shown in figure 10, Cyclic Redundancy Code adopts CRC-16, and its generator polynomial is x
16+ x
12+ x
5+ 1, the error detection rate of this generator polynomial is higher, can utilize d type flip flop and XOR gate to produce corresponding C RC check code when the realization of FPGA.
A kind of distant contactless IC card read/write method also is provided in the embodiment of the invention, comprises the base band data treatment step, described base band data treatment step is a FPGA base band data treatment step.It comprises that forward link step and back are to the link step.
Wherein, described forward link steps in sequence comprises:
Carry out frame and handle, be used to receive MCU and send to the order data frame of FPGA and carry out the frame processing, extract and form the pairing binary data stream of data command that will send to electronic tag;
Generate check code, utilize checking code generator that the binary data stream in the frame processing procedure is generated check code, and add the binary data stream end to and send to electronic tag together;
Carry out baseband coding, comprise pulse-spacing coding and Manchester's cde,, select the respective coding module to encode according to the type of electronic tag;
Wherein, described back comprises to the link steps in sequence:
The FMO decoding, the FMO code stream decoding that is used for receiving becomes binary data stream;
Anticollision is used for carrying out the identification of multiple electronic label when the FMO code stream that receives can not be correctly decoded into binary data stream;
Frame is handled, and be used for that described binary data stream is carried out frame and handle,
Verification is used for the binary data stream of frame processing procedure is carried out CRC check.
Wherein, in the described anticollision step,, adopt dynamic slot ALOHA searching algorithm if when electronic tag is category-A; When if electronic tag is category-B, adopt binary search algorithm.
Below, respectively dynamic slot ALOHA searching algorithm and binary search algorithm are described.
The process flow diagram of dynamic slot ALOHA algorithm as shown in Figure 9.May further comprise the steps:
1. time slot, timeslot number and the associated counter value that resets that electronic tag needs discerned in the FPGA initialization, and utilize initialization command (Init_Round) to transmit operational timeslot number (Round_Size) and give electronic tag, electronic tag (be in static (Quiet) state except) all enters activation (Round_Active) state by ready (Ready) state after receiving the Init_Round order, and utilize inner pseudorandom number generator to produce the time slot sequence number that to use, go back the time slot counter of set inside in addition, promptly time slot counter is put ' 1 '.
2. FPGA waits for electronic tag response current time slots.3. and operation 4. when the time slot sequence number that electronic tag produced that is in activation (Round_Active) state just equates with the count value of its internal time slot counter that then such electronic tag will respond current time slots, continue step.Otherwise jump to step 5..
3. if there is not collision in the time slot of electronic tag response, promptly has only an electronic tag response current time slots, FPGA is the information that does not have to read under the case of collision this electronic tag response (include the 4bit signature of electronic tag and SUID number etc.), send then and select (Select) order (SUID and the 4bit signing messages that have the electronic tag that received just now) to select this electronic tag and allow other electronic tags that are in activation (Round_Active) state enter wait (Round_Standby) state, this is equivalent to they can not be responded next to responding the operational order of electronic tag.After the identification of having finished current electronic tag, FPGA sends a next round (New_Round, Next_Slot, Close_Slot) order, allow this electronic tag enter static (Quiet) state and no longer participate in the collision recognition of back (unless selected again or entered activation (Round_Active) state by static (Quiet) state), and all will be reentered activation (Round_Active) state by the electronic tag of " blockade " just now and its internal time slot counter adds ' 1 ' automatically, prepare the collision recognition of a new round, jump to step 6..
4. if there is collision in the time slot of electronic tag response, FPGA will dynamically increase timeslot number, jumps to step 1..
If 5. there is not electronic tag response time slot, FPGA just sends and closes (Close_Slot) order, and its internal time slot counter of all electronic tags that order is in activation (Round_Active) all adds ' 1 ' automatically.
6. FPGA counts the Close_Slot of transmission or the number of times of Next_Slot order, and whether more current count value equates with initialized timeslot number.If equate, promptly represent the anticollision end of identification, jump to step 7..Otherwise FPGA produces next time slot, jumps to step 2..
7. FPGA finishes the anticollision search.
Wherein, binary search algorithm specifically may further comprise the steps:
1. FPGA only sends the known portions (N～X) as the foundation of search, interrupt transmission then of the sequence number that will search in request (REQUEST) order;
2. all (sequence number in the position of N～X) and search be according to the electronic tag that conforms to, then transmit they sequence number residue everybody promptly (X-1) position to FPGA.FPGA judges whether also to exist collision according to the data of (X-1) position that receives.
If 3. still collision then also joins the position of collision in the foundation of search and carries out the work of recalling.Jump to step 1.;
If 4. there has not been collision, promptly identify unique electronic tag this moment, so just this electronic tag is discerned, after finishing, continue step 5.;
5. good according to precedence record search foundation is recalled, and continues to search for the collision recognition of the electronic tag that also is not accessed to, till finishing to collision recognition.
Claims (7)
1, a kind of distant contactless IC card read/write facility, comprise: the base band signal process circuit of base band data processing unit, the amplification that comprises signal and ASK modulation, microcontroller, PLL frequency synthesis ultra-high frequency signal circuit module, power control circuit unit, emissive power amplifier circuit unit, mixting circuit and directional coupler, it is characterized in that: described base band data processing unit is a FPGA base band data processing unit, comprise that forward link and back are to link, be used to realize the processing of Card Reader communication protocol and frame, and the sequential control of system;
Described forward link comprises the frame processing module, is used to receive MCU and sends to the order data frame of FPGA and carry out the frame processing, extracts and form the pairing binary data stream of data command that will send to electronic tag;
Checking code generator generates check code to the binary data stream in the frame processing procedure;
The baseband coding module comprises pulse-spacing coding module and Manchester's cde module, according to the type of electronic tag, selects the respective coding module to encode.
2, distant contactless IC card read/write facility according to claim 1 is characterized in that: described back comprises two-phase space code decoder module to link, is used to receive two-phase space code code stream and is decoded into binary data stream; The anticollision module when two-phase space code code stream that is used to receive can not be correctly decoded, is carried out the identification of multiple electronic label; The frame processing module is used for the binary data stream of decoding is carried out the frame processing; Checking code generator is used for the binary data stream of frame processing procedure is carried out verification.
3, distant contactless IC card read/write facility according to claim 1 and 2 is characterized in that: described checking code generator is the CRC check code generator.
4, a kind of distant contactless IC card read/write method, comprise the base band data treatment step, it is characterized in that: described base band data treatment step is a FPGA base band data treatment step, and it comprises that forward link step and back are to the link step, wherein, described forward link steps in sequence comprises:
(1) utilize the frame processing module, reception MCU sends to the order data frame of FPGA and information in the frame is extracted, and is formed for discerning the pairing binary data stream of data command of electronic tag;
(2) utilize checking code generator that the binary data stream in the frame processing procedure is generated check information, and this check information is added to the frame end send to electronic tag together;
(3) carry out baseband coding, comprise pulse-spacing coding and Manchester's cde,, select the respective coding module that above-mentioned binary data stream is encoded according to the type of electronic tag.
5, distant contactless IC card read/write method according to claim 4 is characterized in that, described back comprises to the link steps in sequence:
(1) utilizes two-phase space code decoder module, the two-phase space code data stream that receives is decoded into binary data stream;
(2) when the two-phase space code code stream that receives can not be correctly decoded into binary data stream, start the anticollision module and carry out the identification of multiple electronic label;
(3) utilize checking code generator that binary data is carried out verification;
(4) utilizing the frame processing module that described binary data stream is carried out message structure handles.
6, distant contactless IC card read/write method according to claim 5 is characterized in that: in the described anticollision step, if when electronic tag is category-A, adopt dynamic slot ALOHA searching algorithm; When if electronic tag is category-B, adopt binary search algorithm.
7, according to claim 5 or 6 described distant contactless IC card read/write methods, it is characterized in that: the described CRC check that is verified as.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814921B (en) * | 2010-03-17 | 2013-01-23 | 华东师范大学 | Coding module of digital baseband system of radio-frequency identification reader |
| CN101888357B (en) * | 2010-05-20 | 2013-11-20 | 重庆大学 | Baseband signal coding and decoding circuit |
| CN102158239B (en) * | 2010-12-21 | 2013-10-23 | 浙江大学 | Broad-band radio-frequency generation circuit based on VC-TCXO (Voltage Control - Temperature Compensation Crystal Oscillator) array and frequency synthesizing chip |
| CN107070564B (en) * | 2017-01-20 | 2021-01-15 | 北京邮电大学 | Modulation-demodulation system capable of adapting to carrier waveform |
| CN110705324B (en) * | 2019-09-12 | 2022-10-25 | 北京维普无限智能技术有限公司 | Method for preventing non-contact card reader from being mistakenly withdrawn |
| CN110971315B (en) * | 2019-12-06 | 2022-02-11 | 广东汇泰龙科技股份有限公司 | Method and system for detecting communication signal between CPU (Central processing Unit) induction card and intelligent lock |
| CN112927397A (en) * | 2021-01-22 | 2021-06-08 | 贵州电网有限责任公司 | 220kv transformer substation maintenance isolation management and control method and system based on Internet of things |
-
2006
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Non-Patent Citations (4)
| Title |
|---|
| FPGA在非接触IC卡读卡器中应用. 孙宏军，姜印平，王超.电子测量技术，第6期. 2002 |
| FPGA在非接触IC卡读卡器中应用. 孙宏军，姜印平，王超.电子测量技术，第6期. 2002 * |
| 基于ISO/IEC18000-6标准的射频识别系统的FPGA设计及实现. 陈博.电子器件，第28卷第4期. 2005 |
| 基于ISO/IEC18000-6标准的射频识别系统的FPGA设计及实现. 陈博.电子器件，第28卷第4期. 2005 * |
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