CN100477230C - Nonvolatile memory device and method for fabricating the same - Google Patents
Nonvolatile memory device and method for fabricating the same Download PDFInfo
- Publication number
- CN100477230C CN100477230C CNB2005100903199A CN200510090319A CN100477230C CN 100477230 C CN100477230 C CN 100477230C CN B2005100903199 A CNB2005100903199 A CN B2005100903199A CN 200510090319 A CN200510090319 A CN 200510090319A CN 100477230 C CN100477230 C CN 100477230C
- Authority
- CN
- China
- Prior art keywords
- floating gate
- nonvolatile memory
- gate
- layer
- polysilicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000007667 floating Methods 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 230000005641 tunneling Effects 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 229920005591 polysilicon Polymers 0.000 claims description 43
- 238000009413 insulation Methods 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 239000000460 chlorine Substances 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 claims description 2
- 238000011109 contamination Methods 0.000 abstract 1
- 230000007423 decrease Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 238000003723 Smelting Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A nonvolatile memory device and a method for fabricating the same decreases power consumption and prevents contamination of an insulating layer. The nonvolatile memory devices includes a semiconductor substrate; a tunneling oxide layer formed on a predetermined portion of the semiconductor substrate; a floating gate formed on the tunneling oxide layer, the floating gate having a trench structure; a control gate formed inside the trench structure of the floating gate; and a gate insulating layer disposed between the floating gate and the control gate.
Description
The cross reference of related application
The application requires in the priority of the korean patent application No.P2004-63869 of submission on August 13rd, 2004, and its full content is hereby expressly incorporated by reference.
Technical field
The present invention relates to nonvolatile memory, more specifically, relate to the method that is used to make nonvolatile memory, it can reduce power consumption and prevent that insulating barrier from polluting.
Background technology
Even the advantage of nonvolatile memory is that power interruptions can obliterated data yet, this has made them be widely used in the storage of computer BIOS chip, set-top box, printer, the webserver, digital camera and mobile phone.In nonvolatile memory, Electrically Erasable Read Only Memory (EEPROM) device can carry out data erase operation from each memory cell or by the sector.By on the side of drain region, producing channel hot electron, then it is stored on the floating gate, improve transistorized threshold voltage, thereby cell transistor programming with the EEPROM device, and by between floating gate and source region/substrate, producing high-voltage potential, make the channel hot electron discharge of storage then, reduce threshold voltage, thereby wipe the cell transistor of EEPROM device.
Simultaneously, flash memory is the special shape of nonvolatile memory, and data bit is stored in the unit of memory or in the memory cell by it.One group of memory cell can be described as a word, and one group of word can be described as one page, and one group of page or leaf can be described as a sector.Can read and programme by word or access to web page data, simultaneously with " flash memory " in the same, wipe common addressable whole sector.
Figure 1A and 1B illustrate the technology according to the manufacturing flash memory device of correlation technique, and this flash memory device has the stacked grid structure that comprises floating gate and control gate.Floating gate stores the electric charge that is used for these grid, and control gate receives driving voltage.
Referring to Figure 1A, tunnelling (tunneling) oxide skin(coating) 11a forms on the predetermined portions of Semiconductor substrate 11, and stacked grid 12 are formed on the tunneling oxide layer by a series of deposition steps, to form the layer of stacked grid structure.Stacked grid 12 comprise the polysilicon layer that is used to form floating gate 12a, the gate insulation layer 12b with oxide-nitride thing-oxide structure and the polysilicon layer that is used to form control gate 12c, and their orders on tunneling oxide layer 11a form.Be used for polysilicon layer that floating gate forms have by low pressure chemical machinery (gas phase) deposition (Chemical Mechanical Deposition) form 800～
Thickness, and be used for polysilicon layer that control gate forms have same by the low pressure chemical mechanical deposit form 2000～
Thickness.
Subsequently, by the structure (wherein this structure comprise control gate 12c, gate insulation layer 12b and floating gate 12a) of etching, photoetching process is used to form the structure of stacked grid 12 by the deposition step acquisition of front.Or rather, photoetching process is used for removing selectively the part that (that is, etching) is used for polysilicon layer, the gate insulation layer 12b of control gate formation and is used for the polysilicon layer of floating gate formation, thereby forms stacked grid 12.Then on the side of stepped construction, or rather, on each of control gate 12c, gate insulation layer 12b and floating gate 12a, form anticorrosion layer (liner layer) (oxide side walls) 13.
Referring to Figure 1B, insulative sidewall 14 outwards forms on anticorrosion layer 13 next doors.Then, stacked grid 12 and insulative sidewall 14 are used as mask, implanting impurity ion, thereby formation source/drain region 15 and 16.Subsequently, silicide layer 17 forms on the exposed surface of source/ drain region 15 and 16 and control gate 12c.Insulation interbed 19 forms on the whole surface of formed structure, and a plurality of contact hole forms in insulating barrier, with the silicide layer 17 and the control gate 12c of source of exposure/ drain region 15 and 16 tops.Form a plurality of plugs (plug) 18 by filling contact hole.
In above-mentioned technology according to correlation technique manufacturing flash memory device, utilize etching to form stacked grid structure in the photoetching process and comprise two steps, i.e. wet etching and dry ecthing, this is complicated step.Carry out described two process, so that the plasma damage minimum during the photoetching.As the result of plasma damage, or because the rapid etching condition of multistep of self, gate insulation layer still may be contaminated.
For to above-mentioned flash memory device programming according to correlation technique, program voltage is imposed on control gate 12c by word line, impose on drain region 16 by bit line.Like this, utilize the heat carrier method, the electronics in drain region 16 injects to floating gate 12a by tunneling oxide layer 11a.In the process of obliterated data, erasing voltage is imposed on source region 15 by the source line.Like this, the electronics of injection floating gate 12a is discharged into raceway groove by tunneling oxide layer 11a.
The coupling of (particularly, between the contact-making surface between control gate and the floating gate and between the contact-making surface in floating gate and drain region) realizes aforesaid operations between the element according to stacked grid, and makes the coupling efficiency maximum, to reduce power consumption.Therefore, need to improve coupling efficiency and reduce the power consumption of device, provide the small-power flash memory device thereby can be the mobile product that requires low-power consumption.
Summary of the invention
Therefore, the present invention aims to provide a kind of nonvolatile memory and manufacture method thereof, and this method has been avoided one or more problems of causing owing to the limitation of correlation technique and shortcoming basically.
An object of the present invention is to provide a kind of nonvolatile memory and manufacture method thereof that reduces power consumption.
Another object of the present invention provides and a kind ofly prevents insulating barrier because plasma damage and contaminated nonvolatile memory and manufacture method thereof.
Another object of the present invention provides a kind of nonvolatile memory of making the method for nonvolatile memory and being suitable for this method of being used to, and this method has realized being used to form the simplification photoetching process of stacked grid.
Additional advantage of the present invention, purpose and characteristic will partly be set forth in the following description, and part is for being conspicuous the those skilled in the art that read following content, or can obtain according to practice of the present invention.By the structure that written description and claims thereof and accompanying drawing are specifically noted, can realize and obtain purpose of the present invention and other advantage.
According to purpose of the present invention, in order to obtain these purposes and other advantage,, provide a kind of like this nonvolatile memory herein as embodying and general description, comprising: Semiconductor substrate; The tunneling oxide layer is formed on the predetermined portions of this Semiconductor substrate; Floating gate is formed on this tunneling oxide layer, and this floating gate has groove structure; Control gate is formed in the groove structure of this floating gate; And gate insulation layer, be arranged between this floating gate and this control gate.
On the other hand, provide a kind of method that is used to make nonvolatile memory, having comprised: on the predetermined portions of Semiconductor substrate, formed the tunneling oxide layer; On this tunneling oxide layer, be formed for forming first polysilicon layer of floating gate; Form groove at first polysilicon layer that is used for floating gate formation, this groove has desired depth; In the groove that first polysilicon layer that is used for floating gate formation forms, form gate insulation layer; On this gate insulation layer, be formed for forming second polysilicon layer of control gate; Carry out cmp for second polysilicon layer that is used to form control gate; On this floating gate, this gate insulation layer and this control gate, be formed for forming the photoresist pattern of floating gate; And use this photoresist pattern etching to be used for first polysilicon layer that floating gate forms.
Should be understood that aforementioned general description of the present invention and the following detailed description only are schematically, purpose is to provide of the present invention the further specifying to as being advocated.
Description of drawings
Accompanying drawing is used to provide further understanding of the invention, and merges in this application and constitute the application's part, and accompanying drawing illustrates embodiments of the invention, and with explanation in order to explain principle of the present invention.In the accompanying drawings:
Figure 1A and Figure 1B are the sectional views of technology that is used to make nonvolatile memory that illustrates according to correlation technique; And
Fig. 2 A-2E illustrates the sectional view that is used to make the technology of nonvolatile memory according to of the present invention.
Embodiment
Now will be in detail with reference to the preferred embodiments of the present invention, the example is shown in the drawings.In any possible place, same reference numerals is used to represent same or similar part in all figure.
Fig. 2 A-2E illustrates the technology that is used to make nonvolatile memory according to of the present invention.As the initial step in this technology, the sacrificial oxidation film (not shown) is formed on the Semiconductor substrate, and after forming trap and channel layer by ion implantation technology respectively, utilizes wet etching to remove sacrificial oxidation film.
Referring to Fig. 2 A, use the smelting furnace thermal process of carrying out 700～800 ℃ temperature, on Semiconductor substrate 21, form have 90～
The tunneling oxide layer 22 of thickness.Then carry out low-pressure chemical vapor deposition, have 4500 on tunneling oxide layer 22, to form～
First polysilicon layer 23 of thickness.First polysilicon layer 23 of Xing Chenging served as the floating gate of nonvolatile memory afterwards after etching like this.By using chlorine (C1
2) etch process removes the predetermined interior section of first polysilicon layer, forms grooves 24 being used for first polysilicon 23 that floating gate forms, it will serve as the shell (encasement) of the control gate that is used for nonvolatile memory afterwards.After etching, groove 24 preferably has 2500～
Thickness, make, the initial formation thickness of supposing first polysilicon layer 23 is 4500～
Keep then that it is about 1000～
Thickness, to form the downside of groove.
Referring to Fig. 2 B, gate insulation layer 25 forms on the surface of first polysilicon layer 23, so that inwall with oxide-nitride thing-oxide structure covering groove 24, wherein this oxide-nitride thing-oxide structure comprises oxide skin(coating), nitride layer and another (that is the top) oxide skin(coating) that for example forms with the known method order.Utilize low-pressure chemical vapor deposition with about 700～800 ℃ temperature the bottom oxide skin(coating) of gate insulation layer 25 is formed 50～
Thickness; Utilize low-pressure chemical vapor deposition equally but with about 650～750 ℃ temperature the nitride layer of gate insulation layer is formed 60～
Thickness; And utilize the smelting furnace thermal process to form another oxide skin(coating) with about 800～900 ℃ temperature.Carry out low-pressure chemical vapor deposition, on the whole surface of formed structure, to be formed for second polysilicon layer 26 that control gate forms.Second polysilicon layer 26 can have 3500～
Thickness, this thickness degree of depth than groove 24 substantially is thick.
Referring to Fig. 2 C, form very thick polysilicon layer 26 by the cmp planarization, to form and the flush of first polysilicon layer 23 and the control gate 26a that separates with first polysilicon layer by gate insulation layer 25.Like this, the material separately of second polysilicon layer 26 and gate insulation layer 25 is retained in the groove 24, and control gate 26a is set to be enclosed in first polysilicon layer 23 that inserts gate insulation layer 25.In the process of doing like this, control gate 26a and the apparent surface's area that is used for the contact-making surface between the material of first polysilicon layer 23 that floating gate forms increase, thereby have improved coupling efficiency, the corresponding power consumption that has reduced device.
Referring to Fig. 2 D, the photoresist (not shown) forms on the whole surface of the formed structure of Fig. 2 C, comprises the upper surface of the exposure of control gate 26a, gate insulation layer 25 and first polysilicon layer 23.Then carry out exposure and developing process (that is, photoetching), to form the mask pattern, this mask pattern uses in the process of etching first polysilicon layer 23, to form floating gate 23a, like this, make floating gate 23a have inner groove structure of filling with gate insulation layer 25 and control gate 26a.Therefore, the photoresist pattern that is used to form floating gate 23a is positioned on floating gate, gate insulation layer 25 and the control gate 26a, and uses the photoresist pattern that first polysilicon layer 23 that is used for floating gate formation is carried out isotropic etching.Therefore, compare with the technology of correlation technique, be used for the polysilicon layer that floating gate forms by using the etching of single stage etch process, form the grid of nonvolatile memory, thereby prevent the possibility of any pollution gate insulation layer, and the pollution of gate insulation layer is since during being used for according to the etch process of the device manufacturing of correlation technique plasma damage cause.
Referring to Fig. 2 E, the depositing insulating layer (not shown), then it is eat-back (etchback), on the side of floating gate 23a, to form insulative sidewall 27, and floating gate and insulative sidewall are used as mask, implanting impurity ion, thus in the Semiconductor substrate 21 of the either side of floating gate formation source/drain region 28 and 29.Subsequently, carry out self aligned polycide (salicide) technology, thereby make the upper surface of floating gate 23a and control gate 26a and have silicide layer 30 corresponding to the Semiconductor substrate 21 of source/ drain region 28 and 29 for this substrate.Insulation interbed 39 forms on the whole surface of formed structure, and a plurality of contact hole forms in insulating barrier, with source region and drain region 28 and 29 and control gate 26a on expose silicide layer 30.Form a plurality of conductive plugs 31 by filling contact hole.
Therefore, in Fig. 2 E, illustrated according to nonvolatile memory of the present invention.Nonvolatile memory according to the present invention comprises: Semiconductor substrate 21; Tunneling oxide layer 22 is formed in the predetermined portions of upper surface of this Semiconductor substrate; Floating gate 23a forms the groove structure with inside, and this groove structure forms on this tunneling oxide layer; Control gate 26a forms in the inside of the groove structure of this floating gate; And the gate insulation layer 25 with oxide-nitride thing-oxide structure, be arranged between this floating gate and this control gate.Like this, gate insulation layer 25 and control gate 26a all are arranged in the groove, self are that groove structure surrounds by floating gate 23a basically.To be that groove is outside on the side of floating gate 23a form insulative sidewall 27, and source/ drain region 28 and 29 forms in the Semiconductor substrate 21 corresponding to the outside of floating gate.Silicide layer 30 forms on (exposure) surface on control gate 26a and the floating gate 23a, on the end face with the groove structure that is arranged on floating gate, be arranged on equally on each of source/ drain region 28 and 29, or rather, in surface corresponding to the Semiconductor substrate 21 in source/drain region.Insulation interbed 39 forms on the whole formation surface of Semiconductor substrate 21.A plurality of conductive plugs 31 are connected to each of control gate 26a and source/ drain region 28 and 29 by insulation interbed 39, to provide and the electrically contacting of external circuit, and (not shown) such as word line, bit line or source line for example.
As mentioned above, by utilizing according to nonvolatile memory of the present invention and manufacture method thereof, the contact-making surface that may improve between control gate 26a and the floating gate 23a is the size of relative surface area, thereby reduces power consumption owing to coupling efficiency improves.And, be used for first polysilicon layer 23 that floating gate forms by the etching of single stage etch process, forming the grid of device, thus prevent since during the etch process of the traditional stacked grid that are used to form nonvolatile memory such as flash memory device for example plasma damage cause pollution to gate insulation layer 25.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. nonvolatile memory comprises:
Semiconductor substrate;
The tunneling oxide layer is formed on the predetermined portions of described Semiconductor substrate;
Floating gate is formed on the described tunneling oxide layer, and described floating gate has groove structure;
Control gate is formed on the groove structure inside of described floating gate;
Gate insulation layer is arranged between described floating gate and the described control gate; And
Silicide layer is formed in the upper surface of described control gate and described floating gate.
2. nonvolatile memory according to claim 1 further comprises:
Source/drain region is formed in the described Semiconductor substrate on the either side of described floating gate; And
Insulative sidewall is formed on the side of described floating gate.
3. nonvolatile memory according to claim 1, wherein said gate insulation layer has oxide-nitride thing-oxide structure.
4. nonvolatile memory according to claim 2 further is included in the silicide layer that forms in the upper surface in described source region and drain region.
5. method that is used to make nonvolatile memory comprises:
On the predetermined portions of Semiconductor substrate, form the tunneling oxide layer;
On described tunneling oxide layer, be formed for forming first polysilicon layer of floating gate;
Form groove in described first polysilicon layer, described groove has desired depth;
On the surface of described first polysilicon layer, form gate insulation layer, thereby cover the inwall of the described groove that forms in described first polysilicon layer;
On described gate insulation layer, be formed for forming second polysilicon layer of control gate, thereby be retained in the described groove;
Carry out cmp for described second polysilicon layer and described gate insulation layer, come in described groove, to form described gate insulation layer and described control gate;
Use described first polysilicon layer of described photoresist pattern etching, form described floating gate;
In the upper surface of described control gate and described floating gate, form silicide layer.
6. the method that is used to make nonvolatile memory according to claim 5, wherein said first polysilicon layer has
Thickness.
7. the method that is used to make nonvolatile memory according to claim 5, wherein said first polysilicon layer forms by low-pressure chemical vapor deposition.
8. the method that is used to make nonvolatile memory according to claim 5, wherein the described groove that forms in described first polysilicon layer forms by the etch process that uses chlorine.
9. the method that is used to make nonvolatile memory according to claim 5, wherein the described groove that forms in described first polysilicon layer has
The degree of depth.
10. the method that is used to make nonvolatile memory according to claim 5, wherein said second polysilicon layer has
Thickness.
11. the method that is used to make nonvolatile memory according to claim 5, wherein said etching is an isotropic etching.
12. the method that is used to make nonvolatile memory according to claim 5 further comprises:
After forming described control gate, on the side of described floating gate, form insulative sidewall;
Formation source/drain region in the described Semiconductor substrate on the either side of described floating gate; And
Forming silicide layer on the upper surface of described floating gate and described control gate and on described Semiconductor substrate corresponding to described source/drain region.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040063869 | 2004-08-13 | ||
| KR1020040063869A KR100587396B1 (en) | 2004-08-13 | 2004-08-13 | Non-volatile memory device and Method for the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1734774A CN1734774A (en) | 2006-02-15 |
| CN100477230C true CN100477230C (en) | 2009-04-08 |
Family
ID=36077065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100903199A Expired - Fee Related CN100477230C (en) | 2004-08-13 | 2005-08-12 | Nonvolatile memory device and method for fabricating the same |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7371639B2 (en) |
| JP (1) | JP2006054466A (en) |
| KR (1) | KR100587396B1 (en) |
| CN (1) | CN100477230C (en) |
| DE (1) | DE102005037986B4 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811318A (en) * | 2012-11-08 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100870339B1 (en) | 2006-06-29 | 2008-11-25 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| CN102237365B (en) * | 2010-04-28 | 2013-01-02 | 中国科学院微电子研究所 | Flash memory device and manufacturing method thereof |
| KR101649967B1 (en) * | 2010-05-04 | 2016-08-23 | 삼성전자주식회사 | SEMICONDUCTOR DEVICES HAVING AN e-FUSE STRUCTURE AND METHODS OF FABRICATING THE SAME |
| JP5085688B2 (en) | 2010-06-10 | 2012-11-28 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Nonvolatile semiconductor memory transistor, nonvolatile semiconductor memory, and method of manufacturing nonvolatile semiconductor memory |
| US8681439B2 (en) | 2010-09-13 | 2014-03-25 | Lsi Corporation | Systems and methods for handling sector gaps in inter-track interference compensation |
| US8810940B2 (en) | 2011-02-07 | 2014-08-19 | Lsi Corporation | Systems and methods for off track error recovery |
| US8854753B2 (en) | 2011-03-17 | 2014-10-07 | Lsi Corporation | Systems and methods for auto scaling in a data processing system |
| US8689062B2 (en) | 2011-10-03 | 2014-04-01 | Lsi Corporation | Systems and methods for parameter selection using reliability information |
| US8443271B1 (en) | 2011-10-28 | 2013-05-14 | Lsi Corporation | Systems and methods for dual process data decoding |
| KR101903479B1 (en) * | 2012-08-24 | 2018-10-02 | 에스케이하이닉스 주식회사 | Semiconductor devcie and method for forming the same |
| US9337210B2 (en) | 2013-08-12 | 2016-05-10 | Micron Technology, Inc. | Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors |
| US9263577B2 (en) | 2014-04-24 | 2016-02-16 | Micron Technology, Inc. | Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors |
| US9472560B2 (en) | 2014-06-16 | 2016-10-18 | Micron Technology, Inc. | Memory cell and an array of memory cells |
| US9159829B1 (en) * | 2014-10-07 | 2015-10-13 | Micron Technology, Inc. | Recessed transistors containing ferroelectric material |
| US9305929B1 (en) | 2015-02-17 | 2016-04-05 | Micron Technology, Inc. | Memory cells |
| US9853211B2 (en) | 2015-07-24 | 2017-12-26 | Micron Technology, Inc. | Array of cross point memory cells individually comprising a select device and a programmable device |
| US10134982B2 (en) | 2015-07-24 | 2018-11-20 | Micron Technology, Inc. | Array of cross point memory cells |
| US10396145B2 (en) | 2017-01-12 | 2019-08-27 | Micron Technology, Inc. | Memory cells comprising ferroelectric material and including current leakage paths having different total resistances |
| CN108878434A (en) * | 2017-05-11 | 2018-11-23 | 北京兆易创新科技股份有限公司 | A kind of NOR type floating-gate memory and preparation method |
| US11170834B2 (en) | 2019-07-10 | 2021-11-09 | Micron Technology, Inc. | Memory cells and methods of forming a capacitor including current leakage paths having different total resistances |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4764480A (en) * | 1985-04-01 | 1988-08-16 | National Semiconductor Corporation | Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size |
| JP2735193B2 (en) | 1987-08-25 | 1998-04-02 | 株式会社東芝 | Nonvolatile semiconductor device and method of manufacturing the same |
| JPS6453577U (en) | 1987-09-28 | 1989-04-03 | ||
| JPH0474477A (en) * | 1990-07-17 | 1992-03-09 | Nec Corp | Non-volatile memory and its manufacture |
| JP2990493B2 (en) * | 1994-07-30 | 1999-12-13 | エルジイ・セミコン・カンパニイ・リミテッド | Memory device of nonvolatile semiconductor and its preparation |
| JPH09205154A (en) | 1996-01-25 | 1997-08-05 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US5707897A (en) * | 1996-05-16 | 1998-01-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors |
| US6087222A (en) * | 1998-03-05 | 2000-07-11 | Taiwan Semiconductor Manufacturing Company | Method of manufacture of vertical split gate flash memory device |
| US6084265A (en) * | 1998-03-30 | 2000-07-04 | Texas Instruments - Acer Incorporated | High density shallow trench contactless nonvolitile memory |
| US6225162B1 (en) * | 1999-07-06 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | Step-shaped floating poly-si gate to improve gate coupling ratio for flash memory application |
| FR2810161B1 (en) * | 2000-06-09 | 2005-03-11 | Commissariat Energie Atomique | ELECTRONIC MEMORY WITH DAMASCENE ARCHITECTURE AND METHOD OF MAKING SAID MEMORY |
| KR100617074B1 (en) | 2000-08-30 | 2006-08-30 | 매그나칩 반도체 유한회사 | flash EEPROM and method for manufacturing the same |
| JP3594550B2 (en) | 2000-11-27 | 2004-12-02 | シャープ株式会社 | Method for manufacturing semiconductor device |
| US6587396B1 (en) * | 2001-12-21 | 2003-07-01 | Winbond Electronics Corporation | Structure of horizontal surrounding gate flash memory cell |
| US6734055B1 (en) * | 2002-11-15 | 2004-05-11 | Taiwan Semiconductor Manufactoring Company | Multi-level (4 state/2-bit) stacked gate flash memory cell |
| KR100471575B1 (en) * | 2002-12-26 | 2005-03-10 | 주식회사 하이닉스반도체 | Method of manufacturing flash memory device |
| KR100586647B1 (en) * | 2003-10-06 | 2006-06-07 | 동부일렉트로닉스 주식회사 | Flash Memory Device And Method For Manufacturing The Same |
-
2004
- 2004-08-13 KR KR1020040063869A patent/KR100587396B1/en not_active IP Right Cessation
-
2005
- 2005-08-11 JP JP2005233530A patent/JP2006054466A/en active Pending
- 2005-08-11 DE DE102005037986A patent/DE102005037986B4/en not_active Expired - Fee Related
- 2005-08-12 CN CNB2005100903199A patent/CN100477230C/en not_active Expired - Fee Related
- 2005-08-15 US US11/206,257 patent/US7371639B2/en not_active Expired - Fee Related
-
2008
- 2008-04-15 US US12/103,682 patent/US7589372B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811318A (en) * | 2012-11-08 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN103811318B (en) * | 2012-11-08 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1734774A (en) | 2006-02-15 |
| US7371639B2 (en) | 2008-05-13 |
| US20060033150A1 (en) | 2006-02-16 |
| DE102005037986A1 (en) | 2006-03-16 |
| US7589372B2 (en) | 2009-09-15 |
| DE102005037986B4 (en) | 2010-10-28 |
| JP2006054466A (en) | 2006-02-23 |
| KR20060015050A (en) | 2006-02-16 |
| KR100587396B1 (en) | 2006-06-08 |
| US20080191267A1 (en) | 2008-08-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100477230C (en) | Nonvolatile memory device and method for fabricating the same | |
| US6903968B2 (en) | Nonvolatile memory capable of storing multibits binary information and the method of forming the same | |
| US6559501B2 (en) | Method for forming split-gate flash cell for salicide and self-align contact | |
| US6117733A (en) | Poly tip formation and self-align source process for split-gate flash cell | |
| US6724036B1 (en) | Stacked-gate flash memory cell with folding gate and increased coupling ratio | |
| US6838725B2 (en) | Step-shaped floating poly-si gate to improve a gate coupling ratio for flash memory application | |
| US6753569B2 (en) | Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation | |
| US6373095B1 (en) | NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area | |
| CN101154666B (en) | Semi-conductor memory device and manufacturing method thereof | |
| US7056792B2 (en) | Stacked gate flash memory device and method of fabricating the same | |
| US6784039B2 (en) | Method to form self-aligned split gate flash with L-shaped wordline spacers | |
| CN1956171B (en) | Methods of forming non-volatile memory devices and devices formed thereby | |
| US20140061758A1 (en) | Nonvolatile memory device and method of manufacturing the same | |
| US6720219B2 (en) | Split gate flash memory and formation method thereof | |
| US7700991B2 (en) | Two bit memory structure and method of making the same | |
| US6818948B2 (en) | Split gate flash memory device and method of fabricating the same | |
| US7485919B2 (en) | Non-volatile memory | |
| US20040121545A1 (en) | Method to fabricate a square word line poly spacer | |
| US20110230024A1 (en) | Method for manufacturing non-volatile memory | |
| CN101399204B (en) | Grid structure, flash memory and method for producing the same | |
| US20070048936A1 (en) | Method for forming memory cell and periphery circuits | |
| US20090127612A1 (en) | Semiconductor device having a gate structure | |
| CN100386864C (en) | Non-volatile memory and its production | |
| KR20050011501A (en) | Flash memory cell and method for manufacturing thereof | |
| US20100163999A1 (en) | Semiconductor element and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090408 Termination date: 20130812 |