CN100476559C - Thin film transistor array substrate and liquid crystal dispaly panel - Google Patents
Thin film transistor array substrate and liquid crystal dispaly panel Download PDFInfo
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- CN100476559C CN100476559C CNB2005101144720A CN200510114472A CN100476559C CN 100476559 C CN100476559 C CN 100476559C CN B2005101144720 A CNB2005101144720 A CN B2005101144720A CN 200510114472 A CN200510114472 A CN 200510114472A CN 100476559 C CN100476559 C CN 100476559C
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Abstract
A substrate of film transistor array consists of substrate having display and peripheral circuit region on base plate, arranging scan line and data line on substrate, driving display region to be multiple pixel region with pixel unit being driven by said scan and data lines, setting scan welding pad and data welding pad in peripheral circuit region and connecting them to scan and data lines, setting the first and the second switch elements in said circuit region as the first switch element being set between two adjacent scan welding pads and the second switch element being set between two adjacent data welding pads.
Description
Technical field
The present invention relates to a kind of component array baseplate (device array substrate) and display panel (display panel), and be particularly related to a kind of thin-film transistor array base-plate (Thin Film Transistor array substrate with antistatic protection function (anti-static capability), TFT arraysubstrate) and display panels (Liquid Crystal Display panel, LCD panel).
Background technology
In recent years, because the maturation of photoelectric technology and semiconductor fabrication, driven the flourish of flat-panel screens (Flat Panel Display), Thin Film Transistor-LCD (Thin FilmTransistor Liquid Crystal Display wherein, TFT-LCD), and become the main flow of display product gradually based on its low voltage operating, advantage such as operating speed is fast, in light weight and volume is little.
Thin Film Transistor-LCD mainly comprises display panels and backlight module (backlightmodule), wherein display panels is by colored optical filtering substrates (Color Filter, C/F), thin-film transistor array base-plate (Thin Film Transistor array substrate, TFT arraysubstrate) and the liquid crystal layer that is arranged between this two substrates constitute, and backlight module is in order to provide this display panels required area source, so that LCD reaches the effect of demonstration.
Fig. 1 is a kind of synoptic diagram of known thin-film transistor array base-plate.Please refer to Fig. 1, this thin-film transistor array base-plate 100 comprises substrate 110, multi-strip scanning line 120 and data line 130, pixel cell 150, scanning weld pad 160, data weld pad 170, inner electrostatic defending ring 192 (inner guardring) and exterior static protective ring 194.
Substrate 110 has viewing area 112 (display region) and perimeter circuit district 114 (peripheral circuit region).Sweep trace 120 is arranged on the substrate 110 with data line 130, and wherein sweep trace 120 and data line 130 are in viewing area 112 being divided into a plurality of pixel regions 140.Pixel cell 150 is arranged at pixel region 140 respectively in one of them, and it drives by sweep trace 120 and data line 130, and this pixel cell 150 is made up of thin film transistor (TFT) 152 and pixel electrode 154.
Please continue with reference to Fig. 1, scanning weld pad 160 is arranged in the perimeter circuit district 114, and scanning weld pad 160 is electrically connected to sweep trace 120.Data weld pad 170 is arranged in the perimeter circuit district 114, and data weld pad 170 is electrically connected to data line 130.Inner electrostatic defending ring 192 is arranged in the perimeter circuit district 114, and between scanning weld pad 160 and viewing area 112 and between data weld pad 170 and viewing area 112, and inner electrostatic defending ring 192 is electrically connected to sweep trace 120 and data line 130.This inner electrostatic defending ring 192 is the electrostatic discharge protection circuits that are made of active switching element (as thin film transistor (TFT) or diode) and its sweep trace 120 on every side and data line 130.In addition, exterior static protective ring 194 (out guard ring) is arranged in the perimeter circuit district 114, and between scanning weld pad 160 and substrate 110 outer rims and between data weld pad 160 and substrate 110 outer rims, and exterior static protective ring 194 is electrically connected to sweep trace 120 and above-mentioned these data lines 130 respectively.Similarly, this outside electrostatic defending ring 194 is the electrostatic discharge protection circuits that are made of active switching element (as thin film transistor (TFT) or diode) and its sweep trace 120 on every side and data line 130.
Because thin-film transistor array base-plate 100 is in the process of making, usually can be because external factor, for example artificial carrying or environmental change etc., and in substrate, produce the phenomenon of buildup of static electricity.Thus, after electric charge is accumulate to some, just may cause circuit or thin film transistor (TFT) 152 on the thin-film transistor array base-plate 100 to wreck because of static discharge.So, just make static lead whole base plate off, thereby avoided at the electrostatic breakdown of localized accumulated pixel cell 150 or the circuit in the viewing area 112 by above-mentioned inside electrostatic defending ring 192 and exterior static protective ring 194.
In more detail, inner electrostatic defending ring 192 or exterior static protective ring 194 are by the structure of active switching element (not shown) serial connection sweep trace 120 with data line 130, when the static on sweep trace 120 and data line 130 or the thin film transistor (TFT) 152 overloads, just can open active switching element and make electrostatic dispersion to inner electrostatic defending ring 192 and/or exterior static protective ring 194, and reach the function of electrostatic defending.
But, only utilize the design of above-mentioned inside electrostatic defending ring 192 and exterior static protective ring 194, still have the phenomenon that electrostatic breakdown may take place, especially in the position of scanning weld pad 160, because its area is accumulated a large amount of static more greatly and especially easily with data weld pad 170.So when static can't be led off, the phenomenon that circuit on the thin-film transistor array base-plate 100 or thin film transistor (TFT) 152 still have electrostatic breakdown produced.
Summary of the invention
In view of the foregoing, purpose of the present invention just provides a kind of thin-film transistor array base-plate, a large amount of static that it is suitable for leading off on the substrate is accumulated, and then reduce the electrostatic breakdown phenomenon that is produced on the substrate.
A further object of the present invention provides a kind of display panels, and it utilizes above-mentioned thin-film transistor array base-plate, and makes this display panels have good antistatic capacity.
Based on above-mentioned purpose or other purpose, the present invention proposes a kind of thin-film transistor array base-plate, comprises substrate, multi-strip scanning line and many data lines, a plurality of pixel cell, a plurality of scanning weld pad, a plurality of data weld pad, a plurality of first on-off element and a plurality of second switch elements.Substrate has viewing area and perimeter circuit district.Sweep trace and data line are arranged on the substrate, and wherein sweep trace and data line are divided into a plurality of pixel regions with the viewing area.Pixel cell is arranged at pixel region respectively in one of them, and it drives by sweep trace and data line.The scanning weld pad is arranged in the perimeter circuit district, and the scanning weld pad is electrically connected to sweep trace.The data weld pad is arranged in the perimeter circuit district, and the data weld pad is electrically connected to data line.First on-off element is arranged in the perimeter circuit district, wherein be provided with at least one first on-off element between adjacent two scanning weld pads, and each first on-off element can be electrically connected with the scanning weld pad that is positioned at its both sides.The second switch element is arranged in the perimeter circuit district, wherein is provided with at least one second switch element between adjacent two data weld pads, and wherein each second switch element can be electrically connected with the data weld pad that is positioned at its both sides.And, first on-off element and second switch element one of them comprises the source/drain of asymmetric setting at least.
In one embodiment of this invention, above-mentioned is provided with two first on-off elements between adjacent two scanning weld pads, and two first on-off elements are to be provided with parallel way.
In one embodiment of this invention, above-mentioned is provided with two second switch elements between adjacent two data weld pads, and two second switch elements are to be provided with parallel way.
In one embodiment of this invention, each above-mentioned first on-off element comprises floating grid, gate insulation layer, semiconductor layer and source/drain.Floating grid is arranged on the substrate.Gate insulation layer covers floating grid.Semiconductor layer is arranged on the gate insulation layer of floating grid top.Source/drain is arranged on the semiconductor layer, and wherein source/drain can be electrically connected with the scanning weld pad that is positioned at its both sides.In addition, the length of the source electrode of above-mentioned source/drain and drain electrode is unequal.
In one embodiment of this invention, each above-mentioned second switch element comprises floating grid, gate insulation layer, semiconductor layer and source/drain.Floating grid is arranged on the substrate.Gate insulation layer covers floating grid.Semiconductor layer is arranged on the gate insulation layer of floating grid top.Source/drain is arranged on the semiconductor layer, and wherein source/drain can be electrically connected with the data weld pad that is positioned at its both sides.In addition, the length of the source electrode of above-mentioned source/drain and drain electrode is unequal.
In one embodiment of this invention, each above-mentioned pixel cell comprises thin film transistor (TFT) and pixel electrode.Thin film transistor (TFT) is arranged at wherein in the pixel region.Pixel electrode is arranged at wherein in the pixel region, and is electrically connected with thin film transistor (TFT).
In one embodiment of this invention, above-mentioned thin-film transistor array base-plate, also comprise a plurality of inner electrostatic defending rings (inner guard ring), it is arranged in the perimeter circuit district, and between scanning weld pad and viewing area and between data weld pad and viewing area, and inner electrostatic defending ring is electrically connected to sweep trace and data line.
In one embodiment of this invention, above-mentioned thin-film transistor array base-plate, also comprise a plurality of exterior static protective rings (out guard ring), it is arranged in the perimeter circuit district, and between scanning weld pad and substrate outer rim and between data weld pad and substrate outer rim, and the exterior static protective ring is electrically connected to sweep trace and data line respectively.
Based on above-mentioned purpose or other purpose, the present invention reintroduces a kind of display panels, comprises colored optical filtering substrates, thin-film transistor array base-plate and liquid crystal layer.This thin-film transistor array base-plate can be aforesaid thin-film transistor array base-plate, and liquid crystal layer is arranged between colored optical filtering substrates and the thin-film transistor array base-plate.
The present invention is because of adopting first on-off element and second switch element, and it is separately positioned between adjacent two scanning weld pads and adjacent two the data weld pads, so when static is accumulated in scanning weld pad or data weld pad in a large number, the electric charge coupling effect can take place in static on first on-off element and/or second switch element, and will make win on-off element and/or the unlatching of second switch element.By this, static can conduct between adjacent sweep trace or adjacent data line, and reduces the electrostatic breakdown phenomenon that produces on thin-film transistor array base-plate.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is a kind of synoptic diagram of known thin-film transistor array base-plate.
Fig. 2 is the synoptic diagram of a kind of thin-film transistor array base-plate of preferred embodiment of the present invention.
Fig. 3 is that scanning weld pad among Fig. 2 is in the amplification schematic top plan view of a-quadrant.
Fig. 3 A is along the diagrammatic cross-section of A-A ' line among Fig. 3.
Fig. 3 B is along the diagrammatic cross-section of B-B ' line among Fig. 3.
Fig. 4 is that scanning weld pad among Fig. 2 is in the amplification schematic top plan view in B zone.
Fig. 4 A is along the diagrammatic cross-section of C-C ' line among Fig. 4.
Fig. 4 B is along the diagrammatic cross-section of D-D ' line among Fig. 4.
Fig. 5 is the synoptic diagram of a kind of display panels of preferred embodiment of the present invention.
The main element description of symbols
100,200: thin-film transistor array base-plate
110,210: substrate
112,212: the viewing area
114,214: the perimeter circuit district
120,220: sweep trace
130,230: data line
140,240: pixel region
150,250: pixel cell
152,252: thin film transistor (TFT)
154,254: pixel electrode
160,260: the scanning weld pad
170,270: the data weld pad
192,292: inner electrostatic defending ring
194,294: the exterior static protective ring
280a, 280a ': first on-off element
280b: second switch element
282a, 282b: floating grid
284: gate insulation layer
286a, 286b: semiconductor layer
288a, 288b: source/drain
300a, 300b, 300c: opening
310: conductive layer
400: display panels
410: colored optical filtering substrates
420: thin-film transistor array base-plate
430: liquid crystal layer
A, B: zone
A-A ', B-B ', C-C ', D-D ': profile line
L1, L2, L3, L4: contact length
Embodiment
Fig. 2 is the synoptic diagram of a kind of thin-film transistor array base-plate of preferred embodiment of the present invention.Please refer to Fig. 2, this thin-film transistor array base-plate 200 comprises substrate 210, multi-strip scanning line 220 and data line 230, a plurality of pixel cell 250, a plurality of scanning weld pad 260 and data weld pad 270, a plurality of first on-off element 280a and a plurality of second switch element 280b.
Substrate 210 has viewing area 212 and perimeter circuit district 214.Sweep trace 220 is arranged on the substrate 210 with data line 230, and wherein sweep trace 220 is divided into a plurality of pixel regions 240 with data line 230 with viewing area 212.Each pixel cell 250 is arranged at pixel region 240 in one of them, and it drives by sweep trace 220 and data line 230.Scanning weld pad 260 is arranged in the perimeter circuit district 214, and scanning weld pad 260 is electrically connected to sweep trace 220.Data weld pad 270 is arranged in the perimeter circuit district 214, and data weld pad 270 is electrically connected to data line 230.The first on-off element 280a is arranged in the perimeter circuit district 214, wherein between adjacent two scanning weld pads 260, be provided with at least one first on-off element 280a (having represented two among Fig. 2), and each first on-off element 280a can be electrically connected with the scanning weld pad 260 that is positioned at its both sides.Second switch element 280b is arranged in the perimeter circuit district 214, wherein be provided with at least one second switch element 280b (having represented two among Fig. 2) between adjacent two data weld pad 270, wherein each second switch element 280b can be electrically connected with the data weld pad 270 that is positioned at its both sides.
Please refer to Fig. 2, in one embodiment of this invention, each pixel cell 250 comprises thin film transistor (TFT) 252 and pixel electrode 254.Thin film transistor (TFT) 252 is arranged at wherein in the pixel region 240.Pixel electrode 254 is arranged at wherein in the pixel region 240, and is electrically connected with thin film transistor (TFT) 252.
In addition, as shown in Figure 2, thin-film transistor array base-plate 200 for example also comprises a plurality of inner electrostatic defending rings 292, it is arranged in the perimeter circuit district 214, and between scanning weld pad 260 and viewing area 214 and between data weld pad 270 and viewing area 214, and inner electrostatic defending ring 292 is electrically connected to sweep trace 220 and data line 230.And, thin-film transistor array base-plate 200 for example also comprises a plurality of exterior static protective rings 294, it is arranged in the perimeter circuit district 214, and between scanning weld pad 260 and substrate 210 outer rims and between data weld pad 270 and substrate 210 outer rims, and exterior static protective ring 294 is electrically connected to sweep trace 220 and data line 230 respectively.
In more detail, inner electrostatic defending ring 292 or exterior static protective ring 294 are by the circuit structure of active switching element (not shown) serial connection sweep trace 220 with data line 230, when sweep trace 220 is accumulated in a large number with the static on data line 230 or the thin film transistor (TFT) 252, just can open active switching element and make electrostatic dispersion to inner electrostatic defending ring 292 and/or exterior static protective ring 294, to reach the function of electrostatic defending.But,, still have to produce a large amount of buildup of static electricity in the scanning weld pad 260 or the zone of data weld pad 270.Therefore, the present invention is provided with the first on-off element 280a and second switch element 280b respectively between adjacent two scanning weld pads 260 and adjacent two data weld pads 270.
In one embodiment of this invention, between adjacent two scanning weld pads 260, be provided with two first on-off element 280a, and two first on-off element 280a are provided with parallel way.In addition, for example be to be provided with two second switch element 280b between the adjacent two data weld pad 270, and two second switch element 280b are provided with parallel way, and so, static promptly can conduct by the mode of transmitted in both directions (two-way conducting).
Fig. 3 be scanning weld pad among Fig. 2 in the amplification schematic top plan view of a-quadrant, Fig. 3 A be among Fig. 3 along the diagrammatic cross-section of A-A ' line, Fig. 3 B is along the diagrammatic cross-section of B-B ' line among Fig. 3.
Please jointly with reference to Fig. 3 and Fig. 3 A, in one embodiment of this invention, each first on-off element 280a comprises floating grid 282a, gate insulation layer 284, semiconductor layer 286a and source/drain 288a.Floating grid 282a is arranged on the substrate 210.Gate insulation layer 284 covers floating grid 282a.Semiconductor layer 286a is arranged on the gate insulation layer 284 of floating grid 282a top.Source/drain 288a is arranged on the semiconductor layer 286a, and wherein source/drain 288a can be electrically connected with the scanning weld pad 260 that is positioned at its both sides.
The technology of known formation pel array, be to form elements such as lead (for example being sweep trace, data line), thin film transistor (TFT) and pixel electrode on substrate 210, this technology can be five road photo etched mask technologies, four road photo etched mask technologies or any known pel array technology.Please be simultaneously with reference to Fig. 3, Fig. 3 A and Fig. 3 B, with five road photo etched mask technologies is example, as the floating grid 282a of the sweep trace 220 represented among Fig. 3, scanning weld pad 260 and the first on-off element 280a is to utilize the first road photo etched mask technology and make (Metal 1), and it directly is arranged on the substrate 210.Then, on substrate 210, can form gate insulation layer 284 again to cover sweep trace 220, scanning weld pad 260 and floating grid 282a comprehensively.Then, go up making semiconductor layer 286a with the second road photo etched mask technology in floating grid 282a.Follow again, make the metal level (Metal 2) of source/drain 288a with the 3rd road photo etched mask technology.Afterwards; comprehensive again protective mulch 300 on substrate 210; define opening 300a and opening 300b with the 4th road photo etched mask technology again; just the position of the protective seam above sweep trace 220 300 forms opening 300a; this opening 300a exposes the metal level (as shown in Figure 3A) of source/drain 288a; and in the gate insulation layer 284 of scanning above the weld pad 260 and protective seam 300, make opening 300b, make scanning weld pad 260 come out (shown in Fig. 3 B).Then, making conductive layer 310 with the 5th road photo etched mask technology on scanning weld pad 260 and sweep trace 220 again (for example is indium tin oxide layer, ITO).It should be noted that as conductive layer 310 represented among Fig. 3, Fig. 3 A and Fig. 3 B and just can pass through opening 300a and opening 300b, and make source/drain 288a and scanning weld pad 260 be electrically connected to each other.
That is to say that when one of them scanning weld pad 260 accumulation of representing as Fig. 3 have a large amount of static, this static can conduct to source/drain 288a among the first on-off element 280a by scanning weld pad 260.Then, will produce electric charge coupling effect (coupling) between source/drain 288a and the floating grid 282a, and the first on-off element 280a is opened.Consequently, be accumulated in the static on one of them scanning weld pad 260, it can be transmitted to by the semiconductor layer 286a of the first on-off element 280a on its adjacent sweep trace 220.Therefore, static just can localized accumulated not scan on the weld pad 260 at one, and can avoid producing in the adjacent domain of scanning weld pad 260 phenomenon of electrostatic breakdown.
In addition, it should be noted that the source/drain 288a among the first on-off element 280a asymmetricly is provided with or is provided with symmetrically.Please refer to Fig. 3, in one embodiment, source/drain 288a among the first on-off element 280a is provided with in asymmetrical mode, at this moment, under limited space, can make source/drain 288a have the ability of static focus preferably, and can improve the electric charge coupling effect between source/drain 288a and the floating grid 282a.In more detail, the length of a side source electrode among the first on-off element 280a (or drain electrode) is L1, and the length of the opposing party's drain electrode (or source electrode) is L2, and the length of L2 is greater than the length of L1.Because L2 is longer, so but the drain electrode with L2 length will have bigger space static electricity gathered, thereby make easier generation electric charge coupling effect between this drain electrode and the floating grid 282a under it.Consequently, when buildup of static electricity, the first on-off element 280a is easier unlatching, and makes static be transmitted to a side of the source electrode with L1 length from a side of drain electrode with L2 length.
In addition, please continue with reference to Fig. 3, when between two adjacent scanning weld pads 260 two first on-off element 280a, 280a ' being set, another first on-off element 280a ' adopts asymmetric setting.Particularly, be arranged on the source/drain 288a of the floating grid 282a top of this first on-off element 280a ' this moment, its length can be opposite with above-mentioned situation.That is to say, another the first on-off element 280a ' represented as Fig. 3, the length of the source electrode of one side (or drain electrode) is L3, and the length of the opposing party's drain electrode (or source electrode) is L4, and the length of L3 is greater than the length of L4.Consequently, static can be transmitted to a side of the drain electrode (or source electrode) with L4 length from a side of source electrode with L3 length (or drain electrode).In sum, as the first on-off element 280a, 280a ' that two parallel connections are set between scanning weld pad 260, and when its source/drain 288a is asymmetric the setting, can be faster except the unlatching of the first on-off element 280a, 280a ', the conduction orientation of static also can be to be undertaken by the mode of two-way circulate (two-way conducting).
Fig. 4 be scanning weld pad among Fig. 2 in the amplification schematic top plan view in B zone, Fig. 4 A be among Fig. 4 along the diagrammatic cross-section of C-C ' line, Fig. 4 B is along the diagrammatic cross-section of D-D ' line among Fig. 4.
Please jointly with reference to Fig. 4 and Fig. 4 A, in one embodiment of this invention, each second switch element 280b comprises floating grid 282b, gate insulation layer 284, semiconductor layer 286b and source/drain 288b.Floating grid 282b is arranged on the substrate 210.Gate insulation layer 284 covers floating grid 282b.Semiconductor layer 286b is arranged on the gate insulation layer 284 of floating grid 282b top.Source/drain 288b is arranged on the semiconductor layer 286b, and wherein source/drain 288b can be electrically connected with the data weld pad 270 that is positioned at its both sides.
Similarly, when making above-mentioned element, employed technology can be five road photo etched mask technologies, four road photo etched mask technologies or any known pel array technology.With five road photo etched mask technologies is example, and please be simultaneously with reference to Fig. 4, Fig. 4 A and Fig. 4 B, and the floating grid 282b of second switch element 280b is (Metal 1) that utilizes the first road photo etched mask technology made, and it is directly to be made on the substrate 210.Then, on substrate 210, can form gate insulation layer 284 again to cover this floating grid 282b comprehensively.Then, go up making semiconductor layer 286b with the second road photo etched mask technology in floating grid 282b.Follow, with the metal level (Metal 2) of the 3rd road photo etched mask technology making data line 230, data weld pad 270 and source/drain 288b, particularly, it is with one deck metal level again.Afterwards; comprehensive again protective mulch 300 on substrate 210; define opening 300c with the 4th road photo etched mask technology again, just make opening 300c in gate insulation layer above data weld pad 270 284 and the protective seam 300, and data weld pad 270 is come out.Then, making conductive layer 310 with the 5th road photo etched mask technology on data weld pad 270 and data line 230 again (for example is indium tin oxide layer, ITO).It should be noted that source/drain 288b and data weld pad 270 as shown in Fig. 4, Fig. 4 A and Fig. 4 B are same metal levels, so its source/drain 288b and data weld pad 270 are electrically connected to each other.
That is to say that when one of them data weld pad 270 accumulations of representing as Fig. 4 have a large amount of static, this static can conduct to source/drain 288b the second switch element 280b from data weld pad 270.Then, just can produce electric charge coupling effect (coupling) between source/drain 288b and the floating grid 282b, and second switch element 280b is opened.Consequently, be accumulated in the static on one of them data weld pad 270, just can be transmitted on its adjacent data line 230 by the semiconductor layer 286b of second switch element 280b, so, static just can not be accumulated on the data weld pad 270, and can avoid producing in the adjacent domain of data weld pad 270 phenomenon of electrostatic breakdown.
In addition, similarly, the source/drain 288b among the second switch element 280b asymmetricly is provided with or is provided with symmetrically.The purpose of this setting, mode and effect have illustrated when introducing the first on-off element 280a in above-mentioned, will no longer have been described in detail at this.In a word, when two second switch element 280b are set between data weld pad 270, and when its source/drain 288b is asymmetric the setting, can be faster except the unlatching of second switch element 280b, the conduction orientation of static also can be to adopt the mode that two-way circulates and carry out.
In sum, the setting of first on-off element and second switch element can utilize five general road photo etched mask technologies and forms, so do not need to increase extra processing step.In addition, first on-off element and second switch element are separately positioned between adjacent two scanning weld pads and adjacent two the data weld pads, so when buildup of static electricity is on scanning weld pad or data weld pad, the electric charge coupling effect that static can take place on first on-off element and/or second switch element, and make win on-off element and/or the unlatching of second switch element.By this, promptly can reduce static and exceedingly be accumulated on local the scanning weld pad and data weld pad, and and then minimizing electrostatic breakdown phenomenon.In addition, above-mentioned thin-film transistor array base-plate is applied to the making of display panels, can obtains having the display panels of preferable electrostatic protection effect.
Fig. 5 is the synoptic diagram of a kind of display panels of preferred embodiment of the present invention.This display panels 400 comprises colored optical filtering substrates 410, thin-film transistor array base-plate 420 and liquid crystal layer 430.This thin-film transistor array base-plate 420 for example is a thin-film transistor array base-plate 200 as shown in Figure 2, and liquid crystal layer 430 is arranged between colored optical filtering substrates 410 and the thin-film transistor array base-plate 420.
Colored optical filtering substrates 410 is provided with common electrode (common electrode) (not shown) and colour filter array layer (color filter array) (not shown), can form electric field between the pixel electrode (not shown) of common electrode and thin-film transistor array base-plate 420, and make the liquid crystal molecule between colored optical filtering substrates 410 and thin-film transistor array base-plate 420 rotate, and then change the incident light intensity.In addition, the colour filter array layer makes display panels 500 be able to full-colorization.And owing to the thin-film transistor array base-plate 200 that can adopt as shown in Figure 2, therefore, display panels 400 of the present invention will have good antistatic capacity.
In sum, thin-film transistor array base-plate of the present invention and display panels have following advantage:
(1) utilizes first on-off element and the second switch element be separately positioned between adjacent two scanning weld pads and adjacent two the data weld pads, so when static was accumulated in scanning weld pad or data weld pad in a large number, first on-off element and/or second switch element will be opened.By this, static promptly can conduct between adjacent sweep trace or adjacent data line, and eliminates the electrostatic breakdown phenomenon that a large amount of static cause in the regional area accumulation.
(2) under limited space, the source/drain of first on-off element and second switch element is to adopt asymmetric setting, so when buildup of static electricity is on scanning weld pad or data weld pad, first on-off element and second switch element can be opened with fast speeds, and static is transmitted on the contiguous sweep trace or data line.
(3) utilize first on-off element of two parallel connections or the second switch element of two parallel connections, the conduction orientation of static will be carried out in the mode that two-way circulates.
(4) first on-off elements and second switch element can be made by known five road photo etched mask technologies, therefore, do not need to increase extra processing step.
When (5) thin-film transistor array base-plate that will have an antistatic capacity is applied to display panels, can be improved by the caused electrostatic breakdown phenomenon of buildup of static electricity, and makes display panels have good runnability.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (15)
1. thin-film transistor array base-plate is characterized in that comprising:
Substrate has viewing area and perimeter circuit district;
Multi-strip scanning line and many data lines are arranged on this substrate, and wherein above-mentioned these sweep traces and above-mentioned these data lines are divided into a plurality of pixel regions with this viewing area;
A plurality of pixel cells be arranged at above-mentioned these pixel regions respectively in one of them, and it drive by above-mentioned these sweep traces and above-mentioned these data lines;
A plurality of scanning weld pads are arranged in this perimeter circuit district, and above-mentioned these scanning weld pads are electrically connected to above-mentioned these sweep traces;
A plurality of data weld pads are arranged in this perimeter circuit district, and above-mentioned these data weld pads are electrically connected to above-mentioned these data lines;
A plurality of first on-off elements are arranged in this perimeter circuit district, wherein are provided with at least one first on-off element between two adjacent above-mentioned scanning weld pads, and each first on-off element can be electrically connected with above-mentioned these scanning weld pads that are positioned at its both sides; And
A plurality of second switch elements are arranged in this perimeter circuit district, wherein are provided with at least one second switch element between two adjacent above-mentioned data weld pads, and wherein each second switch element can be electrically connected with above-mentioned these data weld pads that are positioned at its both sides;
Wherein, this first on-off element and this second switch element one of them comprises the source/drain of asymmetric setting at least.
2. thin-film transistor array base-plate according to claim 1 is characterized in that being provided with two first on-off elements between two adjacent above-mentioned scanning weld pads.
3. thin-film transistor array base-plate according to claim 2 is characterized in that above-mentioned two first on-off elements are to be provided with parallel way.
4. thin-film transistor array base-plate according to claim 1 is characterized in that being provided with two second switch elements between two adjacent above-mentioned data weld pads.
5. thin-film transistor array base-plate according to claim 4 is characterized in that above-mentioned two second switch elements are to be provided with parallel way.
6. thin-film transistor array base-plate according to claim 1 is characterized in that this first on-off element comprises:
Floating grid is arranged on this substrate;
Gate insulation layer covers this floating grid;
Semiconductor layer is arranged on this gate insulation layer of this floating grid top; And
The source/drain of described asymmetric setting is arranged on this semiconductor layer, and wherein the source/drain of this asymmetric setting can be electrically connected with above-mentioned these scanning weld pads that are positioned at its both sides.
7. thin-film transistor array base-plate according to claim 6 is characterized in that the length of the source electrode of source/drain of this asymmetric setting and drain electrode is unequal.
8. thin-film transistor array base-plate according to claim 2 is characterized in that described two first on-off elements include the source/drain of asymmetric setting.
9. thin-film transistor array base-plate according to claim 1 is characterized in that this second switch element comprises:
Floating grid is arranged on this substrate;
Gate insulation layer covers this floating grid;
Semiconductor layer is arranged on this gate insulation layer of this floating grid top; And
The source/drain of described asymmetric setting is arranged on this semiconductor layer, and wherein the source/drain of this asymmetric setting can be electrically connected with above-mentioned these data weld pads that are positioned at its both sides.
10. thin-film transistor array base-plate according to claim 9 is characterized in that the length of the source electrode of source/drain of this asymmetric setting and drain electrode is unequal.
11. thin-film transistor array base-plate according to claim 4 is characterized in that described two second switch elements include the source/drain of asymmetric setting.
12. thin-film transistor array base-plate according to claim 1 is characterized in that each pixel cell comprises:
Thin film transistor (TFT) is arranged at wherein in the pixel region; And
Pixel electrode is arranged at wherein in the pixel region, and is electrically connected with this thin film transistor (TFT).
13. thin-film transistor array base-plate according to claim 1, it is characterized in that also comprising a plurality of inner electrostatic defending rings, be arranged in this perimeter circuit district, and between above-mentioned these scanning weld pads and this viewing area and between above-mentioned these data weld pads and this viewing area, above-mentioned these inner electrostatic defending rings are electrically connected to above-mentioned these sweep traces and above-mentioned these data lines.
14. thin-film transistor array base-plate according to claim 1, it is characterized in that also comprising a plurality of exterior static protective rings, be arranged in this perimeter circuit district, and between above-mentioned these scanning weld pads and this substrate outer rim and between above-mentioned these data weld pads and this substrate outer rim, above-mentioned these exterior static protective rings are electrically connected to above-mentioned these sweep traces and above-mentioned these data lines respectively.
15. a display panels is characterized in that comprising:
Colored optical filtering substrates;
Thin-film transistor array base-plate, it is according to claim 1; And
Liquid crystal layer is arranged between this colored optical filtering substrates and this thin-film transistor array base-plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101144720A CN100476559C (en) | 2005-10-27 | 2005-10-27 | Thin film transistor array substrate and liquid crystal dispaly panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101144720A CN100476559C (en) | 2005-10-27 | 2005-10-27 | Thin film transistor array substrate and liquid crystal dispaly panel |
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| CN1955825A CN1955825A (en) | 2007-05-02 |
| CN100476559C true CN100476559C (en) | 2009-04-08 |
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| CN103698953B (en) | 2013-12-30 | 2016-07-06 | 京东方科技集团股份有限公司 | A kind of array base palte, display floater and display device |
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Effective date of registration: 20161205 Address after: 430070 Hubei City, Wuhan Province, East Lake Development Zone, high tech Avenue, No. 666 biological city C5 building, Patentee after: Wuhan Hua Xing photoelectricity technology corporation, Ltd. Address before: The Marshall Islands Majuro Adger Island Road trust company Tektronix Tektronix Adger areas MH96960 Patentee before: Hao Chi intangible asset management Investment Limited |