CN100468375C - Method for raising writing speed of memory card - Google Patents
Method for raising writing speed of memory card Download PDFInfo
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- CN100468375C CN100468375C CNB2006100875390A CN200610087539A CN100468375C CN 100468375 C CN100468375 C CN 100468375C CN B2006100875390 A CNB2006100875390 A CN B2006100875390A CN 200610087539 A CN200610087539 A CN 200610087539A CN 100468375 C CN100468375 C CN 100468375C
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Abstract
A method for raising data writing-in speed of storage card includes sending data to temporary data storage region at buffer storage region of storage card by host through data bus if response of storage card is detected after write-command is sent by host and simultaneously receiving response continuously by host through command bus then writing data in temporary data storage region into flash memory of storage card in sequence if correct response is received by host.
Description
Technical field
The present invention relates to the method that a kind of storage card writes data, relate in particular to a kind of method that improves writing speed of memory card.
Background technology
The read-write communication protocol of existing main frame and storage card is as follows: during read data, main frame sends read command, waits for the storage card response, and this response has a start bit, and in a single day main frame detects this start bit, and data bus just can receive data.Therefore, main frame distributes read command and need not wait for and receive whole responses, just can read data; And when writing data, but be that main frame distributes write order and receives after the correct response, just can write data.Because order and response communicate by command line, and data communicate by data bus, these two buses can be communicated by letter simultaneously.In the call duration time of order and response, data bus always is in idle state, has only after command line is received correct response in writing data manipulation, and data bus could transmit data.Therefore, this communication protocols parliament incurs loss through delay the call duration time of data, thereby reduces the traffic rate that writes data manipulation.
Summary of the invention
Therefore technical matters to be solved by this invention provides a kind of method that improves writing speed of memory card, and this method can reduce the idle state of storing card data bus, shortens the time that storing card data writes, and guarantees to write the validity of data.
The present invention specifically is achieved in that
A kind of method that improves writing speed of memory card, at first set up an ephemeral data memory block at the buffer area of storage card, this method is carried out following steps: after main frame sends write order, if detect the response of storage card, then main frame sends data to the ephemeral data memory block of storage card buffer area by data bus, simultaneously, main frame continues to receive response by command line; If main frame receives correct response, then the data with the ephemeral data memory block write in the flash memory of storage card successively.
Press such scheme, the described response that detects storage card is that to detect the start bit of this response be low level signal.
Press such scheme, if storage card provides errored response, then storage card is ignored all data transmission that arrive subsequently and is remained on accepting state; Simultaneously, main frame stops to send data.
Press such scheme, described storage card provides that errored response comprises that write-protect is unusual, crosses the border, address deviation, internal error.
Press such scheme, if the space, ephemeral data memory block of storage card buffer area is full, storage card is changed to low level with data line DATO so.
Press such scheme, if data line DATO is a low level, storage card no longer receives data, and main frame also no longer sends data, is high level again up to data line DATO.
Press such scheme, after main frame sends ED or main frame provide when stopping to send order the data communication between End Host and the storage card.
Press such scheme, also comprise the CRC step, this step is carried out in the ephemeral data memory block of storage card buffer area, for the error of transmission of storage card check data.
Press such scheme, storage card sends the result of CRC to main frame by data line DATO, if error of transmission takes place, storage card sends main frame ' 101 ' to; If error of transmission does not take place, storage card sends main frame ' 010 ' to.
Press such scheme, if the CRC of the data of ephemeral data memory block is incorrect, then it can not be write in the flash memory of storage card, main frame need resend data.
Owing to adopted above-mentioned treatment step, the present invention compared with prior art has the following advantages:
1. after main frame sent write order, when receiving response, main frame sent data by data bus, can save the time of 48 clock period;
If storage card detect mistake (for example write-protect unusual, cross the border, address deviation, internal error etc.), will ignore all data transmission that arrive subsequently and remain on accepting state; If storage card just can not write data among the Flash (flash memory) of storage card after detecting CRC (CYCLIC REDUNDANCY CODE, the Cyclic Redundancy Code) verification correctly of any mistake and data, thereby guaranteed to write the validity of data;
3. if storage card detects the situation that check errors takes place in the ephemeral data memory block of storage card buffer area for mistake or data, perhaps two kinds of situations occur simultaneously, so, when main frame is retransmitted order or retransmission data at every turn, can accomplish to save 48 clock period, thereby improve writing speed.
Description of drawings
Fig. 1 is the structured flowchart of common multimedia card;
Fig. 2 is that monolithic data of the present invention write sequential chart;
Fig. 3 is that monolithic data of common multimedia card write sequential chart;
Fig. 4 is of the present invention and writes data flowchart.
Embodiment
Storage card of the present invention has multiple structure, be that a specific embodiment (but be not limited to specific instructions, command format, response, response format, state indication and register flag or the mmc card itself of mmc card, also can be that other order of taking multiplex mode that do not use or that used of MMC, command format, response, response format, state indication and register flag or SD card are realized) is further described specific implementation process of the present invention with multimedia card (MMC) below:
The concrete structure and the data transfer command of multimedia card (MMC) are at first described:
(1) basic structure of multimedia card (MMC)
The structure of multimedia card (MMC) as shown in Figure 1, wherein signal of communication comprises: CLK: in each cycle of clock signal, only transmit a Bit data on command line and data bus; CMD: this is a two-way instruction path that is used for storage card initialization and transfer instruction, and instruction sends to storage card from the main frame of storage card, and response sends to main frame from storage card; DATO-DAT7: bidirectional data path.
(2) bus protocol
Communication is based on protocol of messages between main frame and the multimedia card, and every message is represented by one of following signal: order: order is the signal of an operation beginning, sends on the storage card serial transmission on the CMD bus from main frame; Response: response is the signal that sends to main frame from storage card, as the response to the order that receives previously.Response serial transmission on the CMD bus; Data: data can be between main frame and storage card transmitted in both directions.Data are transmitted by data bus, and the data-bus width that is used for data transmission can be 1,4 or 8.
Wherein, the transformat of order is as shown in the table:
| The bit position | 47 | 46 | [45：40] | [39:8] | [7:1] | 0 |
| Width (bit) | 1 | 1 | 6 | 32 | 7 | 1 |
| Value | ‘0’ | ‘1’ | X | X | X | ‘1’ |
| Describe | Initial bits | Transmitted bit | Command index | Parameter | CRC7 | End bit |
An order is always by an initial bits (perseverance is ' 0 ') beginning, and the back is the bit that shows transmission direction (permanent is ' 1 '), and ensuing 6 bits are index of order, and its value may be interpreted as binary-coded digit (from 0 to 63).Some order needs parameter (for example address), uses 32 bits of encoded.All orders are all carried out verification by CRC, all finish with end bit (perseverance is ' 1 ').
The response of multimedia card has five types, and wherein clamping receives that the response format after the host side write command is as shown in the table:
| The bit position | 47 | 46 | [45:40] | [39:8] | [7:1] | 0 |
| Width (bit) | 1 | 1 | 6 | 32 | 7 | 1 |
| Value | ‘0’ | ‘0’ | x | x | x | ‘1’ |
| Describe | Initial bits | Transmitted bit | Command index | The card state | CRC7 | End bit |
All responses all transmit by the CMD bus, response is always begun by an initial bits (perseverance is ' 0 '), the back is the bit that shows transmission direction (permanent is ' 0 '), and ensuing 6 bits are index of order, and next 32 bits are used for representing the status information of card.All responses are all carried out verification by CRC, all finish with end bit (perseverance is ' 1 ').
Send at main frame in the processing of data, high position data at first transmits, and low data transmits at last.The start bit perseverance of data transmission is ' 0 ', the stop bit perseverance is ' 1 ', and data transmission has two types: piece transmission and flow transmission, in the piece transmission, verification is carried out by CRC in every blocks of data back, and the indication that CRC condition responsive and storage card " hurry " will send to main frame by data line DATO; And there is not CRC check in the flow transmission.
Design concept of the present invention: the write operation communication means that a kind of main frame and storage card are provided.After the write order transmission finished, when command line received response, data just can communicate by data bus.The present invention sets up an ephemeral data memory block at the buffer area of storage card, also here finishes about CRC (Cyclic Redundancy Code, the Cyclic Redundancy Code) verification of data.If storage card provide errored response (for example write-protect unusual, cross the border, address deviation, internal error etc.), must ignore all data transmission that arrive subsequently and remain on accepting state, main frame no longer sends data simultaneously; If storage card does not detect any mistake, but the CRC check mistake of data, and then the data of ephemeral data memory block can not write among the Flash (flash memory) of storage card; If storage card do not detect the CRC check of any mistake and data correct after, then the data with the ephemeral data memory block write among the Flash of storage card; If the ephemeral data memory block of storage card is full, then storage card data line DATO is set to low level, in case idle memory block is arranged, storage card will be re-set as high level with DATO; If main frame detects the low level signal of DATO, then no longer send data, be high level again up to detecting DATO.
According to above-mentioned design concept, the present invention realizes by following process:
Be illustrated in figure 2 as monolithic data of the present invention and write sequential chart, this sequential chart uses the abbreviated form in the following table:
| S | Initial bits (=' 0 ') |
| T | Transmit bit (main frame=' 1 ', card=' 0 ') |
| P | Draw (=' 1 ') on the one-period |
| E | End bit (=' 1 ') |
| Z | High impedance status |
| * | Repeat |
| L | Low level (=' 0 ') |
| CRC | Cyclic redundancy check bits |
Sequence shown in the figure is begun by the monolithic write command, and it has determined data to write the start address of storage card.When storage card after providing response on the CMD command line, main frame begins transmission and transmits data.And then the CRC check bit after the data, for storage card check error of transmission.Storage card sends the check results of CRC to main frame (can referring to ' the CRC state ' that mark on the DATO data line among Fig. 2) by data line DATO.If the generation error of transmission, storage card will return CRC state ' 101 ', if error of transmission does not take place, storage card will return CRC state ' 010 ' and begin and write data in Flash (flash memory), and promptly storage card enters programming state.If storage card does not have idle Data Receiving buffer area, storage card can be made as data line DATO low level and show this situation.
Monolithic data that are illustrated in figure 3 as the common multimedia card write sequential chart, comparison diagram 2 and Fig. 3 be both differences as can be seen: the time that data write among time ratio Fig. 3 that data write among Fig. 2 is carried the time of previous " card response " at least, therefore reduce the idle state of data bus, shortened the write time of storing card data.
The present invention includes stream and write with piece and write two kinds of writing modes, be described respectively below:
(1) piece writing mode
(1) after main frame sends write order, if detect command line (CMD) response (start bit that detects response is a low level signal) is arranged, then command line begins to receive response, main frame begins to send data to by data bus the ephemeral data memory block of storage card buffer area simultaneously, in this ephemeral data memory block, storage card carries out CRC check to data;
(2) if storage card does not provide errored response, for example: situations such as write-protect is unusual, cross the border, address deviation, internal error, and the CRC check of data is correct, then the data that receive is write storage card from the ephemeral data memory block of buffer area successively;
(3) if storage card provides errored response, for example: situations such as write-protect is unusual, cross the border, address deviation, internal error, then storage card must be ignored all data transmission that arrive subsequently and remain on accepting state; Simultaneously, main frame stops to send data;
(4) if the space, ephemeral data memory block of storage card buffer area is full, so data line DATO is changed to low level, storage card is ignored the data that arrive subsequently, and main frame also no longer sends data.
(2) stream writing mode
Stream writing mode and above-mentioned writing mode are basic identical, and unique difference is: stream writes under the pattern, does not need data are carried out CRC check.
Of the present invention writes data flowchart as shown in Figure 4, below is described in greater detail:
Main frame sends write order, waits for the response of storage card then; In case detect the start bit of response is low level signal (' 0 '), and then command line continues to receive response, if this moment, data line DATO was not a low level, main frame just sends data by data bus;
If storage card provides correct response, begin then to judge whether the CRC check of the data that the ephemeral data memory block of its buffer area receives is correct; If CRC check is correct, then the data of this ephemeral data memory block are write the Flash of storage card; If CRC check is incorrect, then need main frame to resend data; Provide when stopping to send order when data send to finish back or main frame, finish communication specifically; If storage card provides errored response, unusual as write-protect, cross the border, situations such as address deviation and internal error, then storage card must be ignored all data transmission that arrive subsequently and remain on accepting state; Simultaneously, main frame stops to send data;
If it is full that storage card writes the space, ephemeral data memory block of buffer area, so data line DATO is changed to low level, storage card no longer receives data, and main frame also no longer sends data.
Claims (10)
1, a kind of method that improves writing speed of memory card is at first set up an ephemeral data memory block at the buffer area of storage card, and this method is carried out following steps:
After main frame sent write order, if detect the response of storage card, then main frame sent data to the ephemeral data memory block of storage card buffer area by data bus, and simultaneously, main frame continues to receive response by command line;
If main frame receives correct response, then the data with the ephemeral data memory block write in the flash memory of storage card successively.
2, the method for raising writing speed of memory card as claimed in claim 1 is characterized in that, the described response that detects storage card is that to detect the start bit of this response be low level signal.
3, the method for raising writing speed of memory card as claimed in claim 1 or 2 is characterized in that, if storage card provides errored response, then storage card is ignored all data transmission that arrive subsequently and remained on accepting state; Simultaneously, main frame stops to send data.
4, the method for raising writing speed of memory card as claimed in claim 3 is characterized in that, described storage card provides that errored response comprises that write-protect is unusual, crosses the border, address deviation, internal error.
As the method for claim 1 or 2 or 4 described raising writing speed of memory card, it is characterized in that 5, if the space, ephemeral data memory block of storage card buffer area is full, storage card is changed to low level with data line DATO so.
6, the method for raising writing speed of memory card as claimed in claim 5 is characterized in that, if data line DATO is a low level, storage card no longer receives data, and main frame also no longer sends data, is high level again up to data line DATO.
7, the method for raising writing speed of memory card as claimed in claim 1 is characterized in that, after main frame sends ED or main frame provide when stopping to send order the data communication between End Host and the storage card.
8, as claim 1 or 2 or 4 or the method for 6 or 7 described raising writing speed of memory card, it is characterized in that, also comprise the CRC step, this step is carried out in the ephemeral data memory block of storage card buffer area, for the error of transmission of storage card check data.
9, the method for raising writing speed of memory card as claimed in claim 8 is characterized in that, storage card sends the result of CRC to main frame by data line DATO, if error of transmission takes place, storage card sends main frame ' 101 ' to; If error of transmission does not take place, storage card sends main frame ' 010 ' to.
10, the method for raising writing speed of memory card as claimed in claim 9 is characterized in that, if the CRC of the data of ephemeral data memory block is incorrect, then it can not be write in the flash memory of storage card, and main frame need resend data.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100875390A CN100468375C (en) | 2006-06-14 | 2006-06-14 | Method for raising writing speed of memory card |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100875390A CN100468375C (en) | 2006-06-14 | 2006-06-14 | Method for raising writing speed of memory card |
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| CN101089831A CN101089831A (en) | 2007-12-19 |
| CN100468375C true CN100468375C (en) | 2009-03-11 |
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| CNB2006100875390A Expired - Fee Related CN100468375C (en) | 2006-06-14 | 2006-06-14 | Method for raising writing speed of memory card |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102890653B (en) * | 2011-07-18 | 2016-05-18 | 群联电子股份有限公司 | Instruction executing method, Memory Controller and memorizer memory devices |
| CN103631740B (en) * | 2012-08-24 | 2018-02-13 | 上海华虹集成电路有限责任公司 | The circuit of SD card adaptation transmitter byte-aligned in the spi mode |
| CN103927131B (en) * | 2014-03-25 | 2017-02-15 | 四川和芯微电子股份有限公司 | Synchronous flash memory and USB (universal serial bus) flash disk starting method and control system thereof |
| CN105988832B (en) * | 2015-02-09 | 2019-05-24 | 深圳市硅格半导体有限公司 | Memory card data processing method and system |
| US9792975B1 (en) * | 2016-06-23 | 2017-10-17 | Mediatek Inc. | Dram and access and operating method thereof |
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2006
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Non-Patent Citations (2)
| Title |
|---|
| 提高闪速存储器写入速度的方法. 高怡祯.电子技术，第5期. 2003 |
| 提高闪速存储器写入速度的方法. 高怡祯.电子技术，第5期. 2003 * |
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