CN100466601C - 一种数据读写装置及其读写方法 - Google Patents

一种数据读写装置及其读写方法 Download PDF

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CN100466601C
CN100466601C CNB2005100665788A CN200510066578A CN100466601C CN 100466601 C CN100466601 C CN 100466601C CN B2005100665788 A CNB2005100665788 A CN B2005100665788A CN 200510066578 A CN200510066578 A CN 200510066578A CN 100466601 C CN100466601 C CN 100466601C
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write
data
read
memory
information
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CN1855880A (zh
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林郁
罗琨
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Abstract

本发明公开了一种数据读写装置，包括：写请求装置，用于产生写请求、写地址和写数据；读请求装置，用于产生读请求和读地址；两个存储器，用于存储数据；两个存储控制器，用于分别控制两个存储器的读写操作；仲裁器，用于根据仲裁规则、写请装置所产生的信息和读请求装置所产生的信息控制存储控制器对所述的存储器实施读操作或/和写操作。所述的两个存储器其容量、类型相同。本发明还公开了一种数据读写方法。根据本发明，可以保证任何时刻的读写申请均可以获得各自可用的存储器，保证读写操作立刻得到响应，数据输入和数据输出过程不被干扰和打断，从而提高了数据处理能力。

Description

一种数据读写装置及其读写方法
技术领域
本发明涉及一种数据处理技术，尤其涉及一种数据读写装置及其读写方法。
背景技术
随着信息通信技术的发展，对数据处理能力的要求也越来越高。在网络通信中，数据处理功能可由网络处理芯片来完成。
网络处理芯片可完成各端口间的报文交换，所述网络处理芯片包括两类，一类是处理变长度报文的芯片，如以太网交换芯片、L3(层3)交换芯片、路由器芯片，另一类是处理定长信元的芯片，如ATM交换芯片。当芯片处理定长信元或变长信元时，既需要大容量的存储能力以应付网络拥塞或流量不均匀情况下的报文暂存，又需要拥有高带宽能力以支持高速端口间的线速转发。这种存储能力和带宽能力取决于芯片上的数据读写装置和数据读写方法。
在现有技术中，网络处理芯片上的数据读写装置有多种，下面简述其特点。
1)芯片内集成的内置SRAM(静态随机访问存储器)。这种存储器方案的优点是操作简单且开销小，可用带宽较高。但这种方案会受到内置SRAM工艺频率上限的限制，另外，这种存储器成本高，使得其应用范围较小。
2)芯片内集成的内置DRAM(动态随机访问存储器)。相对于内置SRAM，内置DRAM可以提供较大容量的低成本存储能力。但这种存储器方案对芯片加工工艺要求较高，只有较少数芯片生产厂家可以提供，并且在片内容量仍然受限，因此片上集成DRAM方案的应用范围也比较小。另外DRAM操作复杂开销大，可用带宽较低，很难满足高带宽的要求。
3)外置SRAM。这种方案消除了片内存储容量成本问题，但外置SRAM仍然价格昂贵，限制了其应用范围。迫切需要实现存储带宽的最大化。
4)外置DRAM。外置DRAM有PSRAM(伪静态随机访问存储器)、SDRAM(同步随机访问存储器)、DDR SDRAM(双倍速率动态同步随机访问存储器)、DDR2 SDRAM(第2代双倍速率动态同步随机访问存储器)、RLDRAM(低延迟动态同步随机访问存储器)和FCRAM(快速周期随机访问存储器)等多个品种，其中DDR SDRAM、DDR2 SDRAM是目前各类芯片中的主流器件。所有外置DRAM都有操作复杂开销大、可用带宽低的问题，满足高带宽要求常常比较困难。
综上所述，上述任何一种存储系统都有进一步提高带宽的需求，特别是低成本、操作复杂开销大的DRAM存储系统，其提高带宽的需求更加迫切。
发明内容
针对现有技术的上述缺陷，本发明的目的是提供一种数据读写装置及其读写方法，其成本较低，带宽较高，并提高了数据读写能力。
本发明是通过下述技术方案实现的，本发明提供了一种数据读写装置，包括:
写请求装置，用于产生写请求、写地址和写数据；
读请求装置，用于产生读请求和读地址；
两个存储器，用于存储数据；
两个存储控制器，用于分别控制两个存储器的读写操作；
仲裁器，用于根据仲裁规则、写请求装置所产生的信息和读请求装置所产生的信息控制存储控制器对所述的存储器实施读操作或/和写操作，所述仲裁规则包括:
仅有写操作时，仲裁器控制存储控制器将数据写入任一存储器中；
仅有读操作时，仲裁器控制存储控制器从存储器中读出数据；
既有写操作也有读操作时，仲裁器控制存储控制器从存储器中读出数据，并将待写数据写入另一个存储器中。
所述的两个存储器其容量相同。
所述的两个存储器其类型相同。
所述的存储器为双倍速率动态同步随机访问存储器。
本发明还提供了一种数据读写方法，包括:
A、仲裁器获得写申请信息和/或读申请信息；
B、仲裁器根据仲裁规则，结合相应的存储控制器，以及地址信息相同的两个存储器，处理所述写申请信息和/或读申请信息，所述仲裁规则包括:
仅有写申请信息时，仲裁器根据写申请信息控制存储控制器将数据写入所述地址信息相同的两个存储器中的任一存储器中，并返回实际存储位置信息；
仅有读申请信息时，仲裁器根据读申请信息以及实际存储位置信息，控制存储控制器从所述地址信息相同的两个存储器中已写入相应数据的存储器中读出数据；
既有读申请信息也有写申请信息时，仲裁器根据读申请信息以及实际存储位置信息，控制存储控制器从所述地址信息相同的两个存储器中已写入相应数据的存储器中读出数据，并根据写申请信息将待写数据写入所述地址信息相同的两个存储器中的另一个存储器中，并返回实际存储位置信息。
所述的写申请信息包括待写数据和待写地址，所述的读申请信息包括地址信息和实际存储位置信息。
所述存储控制器读操作所使用的时钟周期与写操作所使用时钟周期相等。
当使用双倍速率动态同步随机访问存储器时，所述存储控制器读操作所使用的时钟周期和写操作所使用时钟周期同为11个时钟周期。
本发明的操作过程和仲裁算法非常简单可靠，并具有很强的数据读写能力，提高了带宽。
附图说明
图1示出了利用本发明的数据读写装置的实施例；
图2示出了本发明的写操作时序图；
图3示出了本发明的读操作时序图；
图4示出了本发明的使用CAS参数为2.5个时钟周期的DDR SDRAM的时序图；
图5示出了根据图1所示实施例的写数据操作流程图；
图6示出了根据图1所示实施例的读数据操作流程图。
具体实施方式
为了便于本领域一般技术人员理解和实现本发明，现结合附图描绘本发明的实施例。
本发明提供了一种数据读写装置，包括:写请求装置，用于产生写请求、写地址和写数据；读请求装置，用于产生读请求和读地址；两个存储器，用于存储数据；两个存储控制器，用于分别控制两个存储器的读写操作；仲裁器，用于根据仲裁规则、写请装置所产生的信息和读请求装置所产生的信息控制存储控制器对所述的存储器实施读操作或/和写操作。优选地，所述的两个存储器其容量、类型相同。
在以下实施例中，以目前主流且成本最低的片外DDR SDRAM存储器为例，结合实际的芯片，详细描述本发明的数据读写装置和数据读写方法。
如图1所示，利用本发明数据读写装置的芯片包括:至少一个RxFIFO(输入缓存器)、至少一个TxFIFO(输出缓存器)、输入端数据选通器、输出端数据选通器、业务处理及转发器、两个存储器、两个存储控制器和仲裁器。其中，至少一个RxFIFO(输入缓存器)、输入端数据选通器、业务处理及转发器构成写请求装置；至少一个TxFIFO(输出缓存器)、输出端数据选通器、业务处理及转发器构成读请求装置。
RxFIFO用于暂存从外部端口接收的数据，在每个输入端口上可配置一个RxFIFO。在本发明中，数据帧被保存到存储器时需要切分成固定长度，如128字节，如果网络交换芯片处理的是变长报文，如以太网报文，则RxFIFO在暂存数据的同时也完成数据帧的切分，例如，切分的大小可以每128字节为一块，不足128字节的报文或帧尾也被切分为一块，切分过程通过按数据块读出的方式实现。如果网络交换芯片处理的本来就是等长信元的报文，如ATM信元，也可不对数据块进行切分操作，直接按照该信元的长度进行读写操作。
TxFIFO用于暂存即将发送的数据，在每个发送端口上可配置一个TxFIFO。在本发明中，虽然数据帧是切分成固定长度的数据块保存在存储器中，并且输出过程也是以数据块为单位读取到TxFIFO中，但在TxFIFO中数据块是连续存放的，相当于完成了数据块的拼接，TxMAC(发送端媒体控制器)只需要依次连续发送即可，数据块的切分不会对发送产生任何影响。
一般来说，RxFIFO和TxFIFO需要通过物理层和数据链路层单元才能和外部网络进行数据接收和发送，RxFIFO和TxFIFO的深度需设计为:防止网络速度较高而芯片内部处理速度不足时发生溢出错误。
输入端数据选通器的功能是在输入端轮询控制器的控制下，将选中的RxFIFO的数据读出并发送到写数据总线上。输入端数据选通器被设计为一个多路选一开关。
输出端数据选通器的功能是在输出端轮询控制器单元的控制下，将读数据总线接入到选中的TxFIFO的数据输入端，以便完成TxFIFO的写入操作。
所述业务处理及转发器向仲裁器提出写申请信息和读申请信息。所述业务处理及转发器包括输入端轮询控制、业务处理器、输出队列调度器、输出端轮询控制器。
输入端轮询控制器的功能是轮询所有RxFIFO中数据接收的状态，并为每个新数据帧向存储管理器申请可用的存储器空间块，在每块为定长的情况下，所述存储器空间块可用存储器的起始地址来表示，申请到可用的存储器空间后，输入端轮询控制器向仲裁器发出写操作申请，并同时控制输入端数据选通器将RxFIFO的数据送到写数据总线上，由仲裁器完成数据写入操作，每次写操作完成一个数据块，如128字节。写操作执行完毕，仲裁器会返回一个实际存储位置信息，所述实际存储位置信息为存储器的编号。该实际存储位置信息将在报文读出时使用。经过一次或多次数据块写入操作后可完成一个完整数据报文的写入，输入端轮询控制器将该数据帧的存储器地址信息和实际存储位置信息组合为数据帧控制信息，发送给业务处理器进行业务处理。
业务处理器用于完成数据的业务处理。
输出队列调度器的功能是为输出端口提供多个输出队列并提供队列间的优先级调度服务。
业务处理器和输出队列调度器是数据处理的业务单元，经过这两部分处理后，可以获得每个数据帧的输出端口控制信息，该信息与输入端轮询控制器提供的数据帧的存储器地址、实际存储位置信息等构成了待发发送数据帧的控制信息，用于报文的发送。另外，在报文进入输出缓存器时，可能因拥塞等原因需要丢弃数据帧，输出队列调度器需要用丢弃的报文的控制信息向存储管理器提出存储释放申请，以便该块存储可用于新数据帧的存放。
输出端轮询控制器的功能是轮询TxFIFO的状态，当发现TxFIFO中存在至少有一个空闲的存储块时，则向输出队列调度器申请端口的待发数据帧信息，以便获得输出报文控制块信息，然后，根据其中的存储器地址及实际存储位置信息向仲裁器提出读数据申请，并控制输出端数据选通器将读数据总线上的数据读出并写入到TxFIFO中，每次操作1个数据块，如128字节。如果待发送数据帧长度超过1个数据块大小，则需要多次轮询该端口并进行多次操作。当一个数据帧的所有数据块都已读出完毕，则向存储管理器发送释放缓存申请，以使该缓存可用于新数据帧的存放。
存储管理器的功能是维护报文缓存，也就是维护存储器的使用。报文维护通过“存储器使用状况表”的方式来操作:将所有可用的存储器按可分配的最小粒度进行划分，每个粒度单元分配一个地址标识并配置是否使用的标记。当输入端轮询控制器提出新数据帧存储空间申请时，存储管理器返回一个未使用的缓存块的地址标识并将有关地址控制信息标志为“已用”，当输出队列调度器和输出端轮询控制器返回释放的地址标识时，存储管理器将有关地址的控制信息修改为“未用”以便再次分配。外部存储管理器虽然不直接和存储器打交道，但所有的存储器空间的分配和使用都由存储管理器来控制。
以下阐述本发明的核心装置和方法。
两个存储器分别称为存储器A组、存储器B组，用于存储数据。
存储器A组和存储器B组是两套配置完全相同的DDR SDRAM器件组，配置相同指的是位宽、速度、容量都相同，如2组完全相同的64bit@133MHz DDRSDRAM器件。为获得超过标准位宽(8bit、16bit、32bit)的存储器位宽，可以使用多个标准位宽的DDR SDRAM并联配置，并联配置需将DDR SDRAM的指令总线和数据总线并联，以便在控制器侧统一控制。如64bit位宽可以用4个16bit位宽DDR SDRAM或2个32bit位宽DDR SDRAM并联实现。
两个外部存储控制器分别称为存储器A组控制器、存储器B组控制器。其中存储器A组控制器控制存储器A组进行读写，存储器B组控制器控制存储器B组进行读写。存储器A组控制器和存储器B组控制器是两套功能完全相同的DDR SDRAM读写控制器，但在操作上完全独立，即每个控制器都可以各自完成读写操作，互相之间没有任何影响和牵制，两个控制器间的协调由仲裁器进行控制。DDR SDRAM控制器完成标准的DDR SDRAM读写操作，包括读写操作前的Bank(块)激活、Bank读写指令发送、Bank预充电、Bank刷新等。
仲裁器可同时或单独接收来自输入端的写数据申请和来自输出端的读数据申请。当同时接收到来自输入端的写数据申请和来自输出端的读数据申请时，可控制一个DDR SDRAM控制器完成写数据总线上的数据写入存储器的操作，控制另一个DDR SDRAM控制器完成存储器读操作并将读出数据放入读数据总线上。当仅接收来自输入端的写数据申请时，可控制任一个DDRSDRAM控制器完成写数据总线上的数据写入存储器的操作，当仅接收来自输出端的读数据申请时，可控制与实际存储位置信息相对应的DDR SDRAM控制器完成存储器读操作并将读出数据放入读数据总线上。
根据以上所述，对本发明来说，本发明的特点如下。
1、本发明不仅可支持定长数据块的外部存储，也支持变长数据块的外部存储。如果待处理的是变长报文，则在输入缓存器完成定长切分，在输出缓存器完成拼接操作，如果待处理的是定长报文，则可将读写操作的长度设置为与定长报文长度相对应的长度，从而不需要切分。
2、通过本发明的数据处理过程后，可将数据读写装置的多个外部网络端口，复用为一路写存储器操作序列和一路读存储器操作序列，序列中的每个操作完成一个定长数据块的读或写操作。
3、使用两路完全独立的DDR SDRAM支持数据的读存储器序列和写存储器序列的操作申请，两路DDR SDRAM有完全相同的存储空间和地址空间分配。
4、两路DDR SDRAM的地址统一维护，相同地址单元同时分配、使用和回收，既每个待存储数据都分得2倍容量的存储器空间，但每个待存储数据都只写入一路DDR SDRAM中，存储器的利用率最高为50％，写入哪路DDRSDRAM通过仲裁规则来决定。
地址统一维护是指两路DDR SDRAM中相同的地址单元在存储管理器中被当作是一个管理单元，仅分配一个地址标识符，存储管理器并不知道有两路完全相同的DDR SDRAM的存在，因而每次分配一个地址标识符给新数据帧时，实际上是将存储器A、B组中的地址单元同时进行了分配，相当于每个新数据帧获得了2倍的存储空间。数据帧在使用该存储空间时，只能使用其中的50％，具体使用哪些部分由仲裁规则来控制。当进行地址回收时，也同样使用这个单一的地址标识符，相当于A、B组中的地址单元同时进行回收。
所述仲裁规则是指:如果同时有读请求和写请求，则将读请求分配到其需要的那一路DDR SDRAM中，将写请求分配到另一路DDR SDRAM中；如果仅有读请求，则将读请求分配到其需要的那一路DDR SDRAM中；如果仅有写请求，可将其分配到任一路DDR SDRAM中。对写请求操作响应完毕，都要将数据实际存储位置信息返回给输入端轮询控制器，以便在输出侧读请求时使用，所述实际存储位置信息是指DDR SDRAM的编号，表示数据被放在哪一组DDR SDRAM中的信息。
为了保证本发明的仲裁规则得以实现，还要构造DDR SDRAM的访问时序，以便在读、写操作均充分利用DDR SDRAM的带宽情况下，使读操作指令周期和写操作指令周期等长，从而构造出流水线方式的DDR SDRAM访问操作访问方式，确保读写操作的同步。
下面详细描述DDR SDRAM的操作时序。
本发明的一个实施例是每次读写128字节的数据块，在2组DDR SDRAM中，每一组位宽为64bit，每个数据块均使用了每个DDR SDRAM的全部4个Bank。
如图2所示，128字节写入64bit DDR SDRAM的4个Bank设计为使用11个时钟周期。在图2中，clk是DDR SDRAM的主时钟，cmd是发送给DDR SDRAM的命令，ba是发送给DDR SDRAM的Bank号，dq[63:0]是发送给DDR SDRAM的数据。
发送给DDR SDRAM的指令包括NOP空操作、N空操作、A激活Bank操作、W写Bank操作，涉及Bank操作时的Bank号在指令发送的同时提供，Bank号为0、1、2、3，对应DDR SDRAM的4个Bank。数据线dq标识为0、1、2、3时表示发送给Bank号0、1、2、3的数据。
写操作使用11个时钟周期是从cmd上衡量的，根据本发明，无论本次写操作前是读操作还是写操作，本次写操作启动后，都需要消耗11个周期，才能发起下一个读或写操作周期。如果写入的数据不足128字节，则11个时钟周期不会全部用完，但为保持流水线周期相等，剩余的时钟周期保持空闲。
根据DDR SDRAM器件速度的不同，如图3所示，从64bit DDR SDRAM的4个Bank中读出128字节会消耗10到11个时钟周期，在图3中，clk是DDRSDRAM的主时钟，cmd是发送给DDR SDRAM的命令，ba是发送给DDR SDRAM的Bank号，dq[63:0]是发送给DDR SDRAM的数据。
发送给DDR SDRAM的指令包括NOP空操作、N空操作、A激活Bank操作、R读Bank操作，涉及Bank操作时的Bank号在指令发送的同时提供，Bank号为0、1、2、3，对应DDR SDRAM的4个Bank。数据线dq标识为0、1、2、3时表示DDR SDRAM返回的Bank号0、1、2、3的数据。
以上读操作过程消耗了10个时钟周期，是因为使用了CAS(中文？)参数为2个时钟周期的DDR SDRAM，也就是dq数据比R操作指令延迟2个时钟周期响应。与写操作一样，消耗10个时钟周期是从cmd上衡量的，无论本次读操作前是读操作还是写操作，本次写操作启动后，都需要消耗10个周期，才能发起下一个读或写操作周期。
如图4所示，如果是CAS参数为2.5个时钟周期的DDR SDRAM器件，则需要消耗11个时钟周期，在图4中，clk是DDR SDRAM的主时钟，cmd是发送给DDR SDRAM的命令，ba是发送给DDR SDRAM的Bank号，dq[63:0]是发送给DDRSDRAM的数据。
发送给DDR SDRAM的指令包括NOP空操作、N空操作、A激活Bank操作、R读Bank操作，涉及Bank操作时的Bank号在指令发送的同时提供，Bank号为0、1、2、3，对应DDR SDRAM的4个Bank。数据线dq标识为0、1、2、3时表示DDR SDRAM返回的Bank号0、1、2、3的数据。
使用CAS参数为2.5个时钟周期的DDR SDRAM器件，则dq数据比R操作指令延迟2.5个时钟周期出现，因而整个读指令共消耗11个时钟周期，这11个时钟周期是从cmd上衡量的，无论本次读操作前是读操作还是写操作，本次写操作启动后，都需要消耗11个周期，才能发起下一个读或写操作周期。
类似的，如果使用CAS参数为3个时钟周期的DDR SDRAM，仍然可以获得11个时钟的读操作周期。
为了构造DDR SDRAM访问流水线，必须使写操作所使用的时钟周期与读操作所使用的时钟周期相等，由于写周期为11个时钟周期，因此，可以使用读周期小于或等于11个时钟周期的DDR SDRAM，但要使读周期都统一为11个时钟周期，即与写周期相同，以便DDR SDRAM可以用11个时钟周期的流水线进行操作。如果原为10个时钟周期的读操作，需要在流水线操作时空1个时钟周期。如果读出的数据不足128字节，则11个时钟周期不会全部用完，但为保持流水线周期相等，剩余的时钟周期保持空闲。
仲裁器接收来自输入端和输出端的读写请求，进行操作仲裁和DDRSDRAM分配后，按11个时钟周期流水线的方式启动DDR SDRAM，使两条流水线周期完全同步，任何一条流水线没有指令则该级流水线空转，待下一个流水线周期到来后再启动下一个操作周期。
需要注意的是，以上时序定义是指DDR SDRAM控制器和DDR SDRAM器件间的时序，为了达到该接口上的流水线时序及带宽，仲裁器及DDR SDRAM控制器需要考虑各自的电路处理延迟，如读写申请的到来时间、仲裁操作时间、启动命令时间等。具体的延迟及控制时序在电路设计中考虑，不属本发明的关键内容，本文不再讨论。
上面阐述的是一种高带宽利用率的DDR SDRAM操作流水线设计，带宽利用率达到了8/11。如果需要的带宽不高，也可以考虑将流水线周期增加到12或13个时钟周期，这样可以使用性能指标稍低的DDR SDRAM器件以降低成本。另外，也可以变更写入到每个Bank中的数据量，如从当前的每个Bank写4组数据增加到8组数据等，从而整个流水线延长到19个周期但利用率提高到16/19。仅仅对流水线周期数及数据读写长度，不对本发明构成实质性的改进。
以上对本发明的数据读写装置进行了详细讨论，下面描述本发明的数据读写方法。
本发明的数据读写方法的总体思想是:仲裁器获得写申请信息和/或读申请信息；仲裁器根据仲裁规则处理读申请信息和/或读申请信息。所述的写申请信息包括待写数据和待写地址，所述的读申请信息包括地址信息和实际存储位置信息。所述存储控制器读操作所使用的时钟周期与写操作所使用时钟周期相等。
图5示出了根据图1所示实施例的写数据操作流程图。如图5所示，下面描述写操作流程。
在步骤51中，输入端轮询控制器轮询所有输入缓存器的状态；在步骤52中，输入端轮询控制器若发现输入缓存器中有新接收的数据，则执行步骤53，否则执行步骤51，继续轮询输入缓存器的状态。
在步骤53、输入端轮询控制器为所接收的数据向存储管理器申请可用的存储器的存储空间。
在步骤54中，输入端轮询控制器控制输入端数据选通器将输入缓存器中的数据放在写数据总线上。
在步骤55中，仲裁器根据仲裁规则控制存储控制器将写数据总线上的数据写入存储器的可用空间中。
所述仲裁规则是指:当仲裁器发现:仅有写操作申请时，仲裁器根据写申请信息控制存储控制器将数据写入任一存储器中；仅有读操作申请时，仲裁器根据读申请信息控制存储控制器从存储器中读出数据；既有写操作申请也有写操作申请时，仲裁器根据读申请信息控制存储控制器从存储器中读出数据，并根据写申请信息控制存储控制器将数据写入另一存储器中。
在步骤56中，仲裁器将实际存储位置信息返回输入端轮询控制器。
在步骤57中，输入端轮询控制器向业务处理器发送实际存储位置信息。
图6示出了根据图1所示实施例的读数据操作流程图。如图6所示，下面详细描述读数据的流程。
在步骤61中，输出端轮询控制器轮询所有输出缓存器的状态。
在步骤62中，输出端轮询控制器若发现输出缓存器中存在空闲的存储空间块，则执行步骤63，否则，执行步骤61，继续轮询输出缓存器的状态。
在步骤63中，输出端轮询控制器向输出队列调度器申请输出缓存器的待发数据帧信息。
在步骤64中，输出端轮询控制器根据待发数据帧信息获得数据的外部存储地址和实际存储位置信息，并将外部存储地址和实际存储位置信息发给仲裁器。
在步骤65中，仲裁器根据上述仲裁规则、外部存储地址和实际存储位置信息控制存储控制器读出数据，并将数据放在读数据总线上。
在步骤66中，输出端轮询控制器控制输出端数据选通器将读数据总线上的数据读出并写入到输出缓存器中。
在步骤67中，输出端轮询控制器向存储管理器发送释放存储空间申请。
本发明使用2路并行DDR SDRAM，可使总位宽达到与1路DDR SDRAM位宽相同的情况下，每路的位宽只有总位宽的一半，因此小报文的带宽利用率很高，保证了小报文时的带宽性能要求，从而降低了系统设计难度。
另外，2路DDR SDRAM的操作过程和仲裁算法简单可靠。
通过本发明的仲裁过程，可以保证任何时刻的读写申请均可以获得各自可用的DDR SDRAM，保证读写操作立刻得到响应，数据输入和数据输出过程不被干扰和打断。
由于输入过程和输出过程始终可以有各自可用的DDR SDRAM资源，逻辑上相当于为输入和输出过程配置了独立的DDR SDRAM。这样，在计算DDRSDRAM提供的带宽能否满足各自过程带宽的需要时，完全解除了可用资源的不确定性，简化了计算过程，并且计算结果可完全信赖。
还应注意到，输入、输出端数据选通器与仲裁器之间及输入、输出端轮询控制器与仲裁器之间可以通过FIFO的方式连接，这样会使得仲裁器与业务处理及转发器之间的配合关系更加灵活，控制时序更加容易设计。用FIFO替代直接连接关系，并不改变存储控制系统的核心设计结构，不对本发明构成实质上的改进。
另外，输入、输出端数据选通器与仲裁器之间也可以复用到几个FIFO，由仲裁器通过对多个FIFO的轮询来获得读写数据，从而增强业务和数据读写装置的设计灵活性。用多个FIFO替代直接连接关系或单个FIF0连接，并不改变2路DDR SDRAM的核心设计结构，不对本发明构成实质上的改进。
本发明以DDR SDRAM为例对本发明的基本思想进行了详细描述，本发明可应用所有类型的存储器，包括内置SRAM、内置PSRAM、内置DRAM、外置SRAM、外置PSRAM、外置SDRAM、外置DDR SDRAM、外置DDR2 SDRAM、外置RLDRAM(低延迟动态同步随机访问存储器)、外置FCRAM(快速周期随机访问存储器)等，以及未来可能出现的任何类型存储器，更换存储器类型只需要调整流水线的操作时序即可，不对本发明构成实质性的改进。
虽然通过实施例描绘了本发明，但本领域普通技术人员知道，在不脱离本发明的精神和实质的情况下，就可使本发明有许多变形和变化，本发明的范围由所附的权利要求来限定。

Claims (8)

1.一种数据读写装置，包括：
写请求装置，用于产生写请求、写地址和写数据；
读请求装置，用于产生读请求和读地址；
其特征在于，所述数据读写装置还包括：
两个存储器，用于存储数据；
两个存储控制器，用于分别控制两个存储器的读写操作；
仲裁器，用于根据仲裁规则、写请求装置所产生的信息和读请求装置所产生的信息控制存储控制器对所述的存储器实施读操作或/和写操作，所述仲裁规则包括：
仅有写操作时，仲裁器控制存储控制器将数据写入任一存储器中；
仅有读操作时，仲裁器控制存储控制器从存储器中读出数据；
既有写操作也有读操作时，仲裁器控制存储控制器从存储器中读出数据，并将待写数据写入另一个存储器中。
2.根据权利要求1所述的数据读写装置，其特征在于，所述的两个存储器其容量相同。
3.根据权利要求1所述的数据读写装置，其特征在于，所述的两个存储器其类型相同。
4.根据权利要求1、2或3所述的数据读写装置，其特征在于，所述的存储器为双倍速率动态同步随机访问存储器。
5.一种数据读写方法，其特征在于，包括：
A、仲裁器获得写申请信息和/或读申请信息；
B、仲裁器根据仲裁规则，结合相应的存储控制器，以及地址信息相同的两个存储器，处理所述写申请信息和/或读申请信息，所述仲裁规则包括:仅有写申请信息时，仲裁器根据写申请信息控制存储控制器将数据写入所述地址信息相同的两个存储器中的任一存储器中，并返回实际存储位置信息；
仅有读申请信息时，仲裁器根据读申请信息以及实际存储位置信息，控制存储控制器从所述地址信息相同的两个存储器中已写入相应数据的存储器中读出数据；
既有读申请信息也有写申请信息时，仲裁器根据读申请信息以及实际存储位置信息，控制存储控制器从所述地址信息相同的两个存储器中已写入相应数据的存储器中读出数据，并根据写申请信息将待写数据写入所述地址信息相同的两个存储器中的另一个存储器中，并返回实际存储位置信息。
6.根据权利要求5所述的数据读写方法，其特征在于，所述的写申请信息包括待写数据和待写地址，所述的读申请信息包括地址信息和实际存储位置信息。
7.根据权利要求5所述的数据读写方法，其特征在于，所述存储控制器读操作所使用的时钟周期与写操作所使用时钟周期相等。
8.根据权利要求7所述的数据读写方法，其特征在于，当使用双倍速率动态同步随机访问存储器时，所述存储控制器读操作所使用的时钟周期和写操作所使用时钟周期同为11个时钟周期。
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