CN100466475C

CN100466475C - Automatic regulating method and circuit for phase locking loop frequency synthesizer switch capacitor

Info

Publication number: CN100466475C
Application number: CNB2006100272035A
Authority: CN
Inventors: 张海清
Original assignee: Individual
Current assignee: Individual
Priority date: 2006-06-01
Filing date: 2006-06-01
Publication date: 2009-03-04
Anticipated expiration: 2026-06-01
Also published as: CN1859008A

Abstract

This invention relates to an automatic adjusting method and a realization circuit for the switch of a phase-locking loop frequency synthesizer switch capacitance, which changes the LC resonance structure of the voltage-controlled oscillator in a phase-locking loop frequency synthesizer to a structure of a variable capacitor and switch capacitor array and adds a switch capacitance control module for testing the voltage variance of the voltage-controlled oscillator to control the load of the switch capacitor and regulate the central frequency of the oscillator to get even better performance of synthesizers, said control module is composed of two hysteresis comparators and a FSM for regulating the switch, the input of the comparator is control voltage having high and low threshold voltages, the FSM controls the switch of the switch capacitor array.

Description

The Automatic adjustment method of phase locking loop frequency synthesizer switch capacitor and circuit

Technical field

The invention belongs to technical field of radio frequency integrated circuits, be specifically related to a kind of Automatic adjustment method of phase locking loop frequency synthesizer switch capacitor and realize circuit.

Background technology

The huge market potential of portable wireless communication product has greatly promoted the development of radio frequency integrated circuit product.Various radio communication agreements are also arisen at the historic moment, and they are operated in the frequency range of hundreds of M to several G respectively, and its code requirement separately also is not quite similar.But no matter adopt the twireless radio-frequency communication product of the sort of standard, their all must adopt frequency synthesis technique to obtain local frequency (local oscillator, LO) or directly modulate emission.(frequencysynthesizer, FS) performance to whole radio frequency receiving-transmitting device has decisive influence to the frequency synthesizer of realization this purpose.The radio frequency receiving-transmitting device performance that obtains requires frequency synthesizer to have fast frequency switch speed, low phase noise, accurate setpoint frequency.The design of frequency synthesizer is a technical barrier of radio frequency receiving-transmitting device design always.

Along with the develop rapidly of CMOS integrated technique technology, for low cost, low-power consumption, considerations such as small size, the CMOS monolithic of radio frequency receiving-transmitting device system is integrated to have become a kind of inexorable trend, and this has also proposed more stern challenge to the design of frequency synthesizer.Because the intrinsic characteristic of CMOS technology, the reference frequency output of VCO can produce bigger drift.Simultaneously, integrated high-power output module can cause that the output frequency of frequency synthesizer drifts about.In order to overcome this uncertain frequency drift, the VCO in the frequency synthesizer design needs bigger frequency gain to satisfy the needs of big frequency-tuning range.In addition, high performance analog circuit (as phase-locked loop frequency synthesizer etc.) is integrated in the problem that has mutual interference mutually on the same substrate with digital circuit.Integrated digital circuit can be incorporated into switching noise in the frequency synthesizer by substrate coupling, and phase noise is worsened, and produces various spuious (spur).The frequency gain of their degree of coupling and VCO is proportional.It is big more to gain, and coupled noise is big more.Therefore between the frequency gain of VCO and phase noise, there is a compromise in the design of phase-locked loop frequency synthesizer.A solution eliminating this compromise restriction is to have introduced switched capacitor technique in the realization of VCO, and adopts various corresponding switching capacities to select and the loop adjustment technology in phase-locked loop frequency synthesizer.As A.D.Berny, A.M.Niknejad, and R.G.Meyer, " A wide-band low phase-noise CMOS VCO; " in Proc.IEEECustom Integrated Circuits Conf., San Jose, CA, Sep.2003, pp.555-558.J.Kaiser and T.H.Lin, " A 900MHz 2.5mA CMOS frequency synthesizer with an automatic SC tuning loop; " IEEE J.Solid-State Circuits, vol.36, no.3, pp.424-430, Mar.2001.

But the switching capacity that adopts in the above-mentioned document is selected and the loop adjustment technology is a double loop structure, and elder generation's cor-rection loop during circuit working switches to the work loop again after the cor-rection loop locking.This method has the following disadvantages: 1) need two loops of design, increased the hardware consumption of circuit greatly; 2) the running parameter difference of two loops can't guarantee two loop optimal design simultaneously, and loop is easy to generate the transient state fluctuation when switching, thereby has prolonged locking time; 3) in case circuit has produced bigger fluctuation because of mains voltage variations etc., loop must switch to cor-rection loop from the work loop and proofread and correct again, thereby influences system communication quality.

Summary of the invention

In order to overcome the problem that exists in the above-mentioned switching capacity double loop switching, the present invention proposes a kind of improved implementation, comprise the phase locking loop frequency synthesizer switch capacitor Automatic adjustment method and realize circuit.

The Automatic adjustment method of the phase locking loop frequency synthesizer switch capacitor that the present invention proposes, be in common phase-locked loop frequency synthesizer, change original voltage controlled oscillator (VCO) into switching capacity voltage controlled oscillator (SC VCO), the LC resonance structure that is about to voltage controlled oscillator changes variable capacitance and Kind of Switched Capacitor Array into, set up a switching capacity auto-adjusting circuit simultaneously, this circuit is by detecting the change in voltage of voltage controlled oscillator, control shape capacitive load, thereby adjust the centre frequency of voltage controlled oscillator, to obtain better frequency synthesizer performance.

The realization circuit of the Automatic adjustment method of the phase locking loop frequency synthesizer switch capacitor that the present invention proposes is a switching capacity auto-adjusting circuit.This switching capacity auto-adjusting circuit as shown in Figure 2, the state machine 23 that it is taken back stagnant comparator 20 by two and is used for by-pass cock electric capacity connects to form through circuit, wherein, state machine 23 has the clock input, voltage Vc is controlled in being input as of two comparators 20, and be respectively equipped with high threshold voltage Vref_H and low threshold voltage Vref_L, their output M_U and M_D be or the input of door 21, clock signal clk with or the output of door 21 as two inputs of NAND gate 22.Take back stagnant comparator 20 for two and be used for detecting control voltage Vc:

When control voltage Vc is between high and low threshold voltage Vref_H, the Vref_L, two comparators 20 are output as low level, thereby or door 21 output also be low, and the clock input CLK of shielding NAND gate 22, the output of NAND gate 22 keep high level, and state machine 23 no clocks are imported; When controlling voltage Vc greater than high threshold level Vref_H, high threshold detection comparator output M_U is high, or door 21 also is output as height, thereby the input of the clock of NAND gate 22 effectively, the output clock is to

state machine

23, and 23 work of attitude machine are according to input M_U, control increases the switching capacity load of VCO, and the centre frequency of VCO is reduced; When controlling voltage Vc less than threshold level Vref_L, high threshold detection comparator output M_D is high, same or door 21 is output as height, and the input of the clock of NAND gate 22 effectively, the clock that outputs to state machine 23 is effective, state machine 23 raises the centre frequency of VCO according to the switching capacity load of input M_D control minimizing VCO.

Circuit block diagram that taking back stagnant comparator 20 among Fig. 2 as shown in Figure 3.This circuit comprises that a difference input of being made up of NMOS pipe nm1 and nm2 is right, and the grid of PMOS pipe pm3 is connected with drain electrode, and manages nm1 with NMOS and drain and link to each other, and is its load; The grid of PMOS pipe pm4 is connected with drain electrode, and links to each other with NMOS pipe nm2 drain electrode, is its load.The grid of PMOS pipe pm1 and the drain electrode of pm4 are joined, and receive the drain electrode of nm2; The grid of PMOS pipe pm2 and the drain electrode of pm3 are joined, and receive the drain electrode of nm1.Pm1 and pm2 have formed cross coupling structure like this, produce returning of comparator with PMOS pipe pm3 and pm4 and stagnate, and the size of returning stagnant voltage is by PMOS pipe pm2 and pm3, or the size of pm1 and pm4 determines, and relevant with the deflection current of differential pair.The output of the nm1 of differential pair is connected to the grid of PMOS pipe pm5, and the output of the nm2 of differential pair is connected to the grid of PMOS pipe pm6.The grid of NMOS pipe nm3 links to each other with drain electrode, and is connected with the drain electrode of PMOS pipe pm5.The grid of NMOS pipe nm4 is connected to the grid of nm3, and its drain electrode then links to each other with the drain electrode of PMOS pipe pm6.The drain electrode of PMOS pipe pm6 links to each other with the input of reverser 31.Like this, NMOS pipe nm3 and nm4, PMOS pipe pm5 and pm6 convert the output of differential pair tube nm1 and nm2 to single-ended output together, and this output is converted to high-low level through reverser 31.

The circuit block diagram of the state machine 23 among Fig. 2 is seen shown in Figure 4.It is by 4 registers 41 of the parallel connection that is used to store internal state, upwards computerlogic module (up_logic) 42 and computer logic module (down_logic) 43 and select logic module 44 to constitute through circuit downwards.Register 41 data input D is for selecting the output of logic module 44.Its output is respectively the direction signal QB of Q and Q.Q and QB are simultaneously as upwards computerlogic module 42 and the input of computer logic module 43 downwards.Upwards computerlogic module 42 and output two groups of inputs of conduct selection logic module 44 respectively of computer logic module 43 downwards.Selecting the selection control signal of logic module 44 is M_U.When M_U was high level, select logic module 44 will select to make progress signal that computerlogic module 42 sends here was as output; Otherwise, when M_U is low level, select logic module 44 will select signal that downward computerlogic module 43 sends here as output.

The present invention by the real-time switching of control module control switch electric capacity, with the centre frequency of adjusting voltage controlled oscillator, thereby has obtained good frequency synthesizer performance by the variation of sense switch electric capacity voltage controlled oscillator VCO control voltage.

Description of drawings

Fig. 1 is the self-regulating phase-locked loop frequency synthesizer structural diagrams of switching capacity.

Fig. 2 is a switching capacity auto-adjusting circuit structural diagrams in the frequency synthesizer shown in Figure 1.

Fig. 3 returns stagnant comparator configuration diagram in the switching capacity auto-adjusting circuit shown in Figure 2.

Fig. 4 is a switching capacity adjustment state machine structural diagrams in the switching capacity auto-adjusting circuit shown in Figure 2.

Fig. 5 is a switching capacity adjustment state machine state exchange diagram.

Number in the figure: 10 is phase frequency detector, and 11 is charge pump and electric current bandpass filter, and 12 is the switching capacity voltage controlled oscillator, 13 is frequency divider, 14 is the switching capacity auto-adjusting circuit, and 20 are back stagnant comparator, and 21 are or door, 22 is NAND gate, 23 is state machine, and 41 is register, and 42 are the computerlogic module that makes progress, 43 is downward computerlogic module, and 44 for selecting logic module.

Embodiment

Fig. 1 is for having adopted the self-regulating phase-locked loop frequency synthesizer structural diagrams of switching capacity of the present invention.The present invention is applied in the switching capacity auto-adjusting circuit 14.The automatic regulating frequency synthesizer of switching capacity is by phase frequency detector (PFD) 10, charge pump and low pass filter (CP﹠amp; LPF) 11, switching capacity voltage controlled oscillator (SC VCO) 12, frequency divider (/N) 13 and switching capacity auto-adjusting circuit (switch control) 14 form.Common phase-locked loop frequency synthesizer does not have switching capacity auto-adjusting circuit 14, and voltage controlled oscillator is generally the LC resonance structure, and the adjusting of frequency is realized by a variable capacitance.In switching capacity voltage controlled oscillator 12, frequency adjustment is to be finished by variable capacitance and switched capacitor array.Under certain control voltage Vc, frequency f out of voltage controlled oscillator 12 outputs, this output frequency is behind frequency divider 13 frequency divisions, be output as fdiv, it and reference frequency fref are input to phase frequency detector 10 relatively, produce frequency/phase errors signal phe, behind this error signal process charge pump and the low pass filter 11, obtain new control voltage Vc, be used to revise the output frequency of voltage controlled oscillator 12.Whole loop is a feedback loop.When loop reach stable after, output frequency and reference frequency satisfy and concern: output frequency accurately equals the product of reference frequency and distributor frequency dividing ratio N.This frequency also is the target lock-on frequency that circuit sets.

Locking frequency is bigger if the output frequency of voltage controlled oscillator 12 departs from objectives, and control voltage Vc will constantly rise or descend, up to exceeding its adjustable extent.At this moment, in common phase-locked loop frequency synthesizer, loop can't reach lock-out state.And in the automatic regulating frequency synthesizer of switching capacity, switch control module 14 will increase or reduce the number of switching capacity according to the state of control voltage Vc, regulate the centre frequency of voltage controlled oscillator 12, thereby make loop get back to lock-in range.

Fig. 2 is the structured flowchart of switching capacity auto-adjusting circuit 14.Take back stagnant comparator 20 for 2 and be used for detecting control voltage Vc.When control voltage Vc is between high and low threshold voltage Vref_H, the Vref_L, to return stagnant comparator 20 and be output as low level, thereby make the input clock of switching capacity adjustment state machine 23 invalid, the output of state machine does not change.When controlling voltage Vc greater than high threshold level Vref_H, high threshold detection comparator output M_U is high, or door 21 also is output as height.Thereby the input of the clock of NAND gate 22 effectively, and the output clock is to state machine 23.State machine 23 work, according to input M_U, control increases the switching capacity load of VCO, and the centre frequency of VCO is reduced; When controlling voltage Vc less than threshold level Vref_L, high threshold detection comparator output M_D is high, and same or door 21 is output as height.Thereby the input of the clock of NAND gate 22 effectively, and the clock that outputs to state machine 23 is effective, and state machine raises the centre frequency of VCO according to the switching capacity load of input M_D control minimizing VCO.

Fig. 3 is back the structured flowchart of stagnant comparator 20.Therefore control voltage Vc need introduce back stagnating to eliminate these uncertain switch behaviors that produces because the switching characteristic of charge pump and the transient process of locking can produce ripple in comparator 20.NMOS pipe nm1 and nm2 are that the difference input is right, and the grid of PMOS pipe pm3 is connected with drain electrode, and link to each other with NMOS pipe nm1 drain electrode, are its load; The grid of PMOS pipe pm4 is connected with drain electrode, and links to each other with NMOS pipe nm2 drain electrode, is its load.The grid of PMOS pipe pm1 and the drain electrode of pm4 are joined, and receive the drain electrode of nm2; The grid of PMOS pipe pm2 and the drain electrode of pm3 are joined, and receive the drain electrode of nm1.Pm1 and pm2 have formed cross coupling structure like this, produce returning of comparator with PMOS pipe pm3 and pm4 and stagnate, and the size of returning stagnant voltage is by PMOS pipe pm2 and pm3, or the size of pm1 and pm4 determines, and relevant with the deflection current of differential pair.The output of the nm1 of differential pair is connected to the grid of PMOS pipe pm5, and the output of the nm2 of differential pair is connected to the grid of PMOS pipe pm6.The grid of NMOS pipe nm3 links to each other with drain electrode, and is connected with the drain electrode of PMOS pipe pm5.The grid of NMOS pipe nm4 is connected to the grid of nm3, and its drain electrode then links to each other with the drain electrode of PMOS pipe pm6.The drain electrode of PMOS pipe pm6 links to each other with the input of reverser 31.Like this, NMOS pipe nm3 and nm4, PMOS pipe pm5 and pm6 convert the output of differential pair tube nm1 and nm2 to single-ended output together, and this output is converted to high-low level through reverser 31.

Fig. 4 is the schematic block diagram of switching capacity adjustment state machine 23.When input clock is effective, if M_U is a high level, show that then control voltage Vc is too high, select logic module 44, select the upwards output of counter logic module (up_logic) 42, switching capacity adjustment state machine 23 is with upwards counter mode work.Along with output D＜3:0 increase, the centre frequency of switching capacity voltage controlled oscillator 12 will descend; If M_U is a low level, show that then control voltage Vc is low excessively, select logic module 44 to select the output of downward counter logic module (down_logic) 43, switching capacity adjustment state machine 23 is with downward counter mode work.Along with output D＜3:0 minimizing, the centre frequency of switching capacity voltage controlled oscillator 12 will rise.Wherein 4 registers 41 are used for the internal state of memory state machine, and their initial condition is set at when the circuit power-up initializing＜and 1000 〉.

Fig. 5 is the state transition graph of switching capacity adjustment state machine 23.Upwards the logical relation of counter logic 42 and downward counter logic 43 can obtain from this state transition graph.In state transition graph, signal pwr_on indication circuit power-up initializing signal, this moment, circuit state was S8.When M_U is high level, state will progressively increase, until state S16, if M_U this moment still is high, then state machine will be parked in this state, until M_D is a high level.When M_D is high level, state will successively decrease, until state S0, if this moment, M_D still was a high level, then state machine will be parked in this state, until M_U is a high level.

Claims

1, a kind of phase locking loop frequency synthesizer switch capacitor auto-adjusting circuit, it is characterized in that connecting to form through circuit by two state machines (23) of taking back stagnant comparator (20) and being used for by-pass cock electric capacity, wherein, voltage Vc is controlled in being input as of two comparators (20), and be respectively equipped with high threshold voltage Vref_H and low threshold voltage Vref_L, their output M_U and M_D be or the input of door (21), clock signal clk with or the output of door (21) as two inputs of NAND gate (22); Take back stagnant comparator (20) for two and be used for detecting control voltage Vc:

When control voltage Vc is between high and low threshold voltage Vref_H, the Vref_L, two comparators (20) are output as low level, thereby or the output of door (21) also is low, and the output of the clock of shielding NAND gate (22) input CLK, NAND gate (22) keeps high level, the no clock input of state machine (23); When controlling voltage Vc greater than high threshold level Vref_H, high threshold detection comparator output M_U is high, or door (21) also is output as height, thereby the input of the clock of NAND gate (22) effectively, the output clock is to state machine (23), and state machine (23) work is according to input M_U, control increases the switching capacity load of VCO, and the centre frequency of VCO is reduced; When controlling voltage Vc less than threshold level Vref_L, high threshold detection comparator output M_D is high, same or door (21) is output as height, thereby the input of the clock of NAND gate (22) effectively, the clock that outputs to state machine (23) is effective, state machine (23) raises the centre frequency of VCO according to the switching capacity load of input M_D control minimizing VCO.

2, circuit according to claim 1 is characterized in that said time stagnant comparator (20) comprises that a difference input of being made up of NMOS pipe nm1 and nm2 is right, and the grid of PMOS pipe pm3 is connected with drain electrode, and manages nm1 with NMOS and drain and link to each other, and is its load; The grid of PMOS pipe pm4 is connected with drain electrode, and links to each other with NMOS pipe nm2 drain electrode, is its load; The grid of PMOS pipe pm1 and the drain electrode of pm4 are joined, and receive the drain electrode of nm2; The grid of PMOS pipe pm2 and the drain electrode of pm3 are joined, and the drain electrode of receiving nm1, pm1 and pm2 have formed cross coupling structure like this, producing returning of comparator with PMOS pipe pm3 and pm4 stagnates, the size of returning stagnant voltage is by PMOS pipe pm2 and pm3, or it is the size of pm1 and pm4 is definite, and relevant with the deflection current of differential pair; The output of the nm1 of differential pair is connected to the grid of PMOS pipe pm5, and the output of the nm2 of differential pair is connected to the grid of PMOS pipe pm6; The grid of NMOS pipe nm3 links to each other with drain electrode, and is connected with the drain electrode of PMOS pipe pm5; The grid of NMOS pipe nm4 is connected to the grid of nm3, and its drain electrode then links to each other with the drain electrode of PMOS pipe pm6; The drain electrode of PMOS pipe pm6 links to each other with the input of reverser (31); Like this, NMOS pipe nm3 and nm4, PMOS pipe pm5 and pm6 convert the output of differential pair tube nm1 and nm2 to single-ended output together, and this output is converted to high level or low level through reverser (31).

3, circuit according to claim 1 is characterized in that said state machine (23) is by 4 registers (41) of the parallel connection that is used to store internal state, computerlogic module (42) and computer logic module (43) and selection logic module (44) connect and compose through circuit upwards downwards; Register (41) data input D is for selecting the output of logic module (44), and the output of register (41) is respectively the direction signal QB of Q and Q, and Q and QB are simultaneously as upwards computerlogic module (42) and the input of computer logic module (43) downwards; Upwards computerlogic module (42) and output two groups of inputs of conduct selection logic module (44) respectively of computer logic module (43) downwards, selecting the selection control signal of logic module (44) is M_U; When M_U was high level, select logic module (44) will select to make progress signal that computerlogic module (42) sends here was as output; Otherwise, when M_U is low level, select logic module (44) will select signal that downward computerlogic module (43) sends here as output.